1# Format of file 2# <reg-name> <CRn> <opc1> <CRm> <opc2> <Type> <Description> 3# lines beginning with '@' will be printed as additional comments 4 5@ Based on register description in 6@ ARM Architecture Reference Manual 7@ ARMv7-A and ARMv7-R edition 8@ Issue C.c 9@ 10 11@ B3.18.1 Identification registers, functional group 12AIDR c0 1 c0 7 RO IMPLEMENTATION DEFINED Auxiliary ID Register 13CCSIDR c0 1 c0 0 RO Cache Size ID Registers 14CLIDR c0 1 c0 1 RO Cache Level ID Register 15CSSELR c0 2 c0 0 RW Cache Size Selection Register 16CTR c0 0 c0 1 RO Cache Type Register 17ID_AFR0 c0 0 c1 3 RO Auxiliary Feature Register 0 18ID_DFR0 c0 0 c1 2 RO Debug Feature Register 0 19ID_ISAR0 c0 0 c2 0 RO Instruction Set Attribute Register 0 20ID_ISAR1 c0 0 c2 1 RO Instruction Set Attribute Register 1 21ID_ISAR2 c0 0 c2 2 RO Instruction Set Attribute Register 2 22ID_ISAR3 c0 0 c2 3 RO Instruction Set Attribute Register 3 23ID_ISAR4 c0 0 c2 4 RO Instruction Set Attribute Register 4 24ID_ISAR5 c0 0 c2 5 RO Instruction Set Attribute Register 5 25ID_MMFR0 c0 0 c1 4 RO Memory Model Feature Register 0 26ID_MMFR1 c0 0 c1 5 RO Memory Model Feature Register 1 27ID_MMFR2 c0 0 c1 6 RO Memory Model Feature Register 2 28ID_MMFR3 c0 0 c1 7 RO Memory Model Feature Register 3 29ID_PFR0 c0 0 c1 0 RO Processor Feature Register 0 30ID_PFR1 c0 0 c1 1 RO Processor Feature Register 1 31MIDR c0 0 c0 0 RO Main ID Register 32MPIDR c0 0 c0 5 RO Multiprocessor Affinity Register 33REVIDR c0 0 c0 6 RO Revision ID Register 34TCMTR c0 0 c0 2 RO TCM Type Register 35TLBTR c0 0 c0 3 RO TLB Type Register 36 37@ B3.18.2 Virtual memory control registers, functional group 38AMAIR0 c10 0 c3 0 RW Auxiliary Memory Attribute Indirection Register 0 39AMAIR1 c10 0 c3 1 RW Auxiliary Memory Attribute Indirection Register 1 40CONTEXTIDR c13 0 c0 1 RW Context ID Register 41DACR c3 0 c0 0 RW Domain Access Control Register 42MAIR0 c10 0 c2 0 RW Memory Attribute Indirection Register 0 43MAIR1 c10 0 c2 1 RW Memory Attribute Indirection Register 1 44NMRR c10 0 c2 1 RW Normal Memory Remap Register 45PRRR c10 0 c2 0 RW Primary Region Remap Register 46SCTLR c1 0 c0 0 RW System Control Register 47TTBCR c2 0 c0 2 RW Translation Table Base Control Register 48TTBR0 c2 0 c0 0 RW Translation Table Base Register 0 49TTBR0_64bit - 0 c2 - RW Translation Table Base Register 0 50TTBR1 c2 0 c0 1 RW Translation Table Base Register 1 51TTBR1_64bit - 1 c2 - RW Translation Table Base Register 1 52 53@ B3.18.3 PL1 Fault handling registers, functional group 54ADFSR c5 0 c1 0 RW Auxiliary Data Fault Status Register 55AIFSR c5 0 c1 1 RW Auxiliary Instruction Fault Status Register 56DFAR c6 0 c0 0 RW Data Fault Address Register 57DFSR c5 0 c0 0 RW Data Fault Status Register 58IFAR c6 0 c0 2 RW Instruction Fault Address Register 59IFSR c5 0 c0 1 RW Instruction Fault Status Register 60 61@ B3.18.4 Other system control registers, functional group 62ACTLR c1 0 c0 1 RW IMPLEMENTATION DEFINED Auxiliary Control Register 63CPACR c1 0 c0 2 RW Coprocessor Access Control Register 64FCSEIDR c13 0 c0 0 RW FCSE Process ID Register 65 66@ B3.18.6 Cache maintenance operations, functional group, VMSA 67BPIALL c7 0 c5 6 WOD Branch predictor invalidate all 68BPIALLIS c7 0 c1 6 WOD Branch predictor invalidate all IS 69BPIMVA c7 0 c5 7 WO Branch predictor invalidate by MVA 70DCCIMVAC c7 0 c14 1 WO Data cache clean and invalidate by MVA PoC 71DCCISW c7 0 c14 2 WO Data cache clean and invalidate by set/way 72DCCMVAC c7 0 c10 1 WO Data cache clean by MVA PoC 73DCCMVAU c7 0 c11 1 WO Data cache clean by MVA PoU 74DCCSW c7 0 c10 2 WO Data cache clean by set/way 75DCIMVAC c7 0 c6 1 WO Data cache invalidate by MVA PoC 76DCISW c7 0 c6 2 WO Data cache invalidate by set/way 77ICIALLU c7 0 c5 0 WOD Instruction cache invalidate all PoU 78ICIALLUIS c7 0 c1 0 WOD Instruction cache invalidate all PoU, IS 79ICIMVAU c7 0 c5 1 WO Instruction cache invalidate by MVA PoU 80 81@ B3.18.7 TLB maintenance operations, functional group 82TLBIALL c8 0 c7 0 WOD Invalidate entire unified TLB 83TLBIALLIS c8 0 c3 0 WOD Invalidate entire unified TLB IS 84TLBIASID c8 0 c7 2 WO Invalidate unified TLB by ASID 85TLBIASIDIS c8 0 c3 2 WO Invalidate unified TLB by ASID IS 86TLBIMVAA c8 0 c7 3 WO Invalidate unified TLB by MVA, all ASID 87TLBIMVAAIS c8 0 c3 3 WO Invalidate unified TLB by MVA, all ASID IS 88TLBIMVA c8 0 c7 1 WO Invalidate unified TLB by MVA 89TLBIMVAIS c8 0 c3 1 WO Invalidate unified TLB by MVA IS 90 91@ B3.18.8 Address translation operations, functional group 92ATS12NSOPR c7 0 c8 4 WO Stages 1 and 2 Non-secure only PL1 read 93ATS12NSOPW c7 0 c8 5 WO Stages 1 and 2 Non-secure only PL1 write 94ATS12NSOUR c7 0 c8 6 WO Stages 1 and 2 Non-secure only unprivileged read 95ATS12NSOUW c7 0 c8 7 WO Stages 1 and 2 Non-secure only unprivileged write 96ATS1CPR c7 0 c8 0 WO Stage 1 Current state PL1 read 97ATS1CPW c7 0 c8 1 WO Stage 1 Current state PL1 write 98ATS1CUR c7 0 c8 2 WO Stage 1 Current state unprivileged read 99ATS1CUW c7 0 c8 3 WO Stage 1 Current state unprivileged write 100ATS1HR c7 4 c8 0 WO Stage 1 Hyp mode read 101ATS1HW c7 4 c8 1 WO Stage 1 Hyp mode write 102PAR32 c7 0 c4 0 RW Physical Address Register 103PAR64 - 0 c7 - RW Physical Address Register 104 105@ B3.18.9 Miscellaneous operations, functional group 106TPIDRPRW c13 0 c0 4 RW PL1 only Thread ID Register 107TPIDRURO c13 0 c0 3 RW PL0 User Read-Only Thread ID Register 108TPIDRURW c13 0 c0 2 RW PL0 User Read/Write Thread ID Register 109 110@ B3.18.11 Security Extensions registers, functional group 111ISR c12 0 c1 0 RO Interrupt Status Register 112MVBAR c12 0 c0 1 RW Monitor Vector Base Address Register 113NSACR c1 0 c1 2 RW Non-Secure Access Control Register 114SCR c1 0 c1 0 RW Secure Configuration Register 115SDER c1 0 c1 1 RW Secure Debug Enable Register 116VBAR c12 0 c0 0 RW Vector Base Address Register 117 118@ B8.2 Generic Timer registers summary 119CNTFRQ c14 0 c0 0 RW Counter Frequency register 120CNTPCT - 0 c14 - RO Physical Count register 121CNTKCTL c14 0 c1 0 RW Timer PL1 Control register 122CNTP_TVAL c14 0 c2 0 RW PL1 Physical TimerValue register 123CNTP_CTL c14 0 c2 1 RW PL1 Physical Timer Control register 124CNTV_TVAL c14 0 c3 0 RW Virtual TimerValue register 125CNTV_CTL c14 0 c3 1 RW Virtual Timer Control register 126CNTVCT - 1 c14 - RO Virtual Count register 127CNTP_CVAL - 2 c14 - RW PL1 Physical Timer CompareValue register 128CNTV_CVAL - 3 c14 - RW Virtual Timer CompareValue register 129CNTVOFF - 4 c14 - RW Virtual Offset register 130 131@ Table C12-7 Performance Monitors register summary 132PMCR c9 0 c12 0 RW Performance Monitors Control Register 133PMCNTENSET c9 0 c12 1 RW Performance Monitors Count Enable Set register 134PMCNTENCLR c9 0 c12 2 RW Performance Monitors Count Enable Clear register 135PMOVSR c9 0 c12 3 RW Performance Monitors Overflow Flag Status Register 136PMSWINC c9 0 c12 4 WO Performance Monitors Software Increment register 137PMSELR c9 0 c12 5 RW Performance Monitors Event Counter Selection Register 138PMCEID0 c9 0 c12 6 RO Performance Monitors Common Event Identification reg 0 139PMCEID1 c9 0 c12 7 RO Performance Monitors Common Event Identification reg 1 140PMCCNTR c9 0 c13 0 RW Performance Monitors Cycle Count Register 141PMXEVTYPER c9 0 c13 1 RW Performance Monitors Event Type Select Register 142PMXEVCNTR c9 0 c13 2 RW Performance Monitors Event Count Register 143PMUSERENR c9 0 c14 0 RW Performance Monitors User Enable Register 144PMINTENSET c9 0 c14 1 RW Performance Monitors Interrupt Enable Set register 145PMINTENCLR c9 0 c14 2 RW Performance Monitors Interrupt Enable Clear register 146PMOVSSET c9 0 c14 3 RW Performance Monitors Overflow Flag Status Set register 147