1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2015-2021, Linaro Limited 4 */ 5 6 #include <arm.h> 7 #include <kernel/abort.h> 8 #include <kernel/linker.h> 9 #include <kernel/misc.h> 10 #include <kernel/panic.h> 11 #include <kernel/tee_ta_manager.h> 12 #include <kernel/thread_private.h> 13 #include <kernel/user_mode_ctx.h> 14 #include <mm/core_mmu.h> 15 #include <mm/mobj.h> 16 #include <mm/tee_pager.h> 17 #include <tee/tee_svc.h> 18 #include <trace.h> 19 #include <unw/unwind.h> 20 21 enum fault_type { 22 FAULT_TYPE_USER_MODE_PANIC, 23 FAULT_TYPE_USER_MODE_VFP, 24 FAULT_TYPE_PAGEABLE, 25 FAULT_TYPE_IGNORE, 26 }; 27 28 #ifdef CFG_UNWIND 29 30 #ifdef ARM32 31 /* 32 * Kernel or user mode unwind (32-bit execution state). 33 */ 34 static void __print_stack_unwind(struct abort_info *ai) 35 { 36 struct unwind_state_arm32 state = { }; 37 uint32_t mode = ai->regs->spsr & CPSR_MODE_MASK; 38 uint32_t sp = 0; 39 uint32_t lr = 0; 40 41 assert(!abort_is_user_exception(ai)); 42 43 if (mode == CPSR_MODE_SYS) { 44 sp = ai->regs->usr_sp; 45 lr = ai->regs->usr_lr; 46 } else { 47 sp = read_mode_sp(mode); 48 lr = read_mode_lr(mode); 49 } 50 51 memset(&state, 0, sizeof(state)); 52 state.registers[0] = ai->regs->r0; 53 state.registers[1] = ai->regs->r1; 54 state.registers[2] = ai->regs->r2; 55 state.registers[3] = ai->regs->r3; 56 state.registers[4] = ai->regs->r4; 57 state.registers[5] = ai->regs->r5; 58 state.registers[6] = ai->regs->r6; 59 state.registers[7] = ai->regs->r7; 60 state.registers[8] = ai->regs->r8; 61 state.registers[9] = ai->regs->r9; 62 state.registers[10] = ai->regs->r10; 63 state.registers[11] = ai->regs->r11; 64 state.registers[13] = sp; 65 state.registers[14] = lr; 66 state.registers[15] = ai->pc; 67 68 print_stack_arm32(&state, thread_stack_start(), thread_stack_size()); 69 } 70 #endif /* ARM32 */ 71 72 #ifdef ARM64 73 /* Kernel mode unwind (64-bit execution state) */ 74 static void __print_stack_unwind(struct abort_info *ai) 75 { 76 struct unwind_state_arm64 state = { 77 .pc = ai->regs->elr, 78 .fp = ai->regs->x29, 79 }; 80 81 print_stack_arm64(&state, thread_stack_start(), thread_stack_size()); 82 } 83 #endif /*ARM64*/ 84 85 #else /* CFG_UNWIND */ 86 static void __print_stack_unwind(struct abort_info *ai __unused) 87 { 88 } 89 #endif /* CFG_UNWIND */ 90 91 static __maybe_unused const char *abort_type_to_str(uint32_t abort_type) 92 { 93 if (abort_type == ABORT_TYPE_DATA) 94 return "data"; 95 if (abort_type == ABORT_TYPE_PREFETCH) 96 return "prefetch"; 97 return "undef"; 98 } 99 100 static __maybe_unused const char *fault_to_str(uint32_t abort_type, 101 uint32_t fault_descr) 102 { 103 /* fault_descr is only valid for data or prefetch abort */ 104 if (abort_type != ABORT_TYPE_DATA && abort_type != ABORT_TYPE_PREFETCH) 105 return ""; 106 107 switch (core_mmu_get_fault_type(fault_descr)) { 108 case CORE_MMU_FAULT_ALIGNMENT: 109 return " (alignment fault)"; 110 case CORE_MMU_FAULT_TRANSLATION: 111 return " (translation fault)"; 112 case CORE_MMU_FAULT_READ_PERMISSION: 113 return " (read permission fault)"; 114 case CORE_MMU_FAULT_WRITE_PERMISSION: 115 return " (write permission fault)"; 116 default: 117 return ""; 118 } 119 } 120 121 static __maybe_unused void 122 __print_abort_info(struct abort_info *ai __maybe_unused, 123 const char *ctx __maybe_unused) 124 { 125 __maybe_unused size_t core_pos = 0; 126 #ifdef ARM32 127 uint32_t mode = ai->regs->spsr & CPSR_MODE_MASK; 128 __maybe_unused uint32_t sp = 0; 129 __maybe_unused uint32_t lr = 0; 130 131 if (mode == CPSR_MODE_USR || mode == CPSR_MODE_SYS) { 132 sp = ai->regs->usr_sp; 133 lr = ai->regs->usr_lr; 134 core_pos = thread_get_tsd()->abort_core; 135 } else { 136 sp = read_mode_sp(mode); 137 lr = read_mode_lr(mode); 138 core_pos = get_core_pos(); 139 } 140 #endif /*ARM32*/ 141 #ifdef ARM64 142 if (abort_is_user_exception(ai)) 143 core_pos = thread_get_tsd()->abort_core; 144 else 145 core_pos = get_core_pos(); 146 #endif /*ARM64*/ 147 148 EMSG_RAW(""); 149 EMSG_RAW("%s %s-abort at address 0x%" PRIxVA "%s", 150 ctx, abort_type_to_str(ai->abort_type), ai->va, 151 fault_to_str(ai->abort_type, ai->fault_descr)); 152 #ifdef ARM32 153 EMSG_RAW(" fsr 0x%08x ttbr0 0x%08x ttbr1 0x%08x cidr 0x%X", 154 ai->fault_descr, read_ttbr0(), read_ttbr1(), 155 read_contextidr()); 156 EMSG_RAW(" cpu #%zu cpsr 0x%08x", 157 core_pos, ai->regs->spsr); 158 EMSG_RAW(" r0 0x%08x r4 0x%08x r8 0x%08x r12 0x%08x", 159 ai->regs->r0, ai->regs->r4, ai->regs->r8, ai->regs->ip); 160 EMSG_RAW(" r1 0x%08x r5 0x%08x r9 0x%08x sp 0x%08x", 161 ai->regs->r1, ai->regs->r5, ai->regs->r9, sp); 162 EMSG_RAW(" r2 0x%08x r6 0x%08x r10 0x%08x lr 0x%08x", 163 ai->regs->r2, ai->regs->r6, ai->regs->r10, lr); 164 EMSG_RAW(" r3 0x%08x r7 0x%08x r11 0x%08x pc 0x%08x", 165 ai->regs->r3, ai->regs->r7, ai->regs->r11, ai->pc); 166 #endif /*ARM32*/ 167 #ifdef ARM64 168 EMSG_RAW(" esr 0x%08x ttbr0 0x%08" PRIx64 " ttbr1 0x%08" PRIx64 169 " cidr 0x%X", ai->fault_descr, read_ttbr0_el1(), 170 read_ttbr1_el1(), read_contextidr_el1()); 171 EMSG_RAW(" cpu #%zu cpsr 0x%08x", 172 core_pos, (uint32_t)ai->regs->spsr); 173 EMSG_RAW(" x0 %016" PRIx64 " x1 %016" PRIx64, 174 ai->regs->x0, ai->regs->x1); 175 EMSG_RAW(" x2 %016" PRIx64 " x3 %016" PRIx64, 176 ai->regs->x2, ai->regs->x3); 177 EMSG_RAW(" x4 %016" PRIx64 " x5 %016" PRIx64, 178 ai->regs->x4, ai->regs->x5); 179 EMSG_RAW(" x6 %016" PRIx64 " x7 %016" PRIx64, 180 ai->regs->x6, ai->regs->x7); 181 EMSG_RAW(" x8 %016" PRIx64 " x9 %016" PRIx64, 182 ai->regs->x8, ai->regs->x9); 183 EMSG_RAW(" x10 %016" PRIx64 " x11 %016" PRIx64, 184 ai->regs->x10, ai->regs->x11); 185 EMSG_RAW(" x12 %016" PRIx64 " x13 %016" PRIx64, 186 ai->regs->x12, ai->regs->x13); 187 EMSG_RAW(" x14 %016" PRIx64 " x15 %016" PRIx64, 188 ai->regs->x14, ai->regs->x15); 189 EMSG_RAW(" x16 %016" PRIx64 " x17 %016" PRIx64, 190 ai->regs->x16, ai->regs->x17); 191 EMSG_RAW(" x18 %016" PRIx64 " x19 %016" PRIx64, 192 ai->regs->x18, ai->regs->x19); 193 EMSG_RAW(" x20 %016" PRIx64 " x21 %016" PRIx64, 194 ai->regs->x20, ai->regs->x21); 195 EMSG_RAW(" x22 %016" PRIx64 " x23 %016" PRIx64, 196 ai->regs->x22, ai->regs->x23); 197 EMSG_RAW(" x24 %016" PRIx64 " x25 %016" PRIx64, 198 ai->regs->x24, ai->regs->x25); 199 EMSG_RAW(" x26 %016" PRIx64 " x27 %016" PRIx64, 200 ai->regs->x26, ai->regs->x27); 201 EMSG_RAW(" x28 %016" PRIx64 " x29 %016" PRIx64, 202 ai->regs->x28, ai->regs->x29); 203 EMSG_RAW(" x30 %016" PRIx64 " elr %016" PRIx64, 204 ai->regs->x30, ai->regs->elr); 205 EMSG_RAW(" sp_el0 %016" PRIx64, ai->regs->sp_el0); 206 #endif /*ARM64*/ 207 } 208 209 /* 210 * Print abort info and (optionally) stack dump to the console 211 * @ai kernel-mode abort info. 212 * @stack_dump true to show a stack trace 213 */ 214 static void __abort_print(struct abort_info *ai, bool stack_dump) 215 { 216 assert(!abort_is_user_exception(ai)); 217 218 __print_abort_info(ai, "Core"); 219 220 if (stack_dump) { 221 trace_printf_helper_raw(TRACE_ERROR, true, 222 "TEE load address @ %#"PRIxVA, 223 VCORE_START_VA); 224 __print_stack_unwind(ai); 225 } 226 } 227 228 void abort_print(struct abort_info *ai) 229 { 230 __abort_print(ai, false); 231 } 232 233 void abort_print_error(struct abort_info *ai) 234 { 235 __abort_print(ai, true); 236 } 237 238 /* This function must be called from a normal thread */ 239 void abort_print_current_ts(void) 240 { 241 struct thread_specific_data *tsd = thread_get_tsd(); 242 struct abort_info ai = { }; 243 struct ts_session *s = ts_get_current_session(); 244 245 ai.abort_type = tsd->abort_type; 246 ai.fault_descr = tsd->abort_descr; 247 ai.va = tsd->abort_va; 248 ai.pc = tsd->abort_regs.elr; 249 ai.regs = &tsd->abort_regs; 250 251 if (ai.abort_type != ABORT_TYPE_USER_MODE_PANIC) 252 __print_abort_info(&ai, "User mode"); 253 254 s->ctx->ops->dump_state(s->ctx); 255 256 #if defined(CFG_FTRACE_SUPPORT) 257 if (s->ctx->ops->dump_ftrace) { 258 s->fbuf = NULL; 259 s->ctx->ops->dump_ftrace(s->ctx); 260 } 261 #endif 262 } 263 264 static void save_abort_info_in_tsd(struct abort_info *ai) 265 { 266 struct thread_specific_data *tsd = thread_get_tsd(); 267 268 tsd->abort_type = ai->abort_type; 269 tsd->abort_descr = ai->fault_descr; 270 tsd->abort_va = ai->va; 271 tsd->abort_regs = *ai->regs; 272 tsd->abort_core = get_core_pos(); 273 } 274 275 #ifdef ARM32 276 static void set_abort_info(uint32_t abort_type, struct thread_abort_regs *regs, 277 struct abort_info *ai) 278 { 279 switch (abort_type) { 280 case ABORT_TYPE_DATA: 281 ai->fault_descr = read_dfsr(); 282 ai->va = read_dfar(); 283 break; 284 case ABORT_TYPE_PREFETCH: 285 ai->fault_descr = read_ifsr(); 286 ai->va = read_ifar(); 287 break; 288 default: 289 ai->fault_descr = 0; 290 ai->va = regs->elr; 291 break; 292 } 293 ai->abort_type = abort_type; 294 ai->pc = regs->elr; 295 ai->regs = regs; 296 } 297 #endif /*ARM32*/ 298 299 #ifdef ARM64 300 static void set_abort_info(uint32_t abort_type __unused, 301 struct thread_abort_regs *regs, struct abort_info *ai) 302 { 303 ai->fault_descr = read_esr_el1(); 304 switch ((ai->fault_descr >> ESR_EC_SHIFT) & ESR_EC_MASK) { 305 case ESR_EC_IABT_EL0: 306 case ESR_EC_IABT_EL1: 307 ai->abort_type = ABORT_TYPE_PREFETCH; 308 ai->va = read_far_el1(); 309 break; 310 case ESR_EC_DABT_EL0: 311 case ESR_EC_DABT_EL1: 312 case ESR_EC_SP_ALIGN: 313 ai->abort_type = ABORT_TYPE_DATA; 314 ai->va = read_far_el1(); 315 break; 316 default: 317 ai->abort_type = ABORT_TYPE_UNDEF; 318 ai->va = regs->elr; 319 } 320 ai->pc = regs->elr; 321 ai->regs = regs; 322 } 323 #endif /*ARM64*/ 324 325 #ifdef ARM32 326 static void handle_user_mode_panic(struct abort_info *ai) 327 { 328 /* 329 * It was a user exception, stop user execution and return 330 * to TEE Core. 331 */ 332 ai->regs->r0 = TEE_ERROR_TARGET_DEAD; 333 ai->regs->r1 = true; 334 ai->regs->r2 = 0xdeadbeef; 335 ai->regs->elr = (uint32_t)thread_unwind_user_mode; 336 ai->regs->spsr &= CPSR_FIA; 337 ai->regs->spsr &= ~CPSR_MODE_MASK; 338 ai->regs->spsr |= CPSR_MODE_SVC; 339 /* Select Thumb or ARM mode */ 340 if (ai->regs->elr & 1) 341 ai->regs->spsr |= CPSR_T; 342 else 343 ai->regs->spsr &= ~CPSR_T; 344 } 345 #endif /*ARM32*/ 346 347 #ifdef ARM64 348 static void handle_user_mode_panic(struct abort_info *ai) 349 { 350 uint32_t daif; 351 352 /* 353 * It was a user exception, stop user execution and return 354 * to TEE Core. 355 */ 356 ai->regs->x0 = TEE_ERROR_TARGET_DEAD; 357 ai->regs->x1 = true; 358 ai->regs->x2 = 0xdeadbeef; 359 ai->regs->elr = (vaddr_t)thread_unwind_user_mode; 360 ai->regs->sp_el0 = thread_get_saved_thread_sp(); 361 362 daif = (ai->regs->spsr >> SPSR_32_AIF_SHIFT) & SPSR_32_AIF_MASK; 363 /* XXX what about DAIF_D? */ 364 ai->regs->spsr = SPSR_64(SPSR_64_MODE_EL1, SPSR_64_MODE_SP_EL0, daif); 365 } 366 #endif /*ARM64*/ 367 368 #ifdef CFG_WITH_VFP 369 static void handle_user_mode_vfp(void) 370 { 371 struct ts_session *s = ts_get_current_session(); 372 373 thread_user_enable_vfp(&to_user_mode_ctx(s->ctx)->vfp); 374 } 375 #endif /*CFG_WITH_VFP*/ 376 377 #ifdef CFG_WITH_USER_TA 378 #ifdef ARM32 379 /* Returns true if the exception originated from user mode */ 380 bool abort_is_user_exception(struct abort_info *ai) 381 { 382 return (ai->regs->spsr & ARM32_CPSR_MODE_MASK) == ARM32_CPSR_MODE_USR; 383 } 384 #endif /*ARM32*/ 385 386 #ifdef ARM64 387 /* Returns true if the exception originated from user mode */ 388 bool abort_is_user_exception(struct abort_info *ai) 389 { 390 uint32_t spsr = ai->regs->spsr; 391 392 if (spsr & (SPSR_MODE_RW_32 << SPSR_MODE_RW_SHIFT)) 393 return true; 394 if (((spsr >> SPSR_64_MODE_EL_SHIFT) & SPSR_64_MODE_EL_MASK) == 395 SPSR_64_MODE_EL0) 396 return true; 397 return false; 398 } 399 #endif /*ARM64*/ 400 #else /*CFG_WITH_USER_TA*/ 401 bool abort_is_user_exception(struct abort_info *ai __unused) 402 { 403 return false; 404 } 405 #endif /*CFG_WITH_USER_TA*/ 406 407 #if defined(CFG_WITH_VFP) && defined(CFG_WITH_USER_TA) 408 #ifdef ARM32 409 static bool is_vfp_fault(struct abort_info *ai) 410 { 411 if ((ai->abort_type != ABORT_TYPE_UNDEF) || vfp_is_enabled()) 412 return false; 413 414 /* 415 * Not entirely accurate, but if it's a truly undefined instruction 416 * we'll end up in this function again, except this time 417 * vfp_is_enabled() so we'll return false. 418 */ 419 return true; 420 } 421 #endif /*ARM32*/ 422 423 #ifdef ARM64 424 static bool is_vfp_fault(struct abort_info *ai) 425 { 426 switch ((ai->fault_descr >> ESR_EC_SHIFT) & ESR_EC_MASK) { 427 case ESR_EC_FP_ASIMD: 428 case ESR_EC_AARCH32_FP: 429 case ESR_EC_AARCH64_FP: 430 return true; 431 default: 432 return false; 433 } 434 } 435 #endif /*ARM64*/ 436 #else /*CFG_WITH_VFP && CFG_WITH_USER_TA*/ 437 static bool is_vfp_fault(struct abort_info *ai __unused) 438 { 439 return false; 440 } 441 #endif /*CFG_WITH_VFP && CFG_WITH_USER_TA*/ 442 443 bool abort_is_write_fault(struct abort_info *ai) 444 { 445 #ifdef ARM32 446 unsigned int write_not_read = 11; 447 #endif 448 #ifdef ARM64 449 unsigned int write_not_read = 6; 450 #endif 451 452 return ai->abort_type == ABORT_TYPE_DATA && 453 (ai->fault_descr & BIT(write_not_read)); 454 } 455 456 static enum fault_type get_fault_type(struct abort_info *ai) 457 { 458 if (abort_is_user_exception(ai)) { 459 if (is_vfp_fault(ai)) 460 return FAULT_TYPE_USER_MODE_VFP; 461 #ifndef CFG_WITH_PAGER 462 return FAULT_TYPE_USER_MODE_PANIC; 463 #endif 464 } 465 466 if (thread_is_from_abort_mode()) { 467 abort_print_error(ai); 468 panic("[abort] abort in abort handler (trap CPU)"); 469 } 470 471 if (ai->abort_type == ABORT_TYPE_UNDEF) { 472 if (abort_is_user_exception(ai)) 473 return FAULT_TYPE_USER_MODE_PANIC; 474 abort_print_error(ai); 475 panic("[abort] undefined abort (trap CPU)"); 476 } 477 478 switch (core_mmu_get_fault_type(ai->fault_descr)) { 479 case CORE_MMU_FAULT_ALIGNMENT: 480 if (abort_is_user_exception(ai)) 481 return FAULT_TYPE_USER_MODE_PANIC; 482 abort_print_error(ai); 483 panic("[abort] alignement fault! (trap CPU)"); 484 break; 485 486 case CORE_MMU_FAULT_ACCESS_BIT: 487 if (abort_is_user_exception(ai)) 488 return FAULT_TYPE_USER_MODE_PANIC; 489 abort_print_error(ai); 490 panic("[abort] access bit fault! (trap CPU)"); 491 break; 492 493 case CORE_MMU_FAULT_DEBUG_EVENT: 494 if (!abort_is_user_exception(ai)) 495 abort_print(ai); 496 DMSG("[abort] Ignoring debug event!"); 497 return FAULT_TYPE_IGNORE; 498 499 case CORE_MMU_FAULT_TRANSLATION: 500 case CORE_MMU_FAULT_WRITE_PERMISSION: 501 case CORE_MMU_FAULT_READ_PERMISSION: 502 return FAULT_TYPE_PAGEABLE; 503 504 case CORE_MMU_FAULT_ASYNC_EXTERNAL: 505 if (!abort_is_user_exception(ai)) 506 abort_print(ai); 507 DMSG("[abort] Ignoring async external abort!"); 508 return FAULT_TYPE_IGNORE; 509 510 case CORE_MMU_FAULT_OTHER: 511 default: 512 if (!abort_is_user_exception(ai)) 513 abort_print(ai); 514 DMSG("[abort] Unhandled fault!"); 515 return FAULT_TYPE_IGNORE; 516 } 517 } 518 519 void abort_handler(uint32_t abort_type, struct thread_abort_regs *regs) 520 { 521 struct abort_info ai; 522 bool handled; 523 524 set_abort_info(abort_type, regs, &ai); 525 526 switch (get_fault_type(&ai)) { 527 case FAULT_TYPE_IGNORE: 528 break; 529 case FAULT_TYPE_USER_MODE_PANIC: 530 DMSG("[abort] abort in User mode (TA will panic)"); 531 save_abort_info_in_tsd(&ai); 532 vfp_disable(); 533 handle_user_mode_panic(&ai); 534 break; 535 #ifdef CFG_WITH_VFP 536 case FAULT_TYPE_USER_MODE_VFP: 537 handle_user_mode_vfp(); 538 break; 539 #endif 540 case FAULT_TYPE_PAGEABLE: 541 default: 542 if (thread_get_id_may_fail() < 0) { 543 abort_print_error(&ai); 544 panic("abort outside thread context"); 545 } 546 thread_kernel_save_vfp(); 547 handled = tee_pager_handle_fault(&ai); 548 thread_kernel_restore_vfp(); 549 if (!handled) { 550 if (!abort_is_user_exception(&ai)) { 551 abort_print_error(&ai); 552 panic("unhandled pageable abort"); 553 } 554 DMSG("[abort] abort in User mode (TA will panic)"); 555 save_abort_info_in_tsd(&ai); 556 vfp_disable(); 557 handle_user_mode_panic(&ai); 558 } 559 break; 560 } 561 } 562