1 /* 2 * Copyright (c) 2015, Linaro Limited 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <arm.h> 29 #include <kernel/abort.h> 30 #include <kernel/linker.h> 31 #include <kernel/misc.h> 32 #include <kernel/panic.h> 33 #include <kernel/tee_ta_manager.h> 34 #include <kernel/unwind.h> 35 #include <kernel/user_ta.h> 36 #include <mm/core_mmu.h> 37 #include <mm/mobj.h> 38 #include <mm/tee_pager.h> 39 #include <tee/tee_svc.h> 40 #include <trace.h> 41 42 #include "thread_private.h" 43 44 enum fault_type { 45 FAULT_TYPE_USER_TA_PANIC, 46 FAULT_TYPE_USER_TA_VFP, 47 FAULT_TYPE_PAGEABLE, 48 FAULT_TYPE_IGNORE, 49 }; 50 51 #ifdef CFG_UNWIND 52 53 static void get_current_ta_exidx(uaddr_t *exidx, size_t *exidx_sz) 54 { 55 struct tee_ta_session *s; 56 struct user_ta_ctx *utc; 57 58 if (tee_ta_get_current_session(&s) != TEE_SUCCESS) 59 panic(); 60 61 utc = to_user_ta_ctx(s->ctx); 62 63 /* Only 32-bit TAs use .ARM.exidx/.ARM.extab exception handling */ 64 assert(utc->is_32bit); 65 66 *exidx = utc->exidx_start; /* NULL if TA has no unwind tables */ 67 if (*exidx) 68 *exidx += utc->load_addr; 69 *exidx_sz = utc->exidx_size; 70 } 71 72 #ifdef ARM32 73 74 /* 75 * Kernel or user mode unwind (32-bit execution state). 76 */ 77 static void __print_stack_unwind_arm32(struct abort_info *ai) 78 { 79 struct unwind_state_arm32 state; 80 uaddr_t exidx; 81 size_t exidx_sz; 82 uint32_t mode = ai->regs->spsr & CPSR_MODE_MASK; 83 uint32_t sp; 84 uint32_t lr; 85 86 if (abort_is_user_exception(ai)) { 87 get_current_ta_exidx(&exidx, &exidx_sz); 88 } else { 89 exidx = (vaddr_t)__exidx_start; 90 exidx_sz = (vaddr_t)__exidx_end - (vaddr_t)__exidx_start; 91 } 92 93 if (mode == CPSR_MODE_USR || mode == CPSR_MODE_SYS) { 94 sp = ai->regs->usr_sp; 95 lr = ai->regs->usr_lr; 96 } else { 97 sp = read_mode_sp(mode); 98 lr = read_mode_lr(mode); 99 } 100 101 memset(&state, 0, sizeof(state)); 102 state.registers[0] = ai->regs->r0; 103 state.registers[1] = ai->regs->r1; 104 state.registers[2] = ai->regs->r2; 105 state.registers[3] = ai->regs->r3; 106 state.registers[4] = ai->regs->r4; 107 state.registers[5] = ai->regs->r5; 108 state.registers[6] = ai->regs->r6; 109 state.registers[7] = ai->regs->r7; 110 state.registers[8] = ai->regs->r8; 111 state.registers[9] = ai->regs->r9; 112 state.registers[10] = ai->regs->r10; 113 state.registers[11] = ai->regs->r11; 114 state.registers[13] = sp; 115 state.registers[14] = lr; 116 state.registers[15] = ai->pc; 117 118 print_stack_arm32(TRACE_ERROR, &state, exidx, exidx_sz); 119 } 120 #else /* ARM32 */ 121 122 static void __print_stack_unwind_arm32(struct abort_info *ai __unused) 123 { 124 struct unwind_state_arm32 state; 125 uaddr_t exidx; 126 size_t exidx_sz; 127 128 /* 64-bit kernel, hence 32-bit unwind must be for user mode */ 129 assert(abort_is_user_exception(ai)); 130 131 get_current_ta_exidx(&exidx, &exidx_sz); 132 133 memset(&state, 0, sizeof(state)); 134 state.registers[0] = ai->regs->x0; 135 state.registers[1] = ai->regs->x1; 136 state.registers[2] = ai->regs->x2; 137 state.registers[3] = ai->regs->x3; 138 state.registers[4] = ai->regs->x4; 139 state.registers[5] = ai->regs->x5; 140 state.registers[6] = ai->regs->x6; 141 state.registers[7] = ai->regs->x7; 142 state.registers[8] = ai->regs->x8; 143 state.registers[9] = ai->regs->x9; 144 state.registers[10] = ai->regs->x10; 145 state.registers[11] = ai->regs->x11; 146 147 state.registers[13] = ai->regs->x13; 148 state.registers[14] = ai->regs->x14; 149 state.registers[15] = ai->pc; 150 151 print_stack_arm32(TRACE_ERROR, &state, exidx, exidx_sz); 152 } 153 #endif /* ARM32 */ 154 #ifdef ARM64 155 /* Kernel or user mode unwind (64-bit execution state) */ 156 static void __print_stack_unwind_arm64(struct abort_info *ai) 157 { 158 struct unwind_state_arm64 state; 159 uaddr_t stack; 160 size_t stack_size; 161 162 if (abort_is_user_exception(ai)) { 163 struct tee_ta_session *s; 164 struct user_ta_ctx *utc; 165 166 if (tee_ta_get_current_session(&s) != TEE_SUCCESS) 167 panic(); 168 169 utc = to_user_ta_ctx(s->ctx); 170 /* User stack */ 171 stack = (uaddr_t)utc->mmu->regions[0].va; 172 stack_size = utc->mobj_stack->size; 173 } else { 174 /* Kernel stack */ 175 stack = thread_stack_start(); 176 stack_size = thread_stack_size(); 177 } 178 179 memset(&state, 0, sizeof(state)); 180 state.pc = ai->regs->elr; 181 state.fp = ai->regs->x29; 182 183 print_stack_arm64(TRACE_ERROR, &state, stack, stack_size); 184 } 185 #else 186 static void __print_stack_unwind_arm64(struct abort_info *ai __unused) 187 { 188 189 } 190 #endif /*ARM64*/ 191 #else /* CFG_UNWIND */ 192 static void __print_stack_unwind_arm32(struct abort_info *ai __unused) 193 { 194 } 195 196 static void __print_stack_unwind_arm64(struct abort_info *ai __unused) 197 { 198 } 199 #endif /* CFG_UNWIND */ 200 201 static __maybe_unused const char *abort_type_to_str(uint32_t abort_type) 202 { 203 if (abort_type == ABORT_TYPE_DATA) 204 return "data"; 205 if (abort_type == ABORT_TYPE_PREFETCH) 206 return "prefetch"; 207 return "undef"; 208 } 209 210 static __maybe_unused const char *fault_to_str(uint32_t abort_type, 211 uint32_t fault_descr) 212 { 213 /* fault_descr is only valid for data or prefetch abort */ 214 if (abort_type != ABORT_TYPE_DATA && abort_type != ABORT_TYPE_PREFETCH) 215 return ""; 216 217 switch (core_mmu_get_fault_type(fault_descr)) { 218 case CORE_MMU_FAULT_ALIGNMENT: 219 return " (alignment fault)"; 220 case CORE_MMU_FAULT_TRANSLATION: 221 return " (translation fault)"; 222 case CORE_MMU_FAULT_READ_PERMISSION: 223 return " (read permission fault)"; 224 case CORE_MMU_FAULT_WRITE_PERMISSION: 225 return " (write permission fault)"; 226 default: 227 return ""; 228 } 229 } 230 231 static __maybe_unused void 232 __print_abort_info(struct abort_info *ai __maybe_unused, 233 const char *ctx __maybe_unused) 234 { 235 #ifdef ARM32 236 uint32_t mode = ai->regs->spsr & CPSR_MODE_MASK; 237 __maybe_unused uint32_t sp; 238 __maybe_unused uint32_t lr; 239 240 if (mode == CPSR_MODE_USR || mode == CPSR_MODE_SYS) { 241 sp = ai->regs->usr_sp; 242 lr = ai->regs->usr_lr; 243 } else { 244 sp = read_mode_sp(mode); 245 lr = read_mode_lr(mode); 246 } 247 #endif /*ARM32*/ 248 249 EMSG_RAW(""); 250 EMSG_RAW("%s %s-abort at address 0x%" PRIxVA "%s", 251 ctx, abort_type_to_str(ai->abort_type), ai->va, 252 fault_to_str(ai->abort_type, ai->fault_descr)); 253 #ifdef ARM32 254 EMSG_RAW(" fsr 0x%08x ttbr0 0x%08x ttbr1 0x%08x cidr 0x%X", 255 ai->fault_descr, read_ttbr0(), read_ttbr1(), 256 read_contextidr()); 257 EMSG_RAW(" cpu #%zu cpsr 0x%08x", 258 get_core_pos(), ai->regs->spsr); 259 EMSG_RAW(" r0 0x%08x r4 0x%08x r8 0x%08x r12 0x%08x", 260 ai->regs->r0, ai->regs->r4, ai->regs->r8, ai->regs->ip); 261 EMSG_RAW(" r1 0x%08x r5 0x%08x r9 0x%08x sp 0x%08x", 262 ai->regs->r1, ai->regs->r5, ai->regs->r9, sp); 263 EMSG_RAW(" r2 0x%08x r6 0x%08x r10 0x%08x lr 0x%08x", 264 ai->regs->r2, ai->regs->r6, ai->regs->r10, lr); 265 EMSG_RAW(" r3 0x%08x r7 0x%08x r11 0x%08x pc 0x%08x", 266 ai->regs->r3, ai->regs->r7, ai->regs->r11, ai->pc); 267 #endif /*ARM32*/ 268 #ifdef ARM64 269 EMSG_RAW(" esr 0x%08x ttbr0 0x%08" PRIx64 " ttbr1 0x%08" PRIx64 270 " cidr 0x%X", ai->fault_descr, read_ttbr0_el1(), 271 read_ttbr1_el1(), read_contextidr_el1()); 272 EMSG_RAW(" cpu #%zu cpsr 0x%08x", 273 get_core_pos(), (uint32_t)ai->regs->spsr); 274 EMSG_RAW(" x0 %016" PRIx64 " x1 %016" PRIx64, 275 ai->regs->x0, ai->regs->x1); 276 EMSG_RAW(" x2 %016" PRIx64 " x3 %016" PRIx64, 277 ai->regs->x2, ai->regs->x3); 278 EMSG_RAW(" x4 %016" PRIx64 " x5 %016" PRIx64, 279 ai->regs->x4, ai->regs->x5); 280 EMSG_RAW(" x6 %016" PRIx64 " x7 %016" PRIx64, 281 ai->regs->x6, ai->regs->x7); 282 EMSG_RAW(" x8 %016" PRIx64 " x9 %016" PRIx64, 283 ai->regs->x8, ai->regs->x9); 284 EMSG_RAW(" x10 %016" PRIx64 " x11 %016" PRIx64, 285 ai->regs->x10, ai->regs->x11); 286 EMSG_RAW(" x12 %016" PRIx64 " x13 %016" PRIx64, 287 ai->regs->x12, ai->regs->x13); 288 EMSG_RAW(" x14 %016" PRIx64 " x15 %016" PRIx64, 289 ai->regs->x14, ai->regs->x15); 290 EMSG_RAW(" x16 %016" PRIx64 " x17 %016" PRIx64, 291 ai->regs->x16, ai->regs->x17); 292 EMSG_RAW(" x18 %016" PRIx64 " x19 %016" PRIx64, 293 ai->regs->x18, ai->regs->x19); 294 EMSG_RAW(" x20 %016" PRIx64 " x21 %016" PRIx64, 295 ai->regs->x20, ai->regs->x21); 296 EMSG_RAW(" x22 %016" PRIx64 " x23 %016" PRIx64, 297 ai->regs->x22, ai->regs->x23); 298 EMSG_RAW(" x24 %016" PRIx64 " x25 %016" PRIx64, 299 ai->regs->x24, ai->regs->x25); 300 EMSG_RAW(" x26 %016" PRIx64 " x27 %016" PRIx64, 301 ai->regs->x26, ai->regs->x27); 302 EMSG_RAW(" x28 %016" PRIx64 " x29 %016" PRIx64, 303 ai->regs->x28, ai->regs->x29); 304 EMSG_RAW(" x30 %016" PRIx64 " elr %016" PRIx64, 305 ai->regs->x30, ai->regs->elr); 306 EMSG_RAW(" sp_el0 %016" PRIx64, ai->regs->sp_el0); 307 #endif /*ARM64*/ 308 } 309 310 #if defined(ARM32) 311 static const bool kernel_is32bit = true; 312 #elif defined(ARM64) 313 static const bool kernel_is32bit; 314 #endif 315 316 /* 317 * Print abort info and (optionally) stack dump to the console 318 * @ai user-mode or kernel-mode abort info. If user mode, the current session 319 * must be the one of the TA that caused the abort. 320 * @stack_dump true to show a stack trace 321 */ 322 static void __abort_print(struct abort_info *ai, bool stack_dump) 323 { 324 bool is_32bit; 325 bool paged_ta = false; 326 327 if (abort_is_user_exception(ai)) { 328 struct tee_ta_session *s; 329 struct user_ta_ctx *utc; 330 331 if (tee_ta_get_current_session(&s) != TEE_SUCCESS) 332 panic(); 333 334 utc = to_user_ta_ctx(s->ctx); 335 is_32bit = utc->is_32bit; 336 #ifdef CFG_PAGED_USER_TA 337 /* 338 * We don't want to unwind paged TAs, because we currently 339 * don't handle page faults that could occur when accessing the 340 * TA memory (unwind tables for instance). 341 */ 342 paged_ta = true; 343 #endif 344 345 __print_abort_info(ai, "User TA"); 346 tee_ta_dump_current(); 347 } else { 348 is_32bit = kernel_is32bit; 349 350 __print_abort_info(ai, "Core"); 351 } 352 353 if (!stack_dump || paged_ta) 354 return; 355 356 if (is_32bit) 357 __print_stack_unwind_arm32(ai); 358 else 359 __print_stack_unwind_arm64(ai); 360 } 361 362 void abort_print(struct abort_info *ai) 363 { 364 __abort_print(ai, false); 365 } 366 367 void abort_print_error(struct abort_info *ai) 368 { 369 __abort_print(ai, true); 370 } 371 372 #ifdef ARM32 373 static void set_abort_info(uint32_t abort_type, struct thread_abort_regs *regs, 374 struct abort_info *ai) 375 { 376 switch (abort_type) { 377 case ABORT_TYPE_DATA: 378 ai->fault_descr = read_dfsr(); 379 ai->va = read_dfar(); 380 break; 381 case ABORT_TYPE_PREFETCH: 382 ai->fault_descr = read_ifsr(); 383 ai->va = read_ifar(); 384 break; 385 default: 386 ai->fault_descr = 0; 387 ai->va = regs->elr; 388 break; 389 } 390 ai->abort_type = abort_type; 391 ai->pc = regs->elr; 392 ai->regs = regs; 393 } 394 #endif /*ARM32*/ 395 396 #ifdef ARM64 397 static void set_abort_info(uint32_t abort_type __unused, 398 struct thread_abort_regs *regs, struct abort_info *ai) 399 { 400 ai->fault_descr = read_esr_el1(); 401 switch ((ai->fault_descr >> ESR_EC_SHIFT) & ESR_EC_MASK) { 402 case ESR_EC_IABT_EL0: 403 case ESR_EC_IABT_EL1: 404 ai->abort_type = ABORT_TYPE_PREFETCH; 405 ai->va = read_far_el1(); 406 break; 407 case ESR_EC_DABT_EL0: 408 case ESR_EC_DABT_EL1: 409 case ESR_EC_SP_ALIGN: 410 ai->abort_type = ABORT_TYPE_DATA; 411 ai->va = read_far_el1(); 412 break; 413 default: 414 ai->abort_type = ABORT_TYPE_UNDEF; 415 ai->va = regs->elr; 416 } 417 ai->pc = regs->elr; 418 ai->regs = regs; 419 } 420 #endif /*ARM64*/ 421 422 #ifdef ARM32 423 static void handle_user_ta_panic(struct abort_info *ai) 424 { 425 /* 426 * It was a user exception, stop user execution and return 427 * to TEE Core. 428 */ 429 ai->regs->r0 = TEE_ERROR_TARGET_DEAD; 430 ai->regs->r1 = true; 431 ai->regs->r2 = 0xdeadbeef; 432 ai->regs->elr = (uint32_t)thread_unwind_user_mode; 433 ai->regs->spsr &= CPSR_FIA; 434 ai->regs->spsr &= ~CPSR_MODE_MASK; 435 ai->regs->spsr |= CPSR_MODE_SVC; 436 /* Select Thumb or ARM mode */ 437 if (ai->regs->elr & 1) 438 ai->regs->spsr |= CPSR_T; 439 else 440 ai->regs->spsr &= ~CPSR_T; 441 } 442 #endif /*ARM32*/ 443 444 #ifdef ARM64 445 static void handle_user_ta_panic(struct abort_info *ai) 446 { 447 uint32_t daif; 448 449 /* 450 * It was a user exception, stop user execution and return 451 * to TEE Core. 452 */ 453 ai->regs->x0 = TEE_ERROR_TARGET_DEAD; 454 ai->regs->x1 = true; 455 ai->regs->x2 = 0xdeadbeef; 456 ai->regs->elr = (vaddr_t)thread_unwind_user_mode; 457 ai->regs->sp_el0 = thread_get_saved_thread_sp(); 458 459 daif = (ai->regs->spsr >> SPSR_32_AIF_SHIFT) & SPSR_32_AIF_MASK; 460 /* XXX what about DAIF_D? */ 461 ai->regs->spsr = SPSR_64(SPSR_64_MODE_EL1, SPSR_64_MODE_SP_EL0, daif); 462 } 463 #endif /*ARM64*/ 464 465 #ifdef CFG_WITH_VFP 466 static void handle_user_ta_vfp(void) 467 { 468 struct tee_ta_session *s; 469 470 if (tee_ta_get_current_session(&s) != TEE_SUCCESS) 471 panic(); 472 473 thread_user_enable_vfp(&to_user_ta_ctx(s->ctx)->vfp); 474 } 475 #endif /*CFG_WITH_VFP*/ 476 477 #ifdef CFG_WITH_USER_TA 478 #ifdef ARM32 479 /* Returns true if the exception originated from user mode */ 480 bool abort_is_user_exception(struct abort_info *ai) 481 { 482 return (ai->regs->spsr & ARM32_CPSR_MODE_MASK) == ARM32_CPSR_MODE_USR; 483 } 484 #endif /*ARM32*/ 485 486 #ifdef ARM64 487 /* Returns true if the exception originated from user mode */ 488 bool abort_is_user_exception(struct abort_info *ai) 489 { 490 uint32_t spsr = ai->regs->spsr; 491 492 if (spsr & (SPSR_MODE_RW_32 << SPSR_MODE_RW_SHIFT)) 493 return true; 494 if (((spsr >> SPSR_64_MODE_EL_SHIFT) & SPSR_64_MODE_EL_MASK) == 495 SPSR_64_MODE_EL0) 496 return true; 497 return false; 498 } 499 #endif /*ARM64*/ 500 #else /*CFG_WITH_USER_TA*/ 501 bool abort_is_user_exception(struct abort_info *ai __unused) 502 { 503 return false; 504 } 505 #endif /*CFG_WITH_USER_TA*/ 506 507 #if defined(CFG_WITH_VFP) && defined(CFG_WITH_USER_TA) 508 #ifdef ARM32 509 510 #define T32_INSTR(w1, w0) \ 511 ((((uint32_t)(w0) & 0xffff) << 16) | ((uint32_t)(w1) & 0xffff)) 512 513 #define T32_VTRANS32_MASK T32_INSTR(0xff << 8, (7 << 9) | 1 << 4) 514 #define T32_VTRANS32_VAL T32_INSTR(0xee << 8, (5 << 9) | 1 << 4) 515 516 #define T32_VTRANS64_MASK T32_INSTR((0xff << 8) | (7 << 5), 7 << 9) 517 #define T32_VTRANS64_VAL T32_INSTR((0xec << 8) | (2 << 5), 5 << 9) 518 519 #define T32_VLDST_MASK T32_INSTR((0xff << 8) | (1 << 4), 0) 520 #define T32_VLDST_VAL T32_INSTR( 0xf9 << 8 , 0) 521 522 #define T32_VXLDST_MASK T32_INSTR(0xfc << 8, 7 << 9) 523 #define T32_VXLDST_VAL T32_INSTR(0xec << 8, 5 << 9) 524 525 #define T32_VPROC_MASK T32_INSTR(0xef << 8, 0) 526 #define T32_VPROC_VAL T32_VPROC_MASK 527 528 #define A32_INSTR(x) ((uint32_t)(x)) 529 530 #define A32_VTRANS32_MASK A32_INSTR(SHIFT_U32(0xf, 24) | \ 531 SHIFT_U32(7, 9) | BIT32(4)) 532 #define A32_VTRANS32_VAL A32_INSTR(SHIFT_U32(0xe, 24) | \ 533 SHIFT_U32(5, 9) | BIT32(4)) 534 535 #define A32_VTRANS64_MASK A32_INSTR(SHIFT_U32(0x7f, 21) | SHIFT_U32(7, 9)) 536 #define A32_VTRANS64_VAL A32_INSTR(SHIFT_U32(0x62, 21) | SHIFT_U32(5, 9)) 537 538 #define A32_VLDST_MASK A32_INSTR(SHIFT_U32(0xff, 24) | BIT32(20)) 539 #define A32_VLDST_VAL A32_INSTR(SHIFT_U32(0xf4, 24)) 540 #define A32_VXLDST_MASK A32_INSTR(SHIFT_U32(7, 25) | SHIFT_U32(7, 9)) 541 #define A32_VXLDST_VAL A32_INSTR(SHIFT_U32(6, 25) | SHIFT_U32(5, 9)) 542 543 #define A32_VPROC_MASK A32_INSTR(SHIFT_U32(0x7f, 25)) 544 #define A32_VPROC_VAL A32_INSTR(SHIFT_U32(0x79, 25)) 545 546 static bool is_vfp_fault(struct abort_info *ai) 547 { 548 TEE_Result res; 549 uint32_t instr; 550 551 if ((ai->abort_type != ABORT_TYPE_UNDEF) || vfp_is_enabled()) 552 return false; 553 554 res = tee_svc_copy_from_user(&instr, (void *)ai->pc, sizeof(instr)); 555 if (res != TEE_SUCCESS) 556 return false; 557 558 if (ai->regs->spsr & CPSR_T) { 559 /* Thumb mode */ 560 return ((instr & T32_VTRANS32_MASK) == T32_VTRANS32_VAL) || 561 ((instr & T32_VTRANS64_MASK) == T32_VTRANS64_VAL) || 562 ((instr & T32_VLDST_MASK) == T32_VLDST_VAL) || 563 ((instr & T32_VXLDST_MASK) == T32_VXLDST_VAL) || 564 ((instr & T32_VPROC_MASK) == T32_VPROC_VAL); 565 } else { 566 /* ARM mode */ 567 return ((instr & A32_VTRANS32_MASK) == A32_VTRANS32_VAL) || 568 ((instr & A32_VTRANS64_MASK) == A32_VTRANS64_VAL) || 569 ((instr & A32_VLDST_MASK) == A32_VLDST_VAL) || 570 ((instr & A32_VXLDST_MASK) == A32_VXLDST_VAL) || 571 ((instr & A32_VPROC_MASK) == A32_VPROC_VAL); 572 } 573 } 574 #endif /*ARM32*/ 575 576 #ifdef ARM64 577 static bool is_vfp_fault(struct abort_info *ai) 578 { 579 switch ((ai->fault_descr >> ESR_EC_SHIFT) & ESR_EC_MASK) { 580 case ESR_EC_FP_ASIMD: 581 case ESR_EC_AARCH32_FP: 582 case ESR_EC_AARCH64_FP: 583 return true; 584 default: 585 return false; 586 } 587 } 588 #endif /*ARM64*/ 589 #else /*CFG_WITH_VFP && CFG_WITH_USER_TA*/ 590 static bool is_vfp_fault(struct abort_info *ai __unused) 591 { 592 return false; 593 } 594 #endif /*CFG_WITH_VFP && CFG_WITH_USER_TA*/ 595 596 static enum fault_type get_fault_type(struct abort_info *ai) 597 { 598 if (abort_is_user_exception(ai)) { 599 if (is_vfp_fault(ai)) 600 return FAULT_TYPE_USER_TA_VFP; 601 #ifndef CFG_WITH_PAGER 602 return FAULT_TYPE_USER_TA_PANIC; 603 #endif 604 } 605 606 if (thread_is_from_abort_mode()) { 607 abort_print_error(ai); 608 panic("[abort] abort in abort handler (trap CPU)"); 609 } 610 611 if (ai->abort_type == ABORT_TYPE_UNDEF) { 612 if (abort_is_user_exception(ai)) 613 return FAULT_TYPE_USER_TA_PANIC; 614 abort_print_error(ai); 615 panic("[abort] undefined abort (trap CPU)"); 616 } 617 618 switch (core_mmu_get_fault_type(ai->fault_descr)) { 619 case CORE_MMU_FAULT_ALIGNMENT: 620 if (abort_is_user_exception(ai)) 621 return FAULT_TYPE_USER_TA_PANIC; 622 abort_print_error(ai); 623 panic("[abort] alignement fault! (trap CPU)"); 624 break; 625 626 case CORE_MMU_FAULT_ACCESS_BIT: 627 if (abort_is_user_exception(ai)) 628 return FAULT_TYPE_USER_TA_PANIC; 629 abort_print_error(ai); 630 panic("[abort] access bit fault! (trap CPU)"); 631 break; 632 633 case CORE_MMU_FAULT_DEBUG_EVENT: 634 abort_print(ai); 635 DMSG("[abort] Ignoring debug event!"); 636 return FAULT_TYPE_IGNORE; 637 638 case CORE_MMU_FAULT_TRANSLATION: 639 case CORE_MMU_FAULT_WRITE_PERMISSION: 640 case CORE_MMU_FAULT_READ_PERMISSION: 641 return FAULT_TYPE_PAGEABLE; 642 643 case CORE_MMU_FAULT_ASYNC_EXTERNAL: 644 abort_print(ai); 645 DMSG("[abort] Ignoring async external abort!"); 646 return FAULT_TYPE_IGNORE; 647 648 case CORE_MMU_FAULT_OTHER: 649 default: 650 abort_print(ai); 651 DMSG("[abort] Unhandled fault!"); 652 return FAULT_TYPE_IGNORE; 653 } 654 } 655 656 void abort_handler(uint32_t abort_type, struct thread_abort_regs *regs) 657 { 658 struct abort_info ai; 659 bool handled; 660 661 set_abort_info(abort_type, regs, &ai); 662 663 switch (get_fault_type(&ai)) { 664 case FAULT_TYPE_IGNORE: 665 break; 666 case FAULT_TYPE_USER_TA_PANIC: 667 DMSG("[abort] abort in User mode (TA will panic)"); 668 abort_print_error(&ai); 669 vfp_disable(); 670 handle_user_ta_panic(&ai); 671 break; 672 #ifdef CFG_WITH_VFP 673 case FAULT_TYPE_USER_TA_VFP: 674 handle_user_ta_vfp(); 675 break; 676 #endif 677 case FAULT_TYPE_PAGEABLE: 678 default: 679 thread_kernel_save_vfp(); 680 handled = tee_pager_handle_fault(&ai); 681 thread_kernel_restore_vfp(); 682 if (!handled) { 683 abort_print_error(&ai); 684 if (!abort_is_user_exception(&ai)) 685 panic("unhandled pageable abort"); 686 DMSG("[abort] abort in User mode (TA will panic)"); 687 vfp_disable(); 688 handle_user_ta_panic(&ai); 689 } 690 break; 691 } 692 } 693