1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 */ 5 6 #include <arm.h> 7 #include <kernel/abort.h> 8 #include <kernel/misc.h> 9 #include <kernel/panic.h> 10 #include <kernel/tee_ta_manager.h> 11 #include <kernel/user_mode_ctx.h> 12 #include <mm/core_mmu.h> 13 #include <mm/mobj.h> 14 #include <mm/tee_pager.h> 15 #include <tee/tee_svc.h> 16 #include <trace.h> 17 #include <unw/unwind.h> 18 19 #include "thread_private.h" 20 21 enum fault_type { 22 FAULT_TYPE_USER_MODE_PANIC, 23 FAULT_TYPE_USER_MODE_VFP, 24 FAULT_TYPE_PAGEABLE, 25 FAULT_TYPE_IGNORE, 26 }; 27 28 #ifdef CFG_UNWIND 29 30 #ifdef ARM32 31 /* 32 * Kernel or user mode unwind (32-bit execution state). 33 */ 34 static void __print_stack_unwind(struct abort_info *ai) 35 { 36 struct unwind_state_arm32 state = { }; 37 uint32_t mode = ai->regs->spsr & CPSR_MODE_MASK; 38 uint32_t sp = 0; 39 uint32_t lr = 0; 40 41 assert(!abort_is_user_exception(ai)); 42 43 if (mode == CPSR_MODE_SYS) { 44 sp = ai->regs->usr_sp; 45 lr = ai->regs->usr_lr; 46 } else { 47 sp = read_mode_sp(mode); 48 lr = read_mode_lr(mode); 49 } 50 51 memset(&state, 0, sizeof(state)); 52 state.registers[0] = ai->regs->r0; 53 state.registers[1] = ai->regs->r1; 54 state.registers[2] = ai->regs->r2; 55 state.registers[3] = ai->regs->r3; 56 state.registers[4] = ai->regs->r4; 57 state.registers[5] = ai->regs->r5; 58 state.registers[6] = ai->regs->r6; 59 state.registers[7] = ai->regs->r7; 60 state.registers[8] = ai->regs->r8; 61 state.registers[9] = ai->regs->r9; 62 state.registers[10] = ai->regs->r10; 63 state.registers[11] = ai->regs->r11; 64 state.registers[13] = sp; 65 state.registers[14] = lr; 66 state.registers[15] = ai->pc; 67 68 print_stack_arm32(&state, thread_stack_start(), thread_stack_size()); 69 } 70 #endif /* ARM32 */ 71 72 #ifdef ARM64 73 /* Kernel mode unwind (64-bit execution state) */ 74 static void __print_stack_unwind(struct abort_info *ai) 75 { 76 struct unwind_state_arm64 state = { 77 .pc = ai->regs->elr, 78 .fp = ai->regs->x29, 79 }; 80 81 print_stack_arm64(&state, thread_stack_start(), thread_stack_size()); 82 } 83 #endif /*ARM64*/ 84 85 #else /* CFG_UNWIND */ 86 static void __print_stack_unwind(struct abort_info *ai __unused) 87 { 88 } 89 #endif /* CFG_UNWIND */ 90 91 static __maybe_unused const char *abort_type_to_str(uint32_t abort_type) 92 { 93 if (abort_type == ABORT_TYPE_DATA) 94 return "data"; 95 if (abort_type == ABORT_TYPE_PREFETCH) 96 return "prefetch"; 97 return "undef"; 98 } 99 100 static __maybe_unused const char *fault_to_str(uint32_t abort_type, 101 uint32_t fault_descr) 102 { 103 /* fault_descr is only valid for data or prefetch abort */ 104 if (abort_type != ABORT_TYPE_DATA && abort_type != ABORT_TYPE_PREFETCH) 105 return ""; 106 107 switch (core_mmu_get_fault_type(fault_descr)) { 108 case CORE_MMU_FAULT_ALIGNMENT: 109 return " (alignment fault)"; 110 case CORE_MMU_FAULT_TRANSLATION: 111 return " (translation fault)"; 112 case CORE_MMU_FAULT_READ_PERMISSION: 113 return " (read permission fault)"; 114 case CORE_MMU_FAULT_WRITE_PERMISSION: 115 return " (write permission fault)"; 116 default: 117 return ""; 118 } 119 } 120 121 static __maybe_unused void 122 __print_abort_info(struct abort_info *ai __maybe_unused, 123 const char *ctx __maybe_unused) 124 { 125 __maybe_unused size_t core_pos = 0; 126 #ifdef ARM32 127 uint32_t mode = ai->regs->spsr & CPSR_MODE_MASK; 128 __maybe_unused uint32_t sp = 0; 129 __maybe_unused uint32_t lr = 0; 130 131 if (mode == CPSR_MODE_USR || mode == CPSR_MODE_SYS) { 132 sp = ai->regs->usr_sp; 133 lr = ai->regs->usr_lr; 134 core_pos = thread_get_tsd()->abort_core; 135 } else { 136 sp = read_mode_sp(mode); 137 lr = read_mode_lr(mode); 138 core_pos = get_core_pos(); 139 } 140 #endif /*ARM32*/ 141 #ifdef ARM64 142 if (abort_is_user_exception(ai)) 143 core_pos = thread_get_tsd()->abort_core; 144 else 145 core_pos = get_core_pos(); 146 #endif /*ARM64*/ 147 148 EMSG_RAW(""); 149 EMSG_RAW("%s %s-abort at address 0x%" PRIxVA "%s", 150 ctx, abort_type_to_str(ai->abort_type), ai->va, 151 fault_to_str(ai->abort_type, ai->fault_descr)); 152 #ifdef ARM32 153 EMSG_RAW(" fsr 0x%08x ttbr0 0x%08x ttbr1 0x%08x cidr 0x%X", 154 ai->fault_descr, read_ttbr0(), read_ttbr1(), 155 read_contextidr()); 156 EMSG_RAW(" cpu #%zu cpsr 0x%08x", 157 core_pos, ai->regs->spsr); 158 EMSG_RAW(" r0 0x%08x r4 0x%08x r8 0x%08x r12 0x%08x", 159 ai->regs->r0, ai->regs->r4, ai->regs->r8, ai->regs->ip); 160 EMSG_RAW(" r1 0x%08x r5 0x%08x r9 0x%08x sp 0x%08x", 161 ai->regs->r1, ai->regs->r5, ai->regs->r9, sp); 162 EMSG_RAW(" r2 0x%08x r6 0x%08x r10 0x%08x lr 0x%08x", 163 ai->regs->r2, ai->regs->r6, ai->regs->r10, lr); 164 EMSG_RAW(" r3 0x%08x r7 0x%08x r11 0x%08x pc 0x%08x", 165 ai->regs->r3, ai->regs->r7, ai->regs->r11, ai->pc); 166 #endif /*ARM32*/ 167 #ifdef ARM64 168 EMSG_RAW(" esr 0x%08x ttbr0 0x%08" PRIx64 " ttbr1 0x%08" PRIx64 169 " cidr 0x%X", ai->fault_descr, read_ttbr0_el1(), 170 read_ttbr1_el1(), read_contextidr_el1()); 171 EMSG_RAW(" cpu #%zu cpsr 0x%08x", 172 core_pos, (uint32_t)ai->regs->spsr); 173 EMSG_RAW(" x0 %016" PRIx64 " x1 %016" PRIx64, 174 ai->regs->x0, ai->regs->x1); 175 EMSG_RAW(" x2 %016" PRIx64 " x3 %016" PRIx64, 176 ai->regs->x2, ai->regs->x3); 177 EMSG_RAW(" x4 %016" PRIx64 " x5 %016" PRIx64, 178 ai->regs->x4, ai->regs->x5); 179 EMSG_RAW(" x6 %016" PRIx64 " x7 %016" PRIx64, 180 ai->regs->x6, ai->regs->x7); 181 EMSG_RAW(" x8 %016" PRIx64 " x9 %016" PRIx64, 182 ai->regs->x8, ai->regs->x9); 183 EMSG_RAW(" x10 %016" PRIx64 " x11 %016" PRIx64, 184 ai->regs->x10, ai->regs->x11); 185 EMSG_RAW(" x12 %016" PRIx64 " x13 %016" PRIx64, 186 ai->regs->x12, ai->regs->x13); 187 EMSG_RAW(" x14 %016" PRIx64 " x15 %016" PRIx64, 188 ai->regs->x14, ai->regs->x15); 189 EMSG_RAW(" x16 %016" PRIx64 " x17 %016" PRIx64, 190 ai->regs->x16, ai->regs->x17); 191 EMSG_RAW(" x18 %016" PRIx64 " x19 %016" PRIx64, 192 ai->regs->x18, ai->regs->x19); 193 EMSG_RAW(" x20 %016" PRIx64 " x21 %016" PRIx64, 194 ai->regs->x20, ai->regs->x21); 195 EMSG_RAW(" x22 %016" PRIx64 " x23 %016" PRIx64, 196 ai->regs->x22, ai->regs->x23); 197 EMSG_RAW(" x24 %016" PRIx64 " x25 %016" PRIx64, 198 ai->regs->x24, ai->regs->x25); 199 EMSG_RAW(" x26 %016" PRIx64 " x27 %016" PRIx64, 200 ai->regs->x26, ai->regs->x27); 201 EMSG_RAW(" x28 %016" PRIx64 " x29 %016" PRIx64, 202 ai->regs->x28, ai->regs->x29); 203 EMSG_RAW(" x30 %016" PRIx64 " elr %016" PRIx64, 204 ai->regs->x30, ai->regs->elr); 205 EMSG_RAW(" sp_el0 %016" PRIx64, ai->regs->sp_el0); 206 #endif /*ARM64*/ 207 } 208 209 /* 210 * Print abort info and (optionally) stack dump to the console 211 * @ai kernel-mode abort info. 212 * @stack_dump true to show a stack trace 213 */ 214 static void __abort_print(struct abort_info *ai, bool stack_dump) 215 { 216 assert(!abort_is_user_exception(ai)); 217 218 __print_abort_info(ai, "Core"); 219 220 if (stack_dump) 221 __print_stack_unwind(ai); 222 } 223 224 void abort_print(struct abort_info *ai) 225 { 226 __abort_print(ai, false); 227 } 228 229 void abort_print_error(struct abort_info *ai) 230 { 231 __abort_print(ai, true); 232 } 233 234 /* This function must be called from a normal thread */ 235 void abort_print_current_ta(void) 236 { 237 struct thread_specific_data *tsd = thread_get_tsd(); 238 struct abort_info ai = { }; 239 struct ts_session *s = ts_get_current_session(); 240 241 ai.abort_type = tsd->abort_type; 242 ai.fault_descr = tsd->abort_descr; 243 ai.va = tsd->abort_va; 244 ai.pc = tsd->abort_regs.elr; 245 ai.regs = &tsd->abort_regs; 246 247 if (ai.abort_type != ABORT_TYPE_USER_MODE_PANIC) 248 __print_abort_info(&ai, "User mode"); 249 250 s->ctx->ops->dump_state(s->ctx); 251 252 #if defined(CFG_FTRACE_SUPPORT) 253 if (s->ctx->ops->dump_ftrace) { 254 s->fbuf = NULL; 255 s->ctx->ops->dump_ftrace(s->ctx); 256 } 257 #endif 258 } 259 260 static void save_abort_info_in_tsd(struct abort_info *ai) 261 { 262 struct thread_specific_data *tsd = thread_get_tsd(); 263 264 tsd->abort_type = ai->abort_type; 265 tsd->abort_descr = ai->fault_descr; 266 tsd->abort_va = ai->va; 267 tsd->abort_regs = *ai->regs; 268 tsd->abort_core = get_core_pos(); 269 } 270 271 #ifdef ARM32 272 static void set_abort_info(uint32_t abort_type, struct thread_abort_regs *regs, 273 struct abort_info *ai) 274 { 275 switch (abort_type) { 276 case ABORT_TYPE_DATA: 277 ai->fault_descr = read_dfsr(); 278 ai->va = read_dfar(); 279 break; 280 case ABORT_TYPE_PREFETCH: 281 ai->fault_descr = read_ifsr(); 282 ai->va = read_ifar(); 283 break; 284 default: 285 ai->fault_descr = 0; 286 ai->va = regs->elr; 287 break; 288 } 289 ai->abort_type = abort_type; 290 ai->pc = regs->elr; 291 ai->regs = regs; 292 } 293 #endif /*ARM32*/ 294 295 #ifdef ARM64 296 static void set_abort_info(uint32_t abort_type __unused, 297 struct thread_abort_regs *regs, struct abort_info *ai) 298 { 299 ai->fault_descr = read_esr_el1(); 300 switch ((ai->fault_descr >> ESR_EC_SHIFT) & ESR_EC_MASK) { 301 case ESR_EC_IABT_EL0: 302 case ESR_EC_IABT_EL1: 303 ai->abort_type = ABORT_TYPE_PREFETCH; 304 ai->va = read_far_el1(); 305 break; 306 case ESR_EC_DABT_EL0: 307 case ESR_EC_DABT_EL1: 308 case ESR_EC_SP_ALIGN: 309 ai->abort_type = ABORT_TYPE_DATA; 310 ai->va = read_far_el1(); 311 break; 312 default: 313 ai->abort_type = ABORT_TYPE_UNDEF; 314 ai->va = regs->elr; 315 } 316 ai->pc = regs->elr; 317 ai->regs = regs; 318 } 319 #endif /*ARM64*/ 320 321 #ifdef ARM32 322 static void handle_user_mode_panic(struct abort_info *ai) 323 { 324 /* 325 * It was a user exception, stop user execution and return 326 * to TEE Core. 327 */ 328 ai->regs->r0 = TEE_ERROR_TARGET_DEAD; 329 ai->regs->r1 = true; 330 ai->regs->r2 = 0xdeadbeef; 331 ai->regs->elr = (uint32_t)thread_unwind_user_mode; 332 ai->regs->spsr &= CPSR_FIA; 333 ai->regs->spsr &= ~CPSR_MODE_MASK; 334 ai->regs->spsr |= CPSR_MODE_SVC; 335 /* Select Thumb or ARM mode */ 336 if (ai->regs->elr & 1) 337 ai->regs->spsr |= CPSR_T; 338 else 339 ai->regs->spsr &= ~CPSR_T; 340 } 341 #endif /*ARM32*/ 342 343 #ifdef ARM64 344 static void handle_user_mode_panic(struct abort_info *ai) 345 { 346 uint32_t daif; 347 348 /* 349 * It was a user exception, stop user execution and return 350 * to TEE Core. 351 */ 352 ai->regs->x0 = TEE_ERROR_TARGET_DEAD; 353 ai->regs->x1 = true; 354 ai->regs->x2 = 0xdeadbeef; 355 ai->regs->elr = (vaddr_t)thread_unwind_user_mode; 356 ai->regs->sp_el0 = thread_get_saved_thread_sp(); 357 358 daif = (ai->regs->spsr >> SPSR_32_AIF_SHIFT) & SPSR_32_AIF_MASK; 359 /* XXX what about DAIF_D? */ 360 ai->regs->spsr = SPSR_64(SPSR_64_MODE_EL1, SPSR_64_MODE_SP_EL0, daif); 361 } 362 #endif /*ARM64*/ 363 364 #ifdef CFG_WITH_VFP 365 static void handle_user_mode_vfp(void) 366 { 367 struct ts_session *s = ts_get_current_session(); 368 369 thread_user_enable_vfp(&to_user_mode_ctx(s->ctx)->vfp); 370 } 371 #endif /*CFG_WITH_VFP*/ 372 373 #ifdef CFG_WITH_USER_TA 374 #ifdef ARM32 375 /* Returns true if the exception originated from user mode */ 376 bool abort_is_user_exception(struct abort_info *ai) 377 { 378 return (ai->regs->spsr & ARM32_CPSR_MODE_MASK) == ARM32_CPSR_MODE_USR; 379 } 380 #endif /*ARM32*/ 381 382 #ifdef ARM64 383 /* Returns true if the exception originated from user mode */ 384 bool abort_is_user_exception(struct abort_info *ai) 385 { 386 uint32_t spsr = ai->regs->spsr; 387 388 if (spsr & (SPSR_MODE_RW_32 << SPSR_MODE_RW_SHIFT)) 389 return true; 390 if (((spsr >> SPSR_64_MODE_EL_SHIFT) & SPSR_64_MODE_EL_MASK) == 391 SPSR_64_MODE_EL0) 392 return true; 393 return false; 394 } 395 #endif /*ARM64*/ 396 #else /*CFG_WITH_USER_TA*/ 397 bool abort_is_user_exception(struct abort_info *ai __unused) 398 { 399 return false; 400 } 401 #endif /*CFG_WITH_USER_TA*/ 402 403 #if defined(CFG_WITH_VFP) && defined(CFG_WITH_USER_TA) 404 #ifdef ARM32 405 static bool is_vfp_fault(struct abort_info *ai) 406 { 407 if ((ai->abort_type != ABORT_TYPE_UNDEF) || vfp_is_enabled()) 408 return false; 409 410 /* 411 * Not entirely accurate, but if it's a truly undefined instruction 412 * we'll end up in this function again, except this time 413 * vfp_is_enabled() so we'll return false. 414 */ 415 return true; 416 } 417 #endif /*ARM32*/ 418 419 #ifdef ARM64 420 static bool is_vfp_fault(struct abort_info *ai) 421 { 422 switch ((ai->fault_descr >> ESR_EC_SHIFT) & ESR_EC_MASK) { 423 case ESR_EC_FP_ASIMD: 424 case ESR_EC_AARCH32_FP: 425 case ESR_EC_AARCH64_FP: 426 return true; 427 default: 428 return false; 429 } 430 } 431 #endif /*ARM64*/ 432 #else /*CFG_WITH_VFP && CFG_WITH_USER_TA*/ 433 static bool is_vfp_fault(struct abort_info *ai __unused) 434 { 435 return false; 436 } 437 #endif /*CFG_WITH_VFP && CFG_WITH_USER_TA*/ 438 439 static enum fault_type get_fault_type(struct abort_info *ai) 440 { 441 if (abort_is_user_exception(ai)) { 442 if (is_vfp_fault(ai)) 443 return FAULT_TYPE_USER_MODE_VFP; 444 #ifndef CFG_WITH_PAGER 445 return FAULT_TYPE_USER_MODE_PANIC; 446 #endif 447 } 448 449 if (thread_is_from_abort_mode()) { 450 abort_print_error(ai); 451 panic("[abort] abort in abort handler (trap CPU)"); 452 } 453 454 if (ai->abort_type == ABORT_TYPE_UNDEF) { 455 if (abort_is_user_exception(ai)) 456 return FAULT_TYPE_USER_MODE_PANIC; 457 abort_print_error(ai); 458 panic("[abort] undefined abort (trap CPU)"); 459 } 460 461 switch (core_mmu_get_fault_type(ai->fault_descr)) { 462 case CORE_MMU_FAULT_ALIGNMENT: 463 if (abort_is_user_exception(ai)) 464 return FAULT_TYPE_USER_MODE_PANIC; 465 abort_print_error(ai); 466 panic("[abort] alignement fault! (trap CPU)"); 467 break; 468 469 case CORE_MMU_FAULT_ACCESS_BIT: 470 if (abort_is_user_exception(ai)) 471 return FAULT_TYPE_USER_MODE_PANIC; 472 abort_print_error(ai); 473 panic("[abort] access bit fault! (trap CPU)"); 474 break; 475 476 case CORE_MMU_FAULT_DEBUG_EVENT: 477 if (!abort_is_user_exception(ai)) 478 abort_print(ai); 479 DMSG("[abort] Ignoring debug event!"); 480 return FAULT_TYPE_IGNORE; 481 482 case CORE_MMU_FAULT_TRANSLATION: 483 case CORE_MMU_FAULT_WRITE_PERMISSION: 484 case CORE_MMU_FAULT_READ_PERMISSION: 485 return FAULT_TYPE_PAGEABLE; 486 487 case CORE_MMU_FAULT_ASYNC_EXTERNAL: 488 if (!abort_is_user_exception(ai)) 489 abort_print(ai); 490 DMSG("[abort] Ignoring async external abort!"); 491 return FAULT_TYPE_IGNORE; 492 493 case CORE_MMU_FAULT_OTHER: 494 default: 495 if (!abort_is_user_exception(ai)) 496 abort_print(ai); 497 DMSG("[abort] Unhandled fault!"); 498 return FAULT_TYPE_IGNORE; 499 } 500 } 501 502 void abort_handler(uint32_t abort_type, struct thread_abort_regs *regs) 503 { 504 struct abort_info ai; 505 bool handled; 506 507 set_abort_info(abort_type, regs, &ai); 508 509 switch (get_fault_type(&ai)) { 510 case FAULT_TYPE_IGNORE: 511 break; 512 case FAULT_TYPE_USER_MODE_PANIC: 513 DMSG("[abort] abort in User mode (TA will panic)"); 514 save_abort_info_in_tsd(&ai); 515 vfp_disable(); 516 handle_user_mode_panic(&ai); 517 break; 518 #ifdef CFG_WITH_VFP 519 case FAULT_TYPE_USER_MODE_VFP: 520 handle_user_mode_vfp(); 521 break; 522 #endif 523 case FAULT_TYPE_PAGEABLE: 524 default: 525 if (thread_get_id_may_fail() < 0) { 526 abort_print_error(&ai); 527 panic("abort outside thread context"); 528 } 529 thread_kernel_save_vfp(); 530 handled = tee_pager_handle_fault(&ai); 531 thread_kernel_restore_vfp(); 532 if (!handled) { 533 if (!abort_is_user_exception(&ai)) { 534 abort_print_error(&ai); 535 panic("unhandled pageable abort"); 536 } 537 DMSG("[abort] abort in User mode (TA will panic)"); 538 save_abort_info_in_tsd(&ai); 539 vfp_disable(); 540 handle_user_mode_panic(&ai); 541 } 542 break; 543 } 544 } 545