1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2015-2021, Linaro Limited 4 */ 5 6 #include <arm.h> 7 #include <kernel/abort.h> 8 #include <kernel/linker.h> 9 #include <kernel/misc.h> 10 #include <kernel/panic.h> 11 #include <kernel/tee_ta_manager.h> 12 #include <kernel/thread_private.h> 13 #include <kernel/user_mode_ctx.h> 14 #include <mm/core_mmu.h> 15 #include <mm/mobj.h> 16 #include <mm/tee_pager.h> 17 #include <tee/tee_svc.h> 18 #include <trace.h> 19 #include <unw/unwind.h> 20 21 enum fault_type { 22 FAULT_TYPE_USER_MODE_PANIC, 23 FAULT_TYPE_USER_MODE_VFP, 24 FAULT_TYPE_PAGEABLE, 25 FAULT_TYPE_IGNORE, 26 }; 27 28 #ifdef CFG_UNWIND 29 30 #ifdef ARM32 31 /* 32 * Kernel or user mode unwind (32-bit execution state). 33 */ 34 static void __print_stack_unwind(struct abort_info *ai) 35 { 36 struct unwind_state_arm32 state = { }; 37 uint32_t mode = ai->regs->spsr & CPSR_MODE_MASK; 38 uint32_t sp = 0; 39 uint32_t lr = 0; 40 41 assert(!abort_is_user_exception(ai)); 42 43 if (mode == CPSR_MODE_SYS) { 44 sp = ai->regs->usr_sp; 45 lr = ai->regs->usr_lr; 46 } else { 47 sp = read_mode_sp(mode); 48 lr = read_mode_lr(mode); 49 } 50 51 memset(&state, 0, sizeof(state)); 52 state.registers[0] = ai->regs->r0; 53 state.registers[1] = ai->regs->r1; 54 state.registers[2] = ai->regs->r2; 55 state.registers[3] = ai->regs->r3; 56 state.registers[4] = ai->regs->r4; 57 state.registers[5] = ai->regs->r5; 58 state.registers[6] = ai->regs->r6; 59 state.registers[7] = ai->regs->r7; 60 state.registers[8] = ai->regs->r8; 61 state.registers[9] = ai->regs->r9; 62 state.registers[10] = ai->regs->r10; 63 state.registers[11] = ai->regs->r11; 64 state.registers[13] = sp; 65 state.registers[14] = lr; 66 state.registers[15] = ai->pc; 67 68 print_stack_arm32(&state, thread_stack_start(), thread_stack_size()); 69 } 70 #endif /* ARM32 */ 71 72 #ifdef ARM64 73 /* Kernel mode unwind (64-bit execution state) */ 74 static void __print_stack_unwind(struct abort_info *ai) 75 { 76 struct unwind_state_arm64 state = { 77 .pc = ai->regs->elr, 78 .fp = ai->regs->x29, 79 }; 80 81 print_stack_arm64(&state, thread_stack_start(), thread_stack_size()); 82 } 83 #endif /*ARM64*/ 84 85 #else /* CFG_UNWIND */ 86 static void __print_stack_unwind(struct abort_info *ai __unused) 87 { 88 } 89 #endif /* CFG_UNWIND */ 90 91 static __maybe_unused const char *abort_type_to_str(uint32_t abort_type) 92 { 93 if (abort_type == ABORT_TYPE_DATA) 94 return "data"; 95 if (abort_type == ABORT_TYPE_PREFETCH) 96 return "prefetch"; 97 return "undef"; 98 } 99 100 static __maybe_unused const char *fault_to_str(uint32_t abort_type, 101 uint32_t fault_descr) 102 { 103 /* fault_descr is only valid for data or prefetch abort */ 104 if (abort_type != ABORT_TYPE_DATA && abort_type != ABORT_TYPE_PREFETCH) 105 return ""; 106 107 switch (core_mmu_get_fault_type(fault_descr)) { 108 case CORE_MMU_FAULT_ALIGNMENT: 109 return " (alignment fault)"; 110 case CORE_MMU_FAULT_TRANSLATION: 111 return " (translation fault)"; 112 case CORE_MMU_FAULT_READ_PERMISSION: 113 return " (read permission fault)"; 114 case CORE_MMU_FAULT_WRITE_PERMISSION: 115 return " (write permission fault)"; 116 case CORE_MMU_FAULT_TAG_CHECK: 117 return " (tag check fault)"; 118 default: 119 return ""; 120 } 121 } 122 123 static __maybe_unused void 124 __print_abort_info(struct abort_info *ai __maybe_unused, 125 const char *ctx __maybe_unused) 126 { 127 __maybe_unused size_t core_pos = 0; 128 #ifdef ARM32 129 uint32_t mode = ai->regs->spsr & CPSR_MODE_MASK; 130 __maybe_unused uint32_t sp = 0; 131 __maybe_unused uint32_t lr = 0; 132 133 if (mode == CPSR_MODE_USR || mode == CPSR_MODE_SYS) { 134 sp = ai->regs->usr_sp; 135 lr = ai->regs->usr_lr; 136 core_pos = thread_get_tsd()->abort_core; 137 } else { 138 sp = read_mode_sp(mode); 139 lr = read_mode_lr(mode); 140 core_pos = get_core_pos(); 141 } 142 #endif /*ARM32*/ 143 #ifdef ARM64 144 if (abort_is_user_exception(ai)) 145 core_pos = thread_get_tsd()->abort_core; 146 else 147 core_pos = get_core_pos(); 148 #endif /*ARM64*/ 149 150 EMSG_RAW(""); 151 EMSG_RAW("%s %s-abort at address 0x%" PRIxVA "%s", 152 ctx, abort_type_to_str(ai->abort_type), ai->va, 153 fault_to_str(ai->abort_type, ai->fault_descr)); 154 #ifdef ARM32 155 EMSG_RAW(" fsr 0x%08x ttbr0 0x%08x ttbr1 0x%08x cidr 0x%X", 156 ai->fault_descr, read_ttbr0(), read_ttbr1(), 157 read_contextidr()); 158 EMSG_RAW(" cpu #%zu cpsr 0x%08x", 159 core_pos, ai->regs->spsr); 160 EMSG_RAW(" r0 0x%08x r4 0x%08x r8 0x%08x r12 0x%08x", 161 ai->regs->r0, ai->regs->r4, ai->regs->r8, ai->regs->ip); 162 EMSG_RAW(" r1 0x%08x r5 0x%08x r9 0x%08x sp 0x%08x", 163 ai->regs->r1, ai->regs->r5, ai->regs->r9, sp); 164 EMSG_RAW(" r2 0x%08x r6 0x%08x r10 0x%08x lr 0x%08x", 165 ai->regs->r2, ai->regs->r6, ai->regs->r10, lr); 166 EMSG_RAW(" r3 0x%08x r7 0x%08x r11 0x%08x pc 0x%08x", 167 ai->regs->r3, ai->regs->r7, ai->regs->r11, ai->pc); 168 #endif /*ARM32*/ 169 #ifdef ARM64 170 EMSG_RAW(" esr 0x%08x ttbr0 0x%08" PRIx64 " ttbr1 0x%08" PRIx64 171 " cidr 0x%X", ai->fault_descr, read_ttbr0_el1(), 172 read_ttbr1_el1(), read_contextidr_el1()); 173 EMSG_RAW(" cpu #%zu cpsr 0x%08x", 174 core_pos, (uint32_t)ai->regs->spsr); 175 EMSG_RAW(" x0 %016" PRIx64 " x1 %016" PRIx64, 176 ai->regs->x0, ai->regs->x1); 177 EMSG_RAW(" x2 %016" PRIx64 " x3 %016" PRIx64, 178 ai->regs->x2, ai->regs->x3); 179 EMSG_RAW(" x4 %016" PRIx64 " x5 %016" PRIx64, 180 ai->regs->x4, ai->regs->x5); 181 EMSG_RAW(" x6 %016" PRIx64 " x7 %016" PRIx64, 182 ai->regs->x6, ai->regs->x7); 183 EMSG_RAW(" x8 %016" PRIx64 " x9 %016" PRIx64, 184 ai->regs->x8, ai->regs->x9); 185 EMSG_RAW(" x10 %016" PRIx64 " x11 %016" PRIx64, 186 ai->regs->x10, ai->regs->x11); 187 EMSG_RAW(" x12 %016" PRIx64 " x13 %016" PRIx64, 188 ai->regs->x12, ai->regs->x13); 189 EMSG_RAW(" x14 %016" PRIx64 " x15 %016" PRIx64, 190 ai->regs->x14, ai->regs->x15); 191 EMSG_RAW(" x16 %016" PRIx64 " x17 %016" PRIx64, 192 ai->regs->x16, ai->regs->x17); 193 EMSG_RAW(" x18 %016" PRIx64 " x19 %016" PRIx64, 194 ai->regs->x18, ai->regs->x19); 195 EMSG_RAW(" x20 %016" PRIx64 " x21 %016" PRIx64, 196 ai->regs->x20, ai->regs->x21); 197 EMSG_RAW(" x22 %016" PRIx64 " x23 %016" PRIx64, 198 ai->regs->x22, ai->regs->x23); 199 EMSG_RAW(" x24 %016" PRIx64 " x25 %016" PRIx64, 200 ai->regs->x24, ai->regs->x25); 201 EMSG_RAW(" x26 %016" PRIx64 " x27 %016" PRIx64, 202 ai->regs->x26, ai->regs->x27); 203 EMSG_RAW(" x28 %016" PRIx64 " x29 %016" PRIx64, 204 ai->regs->x28, ai->regs->x29); 205 EMSG_RAW(" x30 %016" PRIx64 " elr %016" PRIx64, 206 ai->regs->x30, ai->regs->elr); 207 EMSG_RAW(" sp_el0 %016" PRIx64, ai->regs->sp_el0); 208 #endif /*ARM64*/ 209 } 210 211 /* 212 * Print abort info and (optionally) stack dump to the console 213 * @ai kernel-mode abort info. 214 * @stack_dump true to show a stack trace 215 */ 216 static void __abort_print(struct abort_info *ai, bool stack_dump) 217 { 218 assert(!abort_is_user_exception(ai)); 219 220 __print_abort_info(ai, "Core"); 221 222 if (stack_dump) { 223 trace_printf_helper_raw(TRACE_ERROR, true, 224 "TEE load address @ %#"PRIxVA, 225 VCORE_START_VA); 226 __print_stack_unwind(ai); 227 } 228 } 229 230 void abort_print(struct abort_info *ai) 231 { 232 __abort_print(ai, false); 233 } 234 235 void abort_print_error(struct abort_info *ai) 236 { 237 __abort_print(ai, true); 238 } 239 240 /* This function must be called from a normal thread */ 241 void abort_print_current_ts(void) 242 { 243 struct thread_specific_data *tsd = thread_get_tsd(); 244 struct abort_info ai = { }; 245 struct ts_session *s = ts_get_current_session(); 246 247 ai.abort_type = tsd->abort_type; 248 ai.fault_descr = tsd->abort_descr; 249 ai.va = tsd->abort_va; 250 ai.pc = tsd->abort_regs.elr; 251 ai.regs = &tsd->abort_regs; 252 253 if (ai.abort_type != ABORT_TYPE_USER_MODE_PANIC) 254 __print_abort_info(&ai, "User mode"); 255 256 s->ctx->ops->dump_state(s->ctx); 257 258 #if defined(CFG_FTRACE_SUPPORT) 259 if (s->ctx->ops->dump_ftrace) { 260 s->fbuf = NULL; 261 s->ctx->ops->dump_ftrace(s->ctx); 262 } 263 #endif 264 } 265 266 static void save_abort_info_in_tsd(struct abort_info *ai) 267 { 268 struct thread_specific_data *tsd = thread_get_tsd(); 269 270 tsd->abort_type = ai->abort_type; 271 tsd->abort_descr = ai->fault_descr; 272 tsd->abort_va = ai->va; 273 tsd->abort_regs = *ai->regs; 274 tsd->abort_core = get_core_pos(); 275 } 276 277 #ifdef ARM32 278 static void set_abort_info(uint32_t abort_type, struct thread_abort_regs *regs, 279 struct abort_info *ai) 280 { 281 switch (abort_type) { 282 case ABORT_TYPE_DATA: 283 ai->fault_descr = read_dfsr(); 284 ai->va = read_dfar(); 285 break; 286 case ABORT_TYPE_PREFETCH: 287 ai->fault_descr = read_ifsr(); 288 ai->va = read_ifar(); 289 break; 290 default: 291 ai->fault_descr = 0; 292 ai->va = regs->elr; 293 break; 294 } 295 ai->abort_type = abort_type; 296 ai->pc = regs->elr; 297 ai->regs = regs; 298 } 299 #endif /*ARM32*/ 300 301 #ifdef ARM64 302 static void set_abort_info(uint32_t abort_type __unused, 303 struct thread_abort_regs *regs, struct abort_info *ai) 304 { 305 ai->fault_descr = read_esr_el1(); 306 switch ((ai->fault_descr >> ESR_EC_SHIFT) & ESR_EC_MASK) { 307 case ESR_EC_IABT_EL0: 308 case ESR_EC_IABT_EL1: 309 ai->abort_type = ABORT_TYPE_PREFETCH; 310 ai->va = read_far_el1(); 311 break; 312 case ESR_EC_DABT_EL0: 313 case ESR_EC_DABT_EL1: 314 case ESR_EC_SP_ALIGN: 315 ai->abort_type = ABORT_TYPE_DATA; 316 ai->va = read_far_el1(); 317 break; 318 default: 319 ai->abort_type = ABORT_TYPE_UNDEF; 320 ai->va = regs->elr; 321 } 322 ai->pc = regs->elr; 323 ai->regs = regs; 324 } 325 #endif /*ARM64*/ 326 327 #ifdef ARM32 328 static void handle_user_mode_panic(struct abort_info *ai) 329 { 330 /* 331 * It was a user exception, stop user execution and return 332 * to TEE Core. 333 */ 334 ai->regs->r0 = TEE_ERROR_TARGET_DEAD; 335 ai->regs->r1 = true; 336 ai->regs->r2 = 0xdeadbeef; 337 ai->regs->elr = (uint32_t)thread_unwind_user_mode; 338 ai->regs->spsr &= CPSR_FIA; 339 ai->regs->spsr &= ~CPSR_MODE_MASK; 340 ai->regs->spsr |= CPSR_MODE_SVC; 341 /* Select Thumb or ARM mode */ 342 if (ai->regs->elr & 1) 343 ai->regs->spsr |= CPSR_T; 344 else 345 ai->regs->spsr &= ~CPSR_T; 346 } 347 #endif /*ARM32*/ 348 349 #ifdef ARM64 350 static void handle_user_mode_panic(struct abort_info *ai) 351 { 352 uint32_t daif; 353 354 /* 355 * It was a user exception, stop user execution and return 356 * to TEE Core. 357 */ 358 ai->regs->x0 = TEE_ERROR_TARGET_DEAD; 359 ai->regs->x1 = true; 360 ai->regs->x2 = 0xdeadbeef; 361 ai->regs->elr = (vaddr_t)thread_unwind_user_mode; 362 ai->regs->sp_el0 = thread_get_saved_thread_sp(); 363 364 daif = (ai->regs->spsr >> SPSR_32_AIF_SHIFT) & SPSR_32_AIF_MASK; 365 /* XXX what about DAIF_D? */ 366 ai->regs->spsr = SPSR_64(SPSR_64_MODE_EL1, SPSR_64_MODE_SP_EL0, daif); 367 } 368 #endif /*ARM64*/ 369 370 #ifdef CFG_WITH_VFP 371 static void handle_user_mode_vfp(void) 372 { 373 struct ts_session *s = ts_get_current_session(); 374 375 thread_user_enable_vfp(&to_user_mode_ctx(s->ctx)->vfp); 376 } 377 #endif /*CFG_WITH_VFP*/ 378 379 #ifdef CFG_WITH_USER_TA 380 #ifdef ARM32 381 /* Returns true if the exception originated from user mode */ 382 bool abort_is_user_exception(struct abort_info *ai) 383 { 384 return (ai->regs->spsr & ARM32_CPSR_MODE_MASK) == ARM32_CPSR_MODE_USR; 385 } 386 #endif /*ARM32*/ 387 388 #ifdef ARM64 389 /* Returns true if the exception originated from user mode */ 390 bool abort_is_user_exception(struct abort_info *ai) 391 { 392 uint32_t spsr = ai->regs->spsr; 393 394 if (spsr & (SPSR_MODE_RW_32 << SPSR_MODE_RW_SHIFT)) 395 return true; 396 if (((spsr >> SPSR_64_MODE_EL_SHIFT) & SPSR_64_MODE_EL_MASK) == 397 SPSR_64_MODE_EL0) 398 return true; 399 return false; 400 } 401 #endif /*ARM64*/ 402 #else /*CFG_WITH_USER_TA*/ 403 bool abort_is_user_exception(struct abort_info *ai __unused) 404 { 405 return false; 406 } 407 #endif /*CFG_WITH_USER_TA*/ 408 409 #if defined(CFG_WITH_VFP) && defined(CFG_WITH_USER_TA) 410 #ifdef ARM32 411 static bool is_vfp_fault(struct abort_info *ai) 412 { 413 if ((ai->abort_type != ABORT_TYPE_UNDEF) || vfp_is_enabled()) 414 return false; 415 416 /* 417 * Not entirely accurate, but if it's a truly undefined instruction 418 * we'll end up in this function again, except this time 419 * vfp_is_enabled() so we'll return false. 420 */ 421 return true; 422 } 423 #endif /*ARM32*/ 424 425 #ifdef ARM64 426 static bool is_vfp_fault(struct abort_info *ai) 427 { 428 switch ((ai->fault_descr >> ESR_EC_SHIFT) & ESR_EC_MASK) { 429 case ESR_EC_FP_ASIMD: 430 case ESR_EC_AARCH32_FP: 431 case ESR_EC_AARCH64_FP: 432 return true; 433 default: 434 return false; 435 } 436 } 437 #endif /*ARM64*/ 438 #else /*CFG_WITH_VFP && CFG_WITH_USER_TA*/ 439 static bool is_vfp_fault(struct abort_info *ai __unused) 440 { 441 return false; 442 } 443 #endif /*CFG_WITH_VFP && CFG_WITH_USER_TA*/ 444 445 bool abort_is_write_fault(struct abort_info *ai) 446 { 447 #ifdef ARM32 448 unsigned int write_not_read = 11; 449 #endif 450 #ifdef ARM64 451 unsigned int write_not_read = 6; 452 #endif 453 454 return ai->abort_type == ABORT_TYPE_DATA && 455 (ai->fault_descr & BIT(write_not_read)); 456 } 457 458 static enum fault_type get_fault_type(struct abort_info *ai) 459 { 460 if (abort_is_user_exception(ai)) { 461 if (is_vfp_fault(ai)) 462 return FAULT_TYPE_USER_MODE_VFP; 463 #ifndef CFG_WITH_PAGER 464 return FAULT_TYPE_USER_MODE_PANIC; 465 #endif 466 } 467 468 if (thread_is_from_abort_mode()) { 469 abort_print_error(ai); 470 panic("[abort] abort in abort handler (trap CPU)"); 471 } 472 473 if (ai->abort_type == ABORT_TYPE_UNDEF) { 474 if (abort_is_user_exception(ai)) 475 return FAULT_TYPE_USER_MODE_PANIC; 476 abort_print_error(ai); 477 panic("[abort] undefined abort (trap CPU)"); 478 } 479 480 switch (core_mmu_get_fault_type(ai->fault_descr)) { 481 case CORE_MMU_FAULT_ALIGNMENT: 482 if (abort_is_user_exception(ai)) 483 return FAULT_TYPE_USER_MODE_PANIC; 484 abort_print_error(ai); 485 panic("[abort] alignement fault! (trap CPU)"); 486 break; 487 488 case CORE_MMU_FAULT_ACCESS_BIT: 489 if (abort_is_user_exception(ai)) 490 return FAULT_TYPE_USER_MODE_PANIC; 491 abort_print_error(ai); 492 panic("[abort] access bit fault! (trap CPU)"); 493 break; 494 495 case CORE_MMU_FAULT_DEBUG_EVENT: 496 if (!abort_is_user_exception(ai)) 497 abort_print(ai); 498 DMSG("[abort] Ignoring debug event!"); 499 return FAULT_TYPE_IGNORE; 500 501 case CORE_MMU_FAULT_TRANSLATION: 502 case CORE_MMU_FAULT_WRITE_PERMISSION: 503 case CORE_MMU_FAULT_READ_PERMISSION: 504 return FAULT_TYPE_PAGEABLE; 505 506 case CORE_MMU_FAULT_ASYNC_EXTERNAL: 507 if (!abort_is_user_exception(ai)) 508 abort_print(ai); 509 DMSG("[abort] Ignoring async external abort!"); 510 return FAULT_TYPE_IGNORE; 511 512 case CORE_MMU_FAULT_TAG_CHECK: 513 if (abort_is_user_exception(ai)) 514 return FAULT_TYPE_USER_MODE_PANIC; 515 abort_print_error(ai); 516 panic("[abort] Tag check fault! (trap CPU)"); 517 break; 518 519 case CORE_MMU_FAULT_OTHER: 520 default: 521 if (!abort_is_user_exception(ai)) 522 abort_print(ai); 523 DMSG("[abort] Unhandled fault!"); 524 return FAULT_TYPE_IGNORE; 525 } 526 } 527 528 void abort_handler(uint32_t abort_type, struct thread_abort_regs *regs) 529 { 530 struct abort_info ai; 531 bool handled; 532 533 set_abort_info(abort_type, regs, &ai); 534 535 switch (get_fault_type(&ai)) { 536 case FAULT_TYPE_IGNORE: 537 break; 538 case FAULT_TYPE_USER_MODE_PANIC: 539 DMSG("[abort] abort in User mode (TA will panic)"); 540 save_abort_info_in_tsd(&ai); 541 vfp_disable(); 542 handle_user_mode_panic(&ai); 543 break; 544 #ifdef CFG_WITH_VFP 545 case FAULT_TYPE_USER_MODE_VFP: 546 handle_user_mode_vfp(); 547 break; 548 #endif 549 case FAULT_TYPE_PAGEABLE: 550 default: 551 if (thread_get_id_may_fail() < 0) { 552 abort_print_error(&ai); 553 panic("abort outside thread context"); 554 } 555 thread_kernel_save_vfp(); 556 handled = tee_pager_handle_fault(&ai); 557 thread_kernel_restore_vfp(); 558 if (!handled) { 559 if (!abort_is_user_exception(&ai)) { 560 abort_print_error(&ai); 561 panic("unhandled pageable abort"); 562 } 563 DMSG("[abort] abort in User mode (TA will panic)"); 564 save_abort_info_in_tsd(&ai); 565 vfp_disable(); 566 handle_user_mode_panic(&ai); 567 } 568 break; 569 } 570 } 571