1 /* 2 * Copyright (c) 2016, Linaro Limited 3 * Copyright (c) 2014, STMicroelectronics International N.V. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef SM_SM_H 30 #define SM_SM_H 31 32 #include <compiler.h> 33 #include <types_ext.h> 34 35 struct sm_mode_regs { 36 uint32_t usr_sp; 37 uint32_t usr_lr; 38 uint32_t irq_spsr; 39 uint32_t irq_sp; 40 uint32_t irq_lr; 41 uint32_t fiq_spsr; 42 uint32_t fiq_sp; 43 uint32_t fiq_lr; 44 /* 45 * Note that fiq_r{8-12} are not saved here. Instead thread_fiq_handler 46 * preserves r{8-12}. 47 */ 48 uint32_t svc_spsr; 49 uint32_t svc_sp; 50 uint32_t svc_lr; 51 uint32_t abt_spsr; 52 uint32_t abt_sp; 53 uint32_t abt_lr; 54 uint32_t und_spsr; 55 uint32_t und_sp; 56 uint32_t und_lr; 57 }; 58 59 struct sm_nsec_ctx { 60 struct sm_mode_regs mode_regs; 61 62 uint32_t r8; 63 uint32_t r9; 64 uint32_t r10; 65 uint32_t r11; 66 uint32_t r12; 67 68 uint32_t r0; 69 uint32_t r1; 70 uint32_t r2; 71 uint32_t r3; 72 uint32_t r4; 73 uint32_t r5; 74 uint32_t r6; 75 uint32_t r7; 76 77 /* return state */ 78 uint32_t mon_lr; 79 uint32_t mon_spsr; 80 }; 81 82 struct sm_sec_ctx { 83 struct sm_mode_regs mode_regs; 84 85 uint32_t r0; 86 uint32_t r1; 87 uint32_t r2; 88 uint32_t r3; 89 uint32_t r4; 90 uint32_t r5; 91 uint32_t r6; 92 uint32_t r7; 93 94 /* return state */ 95 uint32_t mon_lr; 96 uint32_t mon_spsr; 97 }; 98 99 struct sm_ctx { 100 uint32_t pad; 101 struct sm_sec_ctx sec; 102 struct sm_nsec_ctx nsec; 103 }; 104 105 /* 106 * The secure monitor reserves space at top of stack_tmp to hold struct 107 * sm_ctx. 108 */ 109 #define SM_STACK_TMP_RESERVE_SIZE sizeof(struct sm_ctx) 110 111 112 113 /* Returns storage location of non-secure context for current CPU */ 114 struct sm_nsec_ctx *sm_get_nsec_ctx(void); 115 116 /* Returns stack pointer to use in monitor mode for current CPU */ 117 void *sm_get_sp(void); 118 119 /* 120 * Initializes secure monitor, must be called by each CPU 121 */ 122 void sm_init(vaddr_t stack_pointer); 123 124 #ifndef CFG_SM_PLATFORM_HANDLER 125 /* 126 * Returns false if we handled the monitor service and should now return 127 * back to the non-secure state 128 */ 129 static inline bool sm_platform_handler(__unused struct sm_ctx *ctx) 130 { 131 return true; 132 } 133 #else 134 bool sm_platform_handler(struct sm_ctx *ctx); 135 #endif 136 137 void sm_save_modes_regs(struct sm_mode_regs *regs); 138 void sm_restore_modes_regs(struct sm_mode_regs *regs); 139 #endif /*SM_SM_H*/ 140