1 /* 2 * Copyright (c) 2014, STMicroelectronics International N.V. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #ifndef SM_SM_H 29 #define SM_SM_H 30 31 #include <types_ext.h> 32 33 struct sm_nsec_ctx { 34 uint32_t usr_sp; 35 uint32_t usr_lr; 36 uint32_t irq_spsr; 37 uint32_t irq_sp; 38 uint32_t irq_lr; 39 uint32_t fiq_spsr; 40 uint32_t fiq_sp; 41 uint32_t fiq_lr; 42 uint32_t svc_spsr; 43 uint32_t svc_sp; 44 uint32_t svc_lr; 45 uint32_t abt_spsr; 46 uint32_t abt_sp; 47 uint32_t abt_lr; 48 uint32_t und_spsr; 49 uint32_t und_sp; 50 uint32_t und_lr; 51 uint32_t mon_lr; 52 uint32_t mon_spsr; 53 uint32_t r4; 54 uint32_t r5; 55 uint32_t r6; 56 uint32_t r7; 57 uint32_t r8; 58 uint32_t r9; 59 uint32_t r10; 60 uint32_t r11; 61 uint32_t r12; 62 /* Only stored on FIQ entry */ 63 uint32_t r0; 64 uint32_t r1; 65 uint32_t r2; 66 uint32_t r3; 67 }; 68 69 struct sm_sec_ctx { 70 uint32_t usr_sp; 71 uint32_t usr_lr; 72 uint32_t irq_spsr; 73 uint32_t irq_sp; 74 uint32_t irq_lr; 75 uint32_t fiq_spsr; 76 uint32_t fiq_sp; 77 uint32_t fiq_lr; 78 uint32_t svc_spsr; 79 uint32_t svc_sp; 80 uint32_t svc_lr; 81 uint32_t abt_spsr; 82 uint32_t abt_sp; 83 uint32_t abt_lr; 84 uint32_t und_spsr; 85 uint32_t und_sp; 86 uint32_t und_lr; 87 uint32_t mon_lr; 88 uint32_t mon_spsr; 89 uint32_t entry_reason; 90 }; 91 92 /* Returns storage location of non-secure context for current CPU */ 93 struct sm_nsec_ctx *sm_get_nsec_ctx(void); 94 95 /* Returns storage location of secure context for current CPU */ 96 struct sm_sec_ctx *sm_get_sec_ctx(void); 97 98 /* Returns stack pointer to use in monitor mode for current CPU */ 99 void *sm_get_sp(void); 100 101 102 /* 103 * Initializes secure monitor, must be called by each CPU 104 */ 105 void sm_init(vaddr_t stack_pointer); 106 107 void sm_set_entry_vector(void *entry_vector); 108 109 #endif /*SM_SM_H*/ 110