1 /* 2 * Copyright (c) 2016, Linaro Limited 3 * Copyright (c) 2014, STMicroelectronics International N.V. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef SM_SM_H 30 #define SM_SM_H 31 32 #include <types_ext.h> 33 34 struct sm_mode_regs { 35 uint32_t usr_sp; 36 uint32_t usr_lr; 37 uint32_t irq_spsr; 38 uint32_t irq_sp; 39 uint32_t irq_lr; 40 uint32_t fiq_spsr; 41 uint32_t fiq_sp; 42 uint32_t fiq_lr; 43 /* 44 * Note that fiq_r{8-12} are not saved here. Instead thread_fiq_handler 45 * preserves r{8-12}. 46 */ 47 uint32_t svc_spsr; 48 uint32_t svc_sp; 49 uint32_t svc_lr; 50 uint32_t abt_spsr; 51 uint32_t abt_sp; 52 uint32_t abt_lr; 53 uint32_t und_spsr; 54 uint32_t und_sp; 55 uint32_t und_lr; 56 }; 57 58 struct sm_nsec_ctx { 59 struct sm_mode_regs mode_regs; 60 61 uint32_t r8; 62 uint32_t r9; 63 uint32_t r10; 64 uint32_t r11; 65 uint32_t r12; 66 67 uint32_t r0; 68 uint32_t r1; 69 uint32_t r2; 70 uint32_t r3; 71 uint32_t r4; 72 uint32_t r5; 73 uint32_t r6; 74 uint32_t r7; 75 76 /* return state */ 77 uint32_t mon_lr; 78 uint32_t mon_spsr; 79 }; 80 81 struct sm_sec_ctx { 82 struct sm_mode_regs mode_regs; 83 84 uint32_t r0; 85 uint32_t r1; 86 uint32_t r2; 87 uint32_t r3; 88 uint32_t r4; 89 uint32_t r5; 90 uint32_t r6; 91 uint32_t r7; 92 93 /* return state */ 94 uint32_t mon_lr; 95 uint32_t mon_spsr; 96 }; 97 98 struct sm_ctx { 99 uint32_t pad; 100 struct sm_sec_ctx sec; 101 struct sm_nsec_ctx nsec; 102 }; 103 104 /* 105 * The secure monitor reserves space at top of stack_tmp to hold struct 106 * sm_ctx. 107 */ 108 #define SM_STACK_TMP_RESERVE_SIZE sizeof(struct sm_ctx) 109 110 111 112 /* Returns storage location of non-secure context for current CPU */ 113 struct sm_nsec_ctx *sm_get_nsec_ctx(void); 114 115 /* Returns stack pointer to use in monitor mode for current CPU */ 116 void *sm_get_sp(void); 117 118 /* 119 * Initializes secure monitor, must be called by each CPU 120 */ 121 void sm_init(vaddr_t stack_pointer); 122 123 #endif /*SM_SM_H*/ 124