1 /* 2 * Copyright (c) 2015, Linaro Limited 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #ifndef ARM64_H 28 #define ARM64_H 29 30 #include <sys/cdefs.h> 31 #include <stdint.h> 32 #include <util.h> 33 34 #define SCTLR_M BIT32(0) 35 #define SCTLR_A BIT32(1) 36 #define SCTLR_C BIT32(2) 37 #define SCTLR_SA BIT32(3) 38 #define SCTLR_I BIT32(12) 39 #define SCTLR_WXN BIT32(19) 40 41 #define TTBR_ASID_MASK 0xff 42 #define TTBR_ASID_SHIFT 48 43 44 #define CLIDR_LOUIS_SHIFT 21 45 #define CLIDR_LOC_SHIFT 24 46 #define CLIDR_FIELD_WIDTH 3 47 48 #define CSSELR_LEVEL_SHIFT 1 49 50 #define DAIFBIT_FIQ BIT32(0) 51 #define DAIFBIT_IRQ BIT32(1) 52 #define DAIFBIT_ABT BIT32(2) 53 #define DAIFBIT_DBG BIT32(3) 54 #define DAIFBIT_ALL (DAIFBIT_FIQ | DAIFBIT_IRQ | \ 55 DAIFBIT_ABT | DAIFBIT_DBG) 56 57 #define DAIF_F_SHIFT 6 58 #define DAIF_F BIT32(6) 59 #define DAIF_I BIT32(7) 60 #define DAIF_A BIT32(8) 61 #define DAIF_D BIT32(9) 62 #define DAIF_AIF (DAIF_A | DAIF_I | DAIF_F) 63 64 #define SPSR_MODE_RW_SHIFT 4 65 #define SPSR_MODE_RW_MASK 0x1 66 #define SPSR_MODE_RW_64 0x0 67 #define SPSR_MODE_RW_32 0x1 68 69 #define SPSR_64_MODE_SP_SHIFT 0 70 #define SPSR_64_MODE_SP_MASK 0x1 71 #define SPSR_64_MODE_SP_EL0 0x0 72 #define SPSR_64_MODE_SP_ELX 0x1 73 74 #define SPSR_64_MODE_EL_SHIFT 2 75 #define SPSR_64_MODE_EL_MASK 0x3 76 #define SPSR_64_MODE_EL1 0x1 77 #define SPSR_64_MODE_EL0 0x0 78 79 #define SPSR_64_DAIF_SHIFT 6 80 #define SPSR_64_DAIF_MASK 0xf 81 82 #define SPSR_32_AIF_SHIFT 6 83 #define SPSR_32_AIF_MASK 0x7 84 85 #define SPSR_32_E_SHIFT 9 86 #define SPSR_32_E_MASK 0x1 87 #define SPSR_32_E_LITTLE 0x0 88 #define SPSR_32_E_BIG 0x1 89 90 #define SPSR_32_T_SHIFT 5 91 #define SPSR_32_T_MASK 0x1 92 #define SPSR_32_T_ARM 0x0 93 #define SPSR_32_T_THUMB 0x1 94 95 #define SPSR_32_MODE_SHIFT 0 96 #define SPSR_32_MODE_MASK 0xf 97 #define SPSR_32_MODE_USR 0x0 98 99 100 #define SPSR_64(el, sp, daif) \ 101 (SPSR_MODE_RW_64 << SPSR_MODE_RW_SHIFT | \ 102 ((el) & SPSR_64_MODE_EL_MASK) << SPSR_64_MODE_EL_SHIFT | \ 103 ((sp) & SPSR_64_MODE_SP_MASK) << SPSR_64_MODE_SP_SHIFT | \ 104 ((daif) & SPSR_64_DAIF_MASK) << SPSR_64_DAIF_SHIFT) 105 106 #define SPSR_32(mode, isa, aif) \ 107 (SPSR_MODE_RW_32 << SPSR_MODE_RW_SHIFT | \ 108 SPSR_32_E_LITTLE << SPSR_32_E_SHIFT | \ 109 ((mode) & SPSR_32_MODE_MASK) << SPSR_32_MODE_SHIFT | \ 110 ((isa) & SPSR_32_T_MASK) << SPSR_32_T_SHIFT | \ 111 ((aif) & SPSR_32_AIF_MASK) << SPSR_32_AIF_SHIFT) 112 113 114 #define TCR_T0SZ_SHIFT 0 115 #define TCR_EPD0 BIT32(7) 116 #define TCR_IRGN0_SHIFT 8 117 #define TCR_ORGN0_SHIFT 10 118 #define TCR_SH0_SHIFT 12 119 #define TCR_T1SZ_SHIFT 16 120 #define TCR_A1 BIT32(22) 121 #define TCR_EPD1 BIT32(23) 122 #define TCR_IRGN1_SHIFT 24 123 #define TCR_ORGN1_SHIFT 26 124 #define TCR_SH1_SHIFT 28 125 #define TCR_EL1_IPS_SHIFT 32 126 #define TCR_TG1_4KB SHIFT_U32(2, 30) 127 #define TCR_RES1 BIT32(31) 128 129 130 /* Normal memory, Inner/Outer Non-cacheable */ 131 #define TCR_XRGNX_NC 0x0 132 /* Normal memory, Inner/Outer Write-Back Write-Allocate Cacheable */ 133 #define TCR_XRGNX_WB 0x1 134 /* Normal memory, Inner/Outer Write-Through Cacheable */ 135 #define TCR_XRGNX_WT 0x2 136 /* Normal memory, Inner/Outer Write-Back no Write-Allocate Cacheable */ 137 #define TCR_XRGNX_WBWA 0x3 138 139 /* Non-shareable */ 140 #define TCR_SHX_NSH 0x0 141 /* Outer Shareable */ 142 #define TCR_SHX_OSH 0x2 143 /* Inner Shareable */ 144 #define TCR_SHX_ISH 0x3 145 146 #define ESR_EC_SHIFT 26 147 #define ESR_EC_MASK 0x3f 148 149 #define ESR_EC_UNKNOWN 0x00 150 #define ESR_EC_WFI 0x01 151 #define ESR_EC_AARCH32_CP15_32 0x03 152 #define ESR_EC_AARCH32_CP15_64 0x04 153 #define ESR_EC_AARCH32_CP14_MR 0x05 154 #define ESR_EC_AARCH32_CP14_LS 0x06 155 #define ESR_EC_FP_ASIMD 0x07 156 #define ESR_EC_AARCH32_CP10_ID 0x08 157 #define ESR_EC_AARCH32_CP14_64 0x0c 158 #define ESR_EC_ILLEGAL 0x0e 159 #define ESR_EC_AARCH32_SVC 0x11 160 #define ESR_EC_AARCH64_SVC 0x15 161 #define ESR_EC_AARCH64_SYS 0x18 162 #define ESR_EC_IABT_EL0 0x20 163 #define ESR_EC_IABT_EL1 0x21 164 #define ESR_EC_PC_ALIGN 0x22 165 #define ESR_EC_DABT_EL0 0x24 166 #define ESR_EC_DABT_EL1 0x25 167 #define ESR_EC_SP_ALIGN 0x26 168 #define ESR_EC_AARCH32_FP 0x28 169 #define ESR_EC_AARCH64_FP 0x2c 170 #define ESR_EC_SERROR 0x2f 171 #define ESR_EC_BREAKPT_EL0 0x30 172 #define ESR_EC_BREAKPT_EL1 0x31 173 #define ESR_EC_SOFTSTP_EL0 0x32 174 #define ESR_EC_SOFTSTP_EL1 0x33 175 #define ESR_EC_WATCHPT_EL0 0x34 176 #define ESR_EC_WATCHPT_EL1 0x35 177 #define ESR_EC_AARCH32_BKPT 0x38 178 #define ESR_EC_AARCH64_BRK 0x3c 179 180 /* Combined defines for DFSC and IFSC */ 181 #define ESR_FSC_MASK 0x3f 182 #define ESR_FSC_SIZE_L0 0x00 183 #define ESR_FSC_SIZE_L1 0x01 184 #define ESR_FSC_SIZE_L2 0x02 185 #define ESR_FSC_SIZE_L3 0x03 186 #define ESR_FSC_TRANS_L0 0x04 187 #define ESR_FSC_TRANS_L1 0x05 188 #define ESR_FSC_TRANS_L2 0x06 189 #define ESR_FSC_TRANS_L3 0x07 190 #define ESR_FSC_ACCF_L1 0x09 191 #define ESR_FSC_ACCF_L2 0x0a 192 #define ESR_FSC_ACCF_L3 0x0b 193 #define ESR_FSC_PERMF_L1 0x0d 194 #define ESR_FSC_PERMF_L2 0x0e 195 #define ESR_FSC_PERMF_L3 0x0f 196 #define ESR_FSC_ALIGN 0x21 197 198 /* WnR for DABT and RES0 for IABT */ 199 #define ESR_ABT_WNR BIT32(6) 200 201 #define CPACR_EL1_FPEN_SHIFT 20 202 #define CPACR_EL1_FPEN_MASK 0x3 203 #define CPACR_EL1_FPEN_NONE 0x0 204 #define CPACR_EL1_FPEN_EL1 0x1 205 #define CPACR_EL1_FPEN_EL0EL1 0x3 206 #define CPACR_EL1_FPEN(x) ((x) >> CPACR_EL1_FPEN_SHIFT \ 207 & CPACR_EL1_FPEN_MASK) 208 209 210 #define PAR_F BIT32(0) 211 #define PAR_PA_SHIFT 12 212 #define PAR_PA_MASK (BIT64(36) - 1) 213 214 #define TLBI_MVA_SHIFT 12 215 #define TLBI_ASID_SHIFT 48 216 #define TLBI_ASID_MASK 0xff 217 218 #ifndef ASM 219 static inline void isb(void) 220 { 221 asm volatile ("isb"); 222 } 223 224 static inline void dsb(void) 225 { 226 asm volatile ("dsb sy"); 227 } 228 229 static inline void dsb_ish(void) 230 { 231 asm volatile ("dsb ish"); 232 } 233 234 static inline void dsb_ishst(void) 235 { 236 asm volatile ("dsb ishst"); 237 } 238 239 static inline void write_at_s1e1r(uint64_t va) 240 { 241 asm volatile ("at S1E1R, %0" : : "r" (va)); 242 } 243 244 static __always_inline uint64_t read_pc(void) 245 { 246 uint64_t val; 247 248 asm volatile ("adr %0, ." : "=r" (val)); 249 return val; 250 } 251 252 static __always_inline uint64_t read_fp(void) 253 { 254 uint64_t val; 255 256 asm volatile ("mov %0, x29" : "=r" (val)); 257 return val; 258 } 259 260 static inline uint64_t read_pmu_ccnt(void) 261 { 262 uint64_t val; 263 264 asm volatile("mrs %0, PMCCNTR_EL0" : "=r"(val)); 265 return val; 266 } 267 268 static inline void tlbi_vaae1is(uint64_t mva) 269 { 270 asm volatile ("tlbi vaae1is, %0" : : "r" (mva)); 271 } 272 273 /* 274 * Templates for register read/write functions based on mrs/msr 275 */ 276 277 #define DEFINE_REG_READ_FUNC_(reg, type, asmreg) \ 278 static inline type read_##reg(void) \ 279 { \ 280 type val; \ 281 \ 282 asm volatile("mrs %0, " #asmreg : "=r" (val)); \ 283 return val; \ 284 } 285 286 #define DEFINE_REG_WRITE_FUNC_(reg, type, asmreg) \ 287 static inline void write_##reg(type val) \ 288 { \ 289 asm volatile("msr " #asmreg ", %0" : : "r" (val)); \ 290 } 291 292 #define DEFINE_U32_REG_READ_FUNC(reg) \ 293 DEFINE_REG_READ_FUNC_(reg, uint32_t, reg) 294 295 #define DEFINE_U32_REG_WRITE_FUNC(reg) \ 296 DEFINE_REG_WRITE_FUNC_(reg, uint32_t, reg) 297 298 #define DEFINE_U32_REG_READWRITE_FUNCS(reg) \ 299 DEFINE_U32_REG_READ_FUNC(reg) \ 300 DEFINE_U32_REG_WRITE_FUNC(reg) 301 302 #define DEFINE_U64_REG_READ_FUNC(reg) \ 303 DEFINE_REG_READ_FUNC_(reg, uint64_t, reg) 304 305 #define DEFINE_U64_REG_WRITE_FUNC(reg) \ 306 DEFINE_REG_WRITE_FUNC_(reg, uint64_t, reg) 307 308 #define DEFINE_U64_REG_READWRITE_FUNCS(reg) \ 309 DEFINE_U64_REG_READ_FUNC(reg) \ 310 DEFINE_U64_REG_WRITE_FUNC(reg) 311 312 /* 313 * Define register access functions 314 */ 315 316 DEFINE_U32_REG_READWRITE_FUNCS(cpacr_el1) 317 DEFINE_U32_REG_READWRITE_FUNCS(daif) 318 DEFINE_U32_REG_READWRITE_FUNCS(fpcr) 319 DEFINE_U32_REG_READWRITE_FUNCS(fpsr) 320 321 DEFINE_U32_REG_READ_FUNC(contextidr_el1) 322 DEFINE_U32_REG_READ_FUNC(sctlr_el1) 323 324 /* ARM Generic timer functions */ 325 DEFINE_REG_READ_FUNC_(cntfrq, uint32_t, cntfrq_el0) 326 DEFINE_REG_READ_FUNC_(cntpct, uint64_t, cntpct_el0) 327 DEFINE_REG_READ_FUNC_(cntkctl, uint32_t, cntkctl_el1) 328 DEFINE_REG_WRITE_FUNC_(cntkctl, uint32_t, cntkctl_el1) 329 330 DEFINE_U64_REG_READWRITE_FUNCS(ttbr0_el1) 331 DEFINE_U64_REG_READWRITE_FUNCS(ttbr1_el1) 332 DEFINE_U64_REG_READWRITE_FUNCS(tcr_el1) 333 334 DEFINE_U64_REG_READ_FUNC(esr_el1) 335 DEFINE_U64_REG_READ_FUNC(far_el1) 336 DEFINE_U64_REG_READ_FUNC(mpidr_el1) 337 DEFINE_U64_REG_READ_FUNC(par_el1) 338 339 DEFINE_U64_REG_WRITE_FUNC(mair_el1) 340 341 /* Register read/write functions for GICC registers by using system interface */ 342 DEFINE_REG_READ_FUNC_(icc_ctlr, uint32_t, S3_0_C12_C12_4) 343 DEFINE_REG_WRITE_FUNC_(icc_ctlr, uint32_t, S3_0_C12_C12_4) 344 DEFINE_REG_WRITE_FUNC_(icc_pmr, uint32_t, S3_0_C4_C6_0) 345 DEFINE_REG_READ_FUNC_(icc_iar0, uint32_t, S3_0_c12_c8_0) 346 DEFINE_REG_WRITE_FUNC_(icc_eoir0, uint32_t, S3_0_c12_c8_1) 347 #endif /*ASM*/ 348 349 #endif /*ARM64_H*/ 350 351