1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 * Copyright (c) 2023, Arm Limited 5 */ 6 #ifndef ARM64_H 7 #define ARM64_H 8 9 #include <compiler.h> 10 #include <sys/cdefs.h> 11 #include <stdint.h> 12 #include <util.h> 13 14 #define SCTLR_M BIT64(0) 15 #define SCTLR_A BIT64(1) 16 #define SCTLR_C BIT64(2) 17 #define SCTLR_SA BIT64(3) 18 #define SCTLR_I BIT64(12) 19 #define SCTLR_ENDB BIT64(13) 20 #define SCTLR_WXN BIT64(19) 21 #define SCTLR_SPAN BIT64(23) 22 #define SCTLR_ENDA BIT64(27) 23 #define SCTLR_ENIB BIT64(30) 24 #define SCTLR_ENIA BIT64(31) 25 #define SCTLR_BT0 BIT64(35) 26 #define SCTLR_BT1 BIT64(36) 27 #define SCTLR_ITFSB BIT64(37) 28 29 #define SCTLR_TCF_MASK SHIFT_U64(0x3, 40) 30 #define SCTLR_TCF_NONE SHIFT_U64(0x0, 40) 31 #define SCTLR_TCF_SYNC SHIFT_U64(0x1, 40) 32 #define SCTLR_TCF_ASYNC SHIFT_U64(0x2, 40) 33 #define SCTLR_TCF_ASYMM SHIFT_U64(0x3, 40) 34 35 #define SCTLR_TCF0_MASK SHIFT_U64(0x3, 38) 36 #define SCTLR_TCF0_NONE SHIFT_U64(0x0, 38) 37 #define SCTLR_TCF0_SYNC SHIFT_U64(0x1, 38) 38 #define SCTLR_TCF0_ASYNC SHIFT_U64(0x2, 38) 39 #define SCTLR_TCF0_ASYMM SHIFT_U64(0x3, 38) 40 41 #define SCTLR_ATA0 BIT64(42) 42 #define SCTLR_ATA BIT64(43) 43 44 #define TTBR_ASID_MASK U(0xff) 45 #define TTBR_ASID_SHIFT U(48) 46 47 #define CLIDR_LOUIS_SHIFT U(21) 48 #define CLIDR_LOC_SHIFT U(24) 49 #define CLIDR_FIELD_WIDTH U(3) 50 51 #define CSSELR_LEVEL_SHIFT U(1) 52 53 #define DAIFBIT_FIQ BIT32(0) 54 #define DAIFBIT_IRQ BIT32(1) 55 #define DAIFBIT_ABT BIT32(2) 56 #define DAIFBIT_DBG BIT32(3) 57 #define DAIFBIT_ALL (DAIFBIT_FIQ | DAIFBIT_IRQ | \ 58 DAIFBIT_ABT | DAIFBIT_DBG) 59 60 #define DAIF_F_SHIFT U(6) 61 #define DAIF_F BIT32(6) 62 #define DAIF_I BIT32(7) 63 #define DAIF_A BIT32(8) 64 #define DAIF_D BIT32(9) 65 #define DAIF_AIF (DAIF_A | DAIF_I | DAIF_F) 66 67 #define SPSR_MODE_RW_SHIFT U(4) 68 #define SPSR_MODE_RW_MASK U(0x1) 69 #define SPSR_MODE_RW_64 U(0x0) 70 #define SPSR_MODE_RW_32 U(0x1) 71 72 #define SPSR_64_MODE_SP_SHIFT U(0) 73 #define SPSR_64_MODE_SP_MASK U(0x1) 74 #define SPSR_64_MODE_SP_EL0 U(0x0) 75 #define SPSR_64_MODE_SP_ELX U(0x1) 76 77 #define SPSR_64_MODE_EL_SHIFT U(2) 78 #define SPSR_64_MODE_EL_MASK U(0x3) 79 #define SPSR_64_MODE_EL1 U(0x1) 80 #define SPSR_64_MODE_EL0 U(0x0) 81 82 #define SPSR_64_DAIF_SHIFT U(6) 83 #define SPSR_64_DAIF_MASK U(0xf) 84 85 #define SPSR_64_PAN BIT64(22) 86 87 #define SPSR_32_AIF_SHIFT U(6) 88 #define SPSR_32_AIF_MASK U(0x7) 89 90 #define SPSR_32_E_SHIFT U(9) 91 #define SPSR_32_E_MASK U(0x1) 92 #define SPSR_32_E_LITTLE U(0x0) 93 #define SPSR_32_E_BIG U(0x1) 94 95 #define SPSR_32_T_SHIFT U(5) 96 #define SPSR_32_T_MASK U(0x1) 97 #define SPSR_32_T_ARM U(0x0) 98 #define SPSR_32_T_THUMB U(0x1) 99 100 #define SPSR_32_MODE_SHIFT U(0) 101 #define SPSR_32_MODE_MASK U(0xf) 102 #define SPSR_32_MODE_USR U(0x0) 103 104 105 #define SPSR_64(el, sp, daif) \ 106 (SPSR_MODE_RW_64 << SPSR_MODE_RW_SHIFT | \ 107 ((el) & SPSR_64_MODE_EL_MASK) << SPSR_64_MODE_EL_SHIFT | \ 108 ((sp) & SPSR_64_MODE_SP_MASK) << SPSR_64_MODE_SP_SHIFT | \ 109 ((daif) & SPSR_64_DAIF_MASK) << SPSR_64_DAIF_SHIFT) 110 111 #define SPSR_32(mode, isa, aif) \ 112 (SPSR_MODE_RW_32 << SPSR_MODE_RW_SHIFT | \ 113 SPSR_32_E_LITTLE << SPSR_32_E_SHIFT | \ 114 ((mode) & SPSR_32_MODE_MASK) << SPSR_32_MODE_SHIFT | \ 115 ((isa) & SPSR_32_T_MASK) << SPSR_32_T_SHIFT | \ 116 ((aif) & SPSR_32_AIF_MASK) << SPSR_32_AIF_SHIFT) 117 118 119 #define TCR_T0SZ_SHIFT U(0) 120 #define TCR_EPD0 BIT64(7) 121 #define TCR_IRGN0_SHIFT U(8) 122 #define TCR_ORGN0_SHIFT U(10) 123 #define TCR_SH0_SHIFT U(12) 124 #define TCR_T1SZ_SHIFT U(16) 125 #define TCR_A1 BIT64(22) 126 #define TCR_EPD1 BIT64(23) 127 #define TCR_IRGN1_SHIFT U(24) 128 #define TCR_ORGN1_SHIFT U(26) 129 #define TCR_SH1_SHIFT U(28) 130 #define TCR_EL1_IPS_SHIFT U(32) 131 #define TCR_EL1_IPS_MASK UINT64_C(0x7) 132 #define TCR_TG1_4KB SHIFT_U64(2, 30) 133 #define TCR_RES1 BIT64(31) 134 #define TCR_TBI0 BIT64(37) 135 #define TCR_TBI1 BIT64(38) 136 #define TCR_TCMA0 BIT64(57) 137 #define TCR_TCMA1 BIT64(58) 138 139 140 /* Normal memory, Inner/Outer Non-cacheable */ 141 #define TCR_XRGNX_NC U(0x0) 142 /* Normal memory, Inner/Outer Write-Back Write-Allocate Cacheable */ 143 #define TCR_XRGNX_WB U(0x1) 144 /* Normal memory, Inner/Outer Write-Through Cacheable */ 145 #define TCR_XRGNX_WT U(0x2) 146 /* Normal memory, Inner/Outer Write-Back no Write-Allocate Cacheable */ 147 #define TCR_XRGNX_WBWA U(0x3) 148 149 /* Non-shareable */ 150 #define TCR_SHX_NSH U(0x0) 151 /* Outer Shareable */ 152 #define TCR_SHX_OSH U(0x2) 153 /* Inner Shareable */ 154 #define TCR_SHX_ISH U(0x3) 155 156 #define ESR_EC_SHIFT U(26) 157 #define ESR_EC_MASK U(0x3f) 158 159 #define ESR_EC_UNKNOWN U(0x00) 160 #define ESR_EC_WFI U(0x01) 161 #define ESR_EC_AARCH32_CP15_32 U(0x03) 162 #define ESR_EC_AARCH32_CP15_64 U(0x04) 163 #define ESR_EC_AARCH32_CP14_MR U(0x05) 164 #define ESR_EC_AARCH32_CP14_LS U(0x06) 165 #define ESR_EC_FP_ASIMD U(0x07) 166 #define ESR_EC_AARCH32_CP10_ID U(0x08) 167 #define ESR_EC_PAUTH U(0x09) 168 #define ESR_EC_AARCH32_CP14_64 U(0x0c) 169 #define ESR_EC_BTI U(0x0d) 170 #define ESR_EC_ILLEGAL U(0x0e) 171 #define ESR_EC_AARCH32_SVC U(0x11) 172 #define ESR_EC_AARCH64_SVC U(0x15) 173 #define ESR_EC_AARCH64_SYS U(0x18) 174 #define ESR_EC_ERET U(0x1a) 175 #define ESR_EC_FPAC U(0x1c) 176 #define ESR_EC_IABT_EL0 U(0x20) 177 #define ESR_EC_IABT_EL1 U(0x21) 178 #define ESR_EC_PC_ALIGN U(0x22) 179 #define ESR_EC_DABT_EL0 U(0x24) 180 #define ESR_EC_DABT_EL1 U(0x25) 181 #define ESR_EC_SP_ALIGN U(0x26) 182 #define ESR_EC_AARCH32_FP U(0x28) 183 #define ESR_EC_AARCH64_FP U(0x2c) 184 #define ESR_EC_SERROR U(0x2f) 185 #define ESR_EC_BREAKPT_EL0 U(0x30) 186 #define ESR_EC_BREAKPT_EL1 U(0x31) 187 #define ESR_EC_SOFTSTP_EL0 U(0x32) 188 #define ESR_EC_SOFTSTP_EL1 U(0x33) 189 #define ESR_EC_WATCHPT_EL0 U(0x34) 190 #define ESR_EC_WATCHPT_EL1 U(0x35) 191 #define ESR_EC_AARCH32_BKPT U(0x38) 192 #define ESR_EC_AARCH64_BRK U(0x3c) 193 194 /* Combined defines for DFSC and IFSC */ 195 #define ESR_FSC_MASK U(0x3f) 196 #define ESR_FSC_SIZE_L0 U(0x00) 197 #define ESR_FSC_SIZE_L1 U(0x01) 198 #define ESR_FSC_SIZE_L2 U(0x02) 199 #define ESR_FSC_SIZE_L3 U(0x03) 200 #define ESR_FSC_TRANS_L0 U(0x04) 201 #define ESR_FSC_TRANS_L1 U(0x05) 202 #define ESR_FSC_TRANS_L2 U(0x06) 203 #define ESR_FSC_TRANS_L3 U(0x07) 204 #define ESR_FSC_ACCF_L1 U(0x09) 205 #define ESR_FSC_ACCF_L2 U(0x0a) 206 #define ESR_FSC_ACCF_L3 U(0x0b) 207 #define ESR_FSC_PERMF_L1 U(0x0d) 208 #define ESR_FSC_PERMF_L2 U(0x0e) 209 #define ESR_FSC_PERMF_L3 U(0x0f) 210 #define ESR_FSC_TAG_CHECK U(0x11) 211 #define ESR_FSC_ALIGN U(0x21) 212 213 /* WnR for DABT and RES0 for IABT */ 214 #define ESR_ABT_WNR BIT32(6) 215 216 #define CPACR_EL1_FPEN_SHIFT U(20) 217 #define CPACR_EL1_FPEN_MASK U(0x3) 218 #define CPACR_EL1_FPEN_NONE U(0x0) 219 #define CPACR_EL1_FPEN_EL1 U(0x1) 220 #define CPACR_EL1_FPEN_EL0EL1 U(0x3) 221 #define CPACR_EL1_FPEN(x) ((x) >> CPACR_EL1_FPEN_SHIFT \ 222 & CPACR_EL1_FPEN_MASK) 223 224 225 #define PAR_F BIT32(0) 226 #define PAR_PA_SHIFT U(12) 227 #define PAR_PA_MASK (BIT64(36) - 1) 228 229 #define TLBI_VA_SHIFT U(12) 230 #define TLBI_ASID_SHIFT U(48) 231 #define TLBI_ASID_MASK U(0xff) 232 233 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 234 #define FEAT_BTI_IMPLEMENTED ULL(0x1) 235 236 #define ID_AA64PFR1_EL1_MTE_MASK UL(0xf) 237 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 238 #define FEAT_MTE_NOT_IMPLEMENTED U(0x0) 239 #define FEAT_MTE_IMPLEMENTED U(0x1) 240 #define FEAT_MTE2_IMPLEMENTED U(0x2) 241 #define FEAT_MTE3_IMPLEMENTED U(0x3) 242 243 #define ID_AA64MMFR1_EL1_PAN_MASK UL(0xf) 244 #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20) 245 #define FEAT_PAN_NOT_IMPLEMENTED U(0x0) 246 #define FEAT_PAN_IMPLEMENTED U(0x1) 247 #define FEAT_PAN2_IMPLEMENTED U(0x2) 248 #define FEAT_PAN3_IMPLEMENTED U(0x3) 249 250 #define ID_AA64ISAR0_EL1_CRC32_MASK UL(0xf) 251 #define ID_AA64ISAR0_EL1_CRC32_SHIFT U(16) 252 #define FEAT_CRC32_NOT_IMPLEMENTED U(0x0) 253 #define FEAT_CRC32_IMPLEMENTED U(0x1) 254 255 #define ID_AA64ISAR1_GPI_SHIFT U(28) 256 #define ID_AA64ISAR1_GPI_MASK U(0xf) 257 #define ID_AA64ISAR1_GPI_NI U(0x0) 258 #define ID_AA64ISAR1_GPI_IMP_DEF U(0x1) 259 260 #define ID_AA64ISAR1_GPA_SHIFT U(24) 261 #define ID_AA64ISAR1_GPA_MASK U(0xf) 262 #define ID_AA64ISAR1_GPA_NI U(0x0) 263 #define ID_AA64ISAR1_GPA_ARCHITECTED U(0x1) 264 265 #define ID_AA64ISAR1_API_SHIFT U(8) 266 #define ID_AA64ISAR1_API_MASK U(0xf) 267 #define ID_AA64ISAR1_API_NI U(0x0) 268 #define ID_AA64ISAR1_API_IMP_DEF U(0x1) 269 #define ID_AA64ISAR1_API_IMP_DEF_EPAC U(0x2) 270 #define ID_AA64ISAR1_API_IMP_DEF_EPAC2 U(0x3) 271 #define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC U(0x4) 272 #define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC_CMB U(0x5) 273 274 #define ID_AA64ISAR1_APA_SHIFT U(4) 275 #define ID_AA64ISAR1_APA_MASK U(0xf) 276 #define ID_AA64ISAR1_APA_NI U(0x0) 277 #define ID_AA64ISAR1_APA_ARCHITECTED U(0x1) 278 #define ID_AA64ISAR1_APA_ARCH_EPAC U(0x2) 279 #define ID_AA64ISAR1_APA_ARCH_EPAC2 U(0x3) 280 #define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC U(0x4) 281 #define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC_CMB U(0x5) 282 283 #define ID_MMFR3_EL1_PAN_SHIFT U(16) 284 285 #define GCR_EL1_RRND BIT64(16) 286 287 #ifndef __ASSEMBLER__ 288 static inline __noprof void isb(void) 289 { 290 asm volatile ("isb" : : : "memory"); 291 } 292 293 static inline __noprof void dsb(void) 294 { 295 asm volatile ("dsb sy" : : : "memory"); 296 } 297 298 static inline __noprof void dsb_ish(void) 299 { 300 asm volatile ("dsb ish" : : : "memory"); 301 } 302 303 static inline __noprof void dsb_ishst(void) 304 { 305 asm volatile ("dsb ishst" : : : "memory"); 306 } 307 308 static inline __noprof void dsb_osh(void) 309 { 310 asm volatile ("dsb osh" : : : "memory"); 311 } 312 313 static inline __noprof void sev(void) 314 { 315 asm volatile ("sev" : : : "memory"); 316 } 317 318 static inline __noprof void wfe(void) 319 { 320 asm volatile ("wfe" : : : "memory"); 321 } 322 323 static inline __noprof void wfi(void) 324 { 325 asm volatile ("wfi" : : : "memory"); 326 } 327 328 static inline __noprof void write_at_s1e1r(uint64_t va) 329 { 330 asm volatile ("at S1E1R, %0" : : "r" (va)); 331 } 332 333 static __always_inline __noprof uint64_t read_pc(void) 334 { 335 uint64_t val; 336 337 asm volatile ("adr %0, ." : "=r" (val)); 338 return val; 339 } 340 341 static __always_inline __noprof uint64_t read_fp(void) 342 { 343 uint64_t val; 344 345 asm volatile ("mov %0, x29" : "=r" (val)); 346 return val; 347 } 348 349 static inline __noprof uint64_t read_pmu_ccnt(void) 350 { 351 uint64_t val; 352 353 asm volatile("mrs %0, PMCCNTR_EL0" : "=r"(val)); 354 return val; 355 } 356 357 static inline __noprof void tlbi_vaae1is(uint64_t va) 358 { 359 asm volatile ("tlbi vaae1is, %0" : : "r" (va)); 360 } 361 362 static inline __noprof void tlbi_vale1is(uint64_t va) 363 { 364 asm volatile ("tlbi vale1is, %0" : : "r" (va)); 365 } 366 367 static inline void write_64bit_pair(uint64_t dst, uint64_t hi, uint64_t lo) 368 { 369 /* 128bits should be written to hardware at one time */ 370 asm volatile ("stp %1, %0, [%2]" : : 371 "r" (hi), "r" (lo), "r" (dst) : "memory"); 372 } 373 374 /* 375 * Templates for register read/write functions based on mrs/msr 376 */ 377 378 #define DEFINE_REG_READ_FUNC_(reg, type, asmreg) \ 379 static inline __noprof type read_##reg(void) \ 380 { \ 381 uint64_t val64 = 0; \ 382 \ 383 asm volatile("mrs %0, " #asmreg : "=r" (val64)); \ 384 return val64; \ 385 } 386 387 #define DEFINE_REG_WRITE_FUNC_(reg, type, asmreg) \ 388 static inline __noprof void write_##reg(type val) \ 389 { \ 390 uint64_t val64 = val; \ 391 \ 392 asm volatile("msr " #asmreg ", %0" : : "r" (val64)); \ 393 } 394 395 #define DEFINE_U32_REG_READ_FUNC(reg) \ 396 DEFINE_REG_READ_FUNC_(reg, uint32_t, reg) 397 398 #define DEFINE_U32_REG_WRITE_FUNC(reg) \ 399 DEFINE_REG_WRITE_FUNC_(reg, uint32_t, reg) 400 401 #define DEFINE_U32_REG_READWRITE_FUNCS(reg) \ 402 DEFINE_U32_REG_READ_FUNC(reg) \ 403 DEFINE_U32_REG_WRITE_FUNC(reg) 404 405 #define DEFINE_U64_REG_READ_FUNC(reg) \ 406 DEFINE_REG_READ_FUNC_(reg, uint64_t, reg) 407 408 #define DEFINE_U64_REG_WRITE_FUNC(reg) \ 409 DEFINE_REG_WRITE_FUNC_(reg, uint64_t, reg) 410 411 #define DEFINE_U64_REG_READWRITE_FUNCS(reg) \ 412 DEFINE_U64_REG_READ_FUNC(reg) \ 413 DEFINE_U64_REG_WRITE_FUNC(reg) 414 415 /* 416 * Define register access functions 417 */ 418 419 DEFINE_U32_REG_READWRITE_FUNCS(cpacr_el1) 420 DEFINE_U32_REG_READWRITE_FUNCS(daif) 421 DEFINE_U32_REG_READWRITE_FUNCS(fpcr) 422 DEFINE_U32_REG_READWRITE_FUNCS(fpsr) 423 424 DEFINE_U32_REG_READ_FUNC(ctr_el0) 425 #define read_ctr() read_ctr_el0() 426 DEFINE_U32_REG_READ_FUNC(contextidr_el1) 427 DEFINE_U64_REG_READ_FUNC(sctlr_el1) 428 429 /* ARM Generic timer functions */ 430 DEFINE_REG_READ_FUNC_(cntfrq, uint32_t, cntfrq_el0) 431 DEFINE_REG_READ_FUNC_(cntvct, uint64_t, cntvct_el0) 432 DEFINE_REG_READ_FUNC_(cntpct, uint64_t, cntpct_el0) 433 DEFINE_REG_READ_FUNC_(cntkctl, uint32_t, cntkctl_el1) 434 DEFINE_REG_WRITE_FUNC_(cntkctl, uint32_t, cntkctl_el1) 435 DEFINE_REG_READ_FUNC_(cntps_ctl, uint32_t, cntps_ctl_el1) 436 DEFINE_REG_WRITE_FUNC_(cntps_ctl, uint32_t, cntps_ctl_el1) 437 DEFINE_REG_READ_FUNC_(cntps_tval, uint32_t, cntps_tval_el1) 438 DEFINE_REG_WRITE_FUNC_(cntps_tval, uint32_t, cntps_tval_el1) 439 440 DEFINE_REG_READ_FUNC_(pmccntr, uint64_t, pmccntr_el0) 441 442 DEFINE_U64_REG_READWRITE_FUNCS(ttbr0_el1) 443 DEFINE_U64_REG_READWRITE_FUNCS(ttbr1_el1) 444 DEFINE_U64_REG_READWRITE_FUNCS(tcr_el1) 445 446 DEFINE_U64_REG_READ_FUNC(esr_el1) 447 DEFINE_U64_REG_READ_FUNC(far_el1) 448 DEFINE_U64_REG_READ_FUNC(mpidr_el1) 449 /* Alias for reading this register to avoid ifdefs in code */ 450 #define read_mpidr() read_mpidr_el1() 451 DEFINE_U64_REG_READ_FUNC(midr_el1) 452 /* Alias for reading this register to avoid ifdefs in code */ 453 #define read_midr() read_midr_el1() 454 DEFINE_U64_REG_READ_FUNC(par_el1) 455 456 DEFINE_U64_REG_WRITE_FUNC(mair_el1) 457 458 DEFINE_U64_REG_READ_FUNC(id_aa64mmfr1_el1) 459 DEFINE_U64_REG_READ_FUNC(id_aa64pfr1_el1) 460 DEFINE_U64_REG_READ_FUNC(id_aa64isar0_el1) 461 DEFINE_U64_REG_READ_FUNC(id_aa64isar1_el1) 462 DEFINE_REG_READ_FUNC_(apiakeylo, uint64_t, S3_0_c2_c1_0) 463 DEFINE_REG_READ_FUNC_(apiakeyhi, uint64_t, S3_0_c2_c1_1) 464 465 DEFINE_REG_WRITE_FUNC_(apibkeylo, uint64_t, S3_0_c2_c1_2) 466 DEFINE_REG_WRITE_FUNC_(apibkeyhi, uint64_t, S3_0_c2_c1_3) 467 468 DEFINE_REG_READ_FUNC_(apdakeylo, uint64_t, S3_0_c2_c2_0) 469 DEFINE_REG_READ_FUNC_(apdakeyhi, uint64_t, S3_0_c2_c2_1) 470 471 DEFINE_REG_WRITE_FUNC_(apdbkeylo, uint64_t, S3_0_c2_c2_2) 472 DEFINE_REG_WRITE_FUNC_(apdbkeyhi, uint64_t, S3_0_c2_c2_3) 473 474 DEFINE_REG_WRITE_FUNC_(apgakeylo, uint64_t, S3_0_c2_c3_0) 475 DEFINE_REG_WRITE_FUNC_(apgakeyhi, uint64_t, S3_0_c2_c3_1) 476 477 /* Register read/write functions for GICC registers by using system interface */ 478 DEFINE_REG_READ_FUNC_(icc_ctlr, uint32_t, S3_0_C12_C12_4) 479 DEFINE_REG_WRITE_FUNC_(icc_ctlr, uint32_t, S3_0_C12_C12_4) 480 DEFINE_REG_WRITE_FUNC_(icc_pmr, uint32_t, S3_0_C4_C6_0) 481 DEFINE_REG_READ_FUNC_(icc_iar0, uint32_t, S3_0_c12_c8_0) 482 DEFINE_REG_READ_FUNC_(icc_iar1, uint32_t, S3_0_c12_c12_0) 483 DEFINE_REG_WRITE_FUNC_(icc_eoir0, uint32_t, S3_0_c12_c8_1) 484 DEFINE_REG_WRITE_FUNC_(icc_eoir1, uint32_t, S3_0_c12_c12_1) 485 DEFINE_REG_WRITE_FUNC_(icc_igrpen0, uint32_t, S3_0_C12_C12_6) 486 DEFINE_REG_WRITE_FUNC_(icc_igrpen1, uint32_t, S3_0_C12_C12_7) 487 488 DEFINE_REG_WRITE_FUNC_(pan, uint64_t, S3_0_c4_c2_3) 489 DEFINE_REG_READ_FUNC_(pan, uint64_t, S3_0_c4_c2_3) 490 491 static inline void write_pan_enable(void) 492 { 493 /* msr pan, #1 */ 494 asm volatile("msr S0_0_c4_c1_4, xzr" ::: "memory" ); 495 } 496 497 static inline void write_pan_disable(void) 498 { 499 /* msr pan, #0 */ 500 asm volatile("msr S0_0_c4_c0_4, xzr" ::: "memory" ); 501 } 502 503 #endif /*__ASSEMBLER__*/ 504 505 #endif /*ARM64_H*/ 506 507