1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 */ 5 #ifndef ARM64_H 6 #define ARM64_H 7 8 #include <sys/cdefs.h> 9 #include <stdint.h> 10 #include <util.h> 11 12 #define SCTLR_M BIT32(0) 13 #define SCTLR_A BIT32(1) 14 #define SCTLR_C BIT32(2) 15 #define SCTLR_SA BIT32(3) 16 #define SCTLR_I BIT32(12) 17 #define SCTLR_WXN BIT32(19) 18 19 #define TTBR_ASID_MASK 0xff 20 #define TTBR_ASID_SHIFT 48 21 22 #define CLIDR_LOUIS_SHIFT 21 23 #define CLIDR_LOC_SHIFT 24 24 #define CLIDR_FIELD_WIDTH 3 25 26 #define CSSELR_LEVEL_SHIFT 1 27 28 #define DAIFBIT_FIQ BIT32(0) 29 #define DAIFBIT_IRQ BIT32(1) 30 #define DAIFBIT_ABT BIT32(2) 31 #define DAIFBIT_DBG BIT32(3) 32 #define DAIFBIT_ALL (DAIFBIT_FIQ | DAIFBIT_IRQ | \ 33 DAIFBIT_ABT | DAIFBIT_DBG) 34 35 #define DAIF_F_SHIFT 6 36 #define DAIF_F BIT32(6) 37 #define DAIF_I BIT32(7) 38 #define DAIF_A BIT32(8) 39 #define DAIF_D BIT32(9) 40 #define DAIF_AIF (DAIF_A | DAIF_I | DAIF_F) 41 42 #define SPSR_MODE_RW_SHIFT 4 43 #define SPSR_MODE_RW_MASK 0x1 44 #define SPSR_MODE_RW_64 0x0 45 #define SPSR_MODE_RW_32 0x1 46 47 #define SPSR_64_MODE_SP_SHIFT 0 48 #define SPSR_64_MODE_SP_MASK 0x1 49 #define SPSR_64_MODE_SP_EL0 0x0 50 #define SPSR_64_MODE_SP_ELX 0x1 51 52 #define SPSR_64_MODE_EL_SHIFT 2 53 #define SPSR_64_MODE_EL_MASK 0x3 54 #define SPSR_64_MODE_EL1 0x1 55 #define SPSR_64_MODE_EL0 0x0 56 57 #define SPSR_64_DAIF_SHIFT 6 58 #define SPSR_64_DAIF_MASK 0xf 59 60 #define SPSR_32_AIF_SHIFT 6 61 #define SPSR_32_AIF_MASK 0x7 62 63 #define SPSR_32_E_SHIFT 9 64 #define SPSR_32_E_MASK 0x1 65 #define SPSR_32_E_LITTLE 0x0 66 #define SPSR_32_E_BIG 0x1 67 68 #define SPSR_32_T_SHIFT 5 69 #define SPSR_32_T_MASK 0x1 70 #define SPSR_32_T_ARM 0x0 71 #define SPSR_32_T_THUMB 0x1 72 73 #define SPSR_32_MODE_SHIFT 0 74 #define SPSR_32_MODE_MASK 0xf 75 #define SPSR_32_MODE_USR 0x0 76 77 78 #define SPSR_64(el, sp, daif) \ 79 (SPSR_MODE_RW_64 << SPSR_MODE_RW_SHIFT | \ 80 ((el) & SPSR_64_MODE_EL_MASK) << SPSR_64_MODE_EL_SHIFT | \ 81 ((sp) & SPSR_64_MODE_SP_MASK) << SPSR_64_MODE_SP_SHIFT | \ 82 ((daif) & SPSR_64_DAIF_MASK) << SPSR_64_DAIF_SHIFT) 83 84 #define SPSR_32(mode, isa, aif) \ 85 (SPSR_MODE_RW_32 << SPSR_MODE_RW_SHIFT | \ 86 SPSR_32_E_LITTLE << SPSR_32_E_SHIFT | \ 87 ((mode) & SPSR_32_MODE_MASK) << SPSR_32_MODE_SHIFT | \ 88 ((isa) & SPSR_32_T_MASK) << SPSR_32_T_SHIFT | \ 89 ((aif) & SPSR_32_AIF_MASK) << SPSR_32_AIF_SHIFT) 90 91 92 #define TCR_T0SZ_SHIFT 0 93 #define TCR_EPD0 BIT32(7) 94 #define TCR_IRGN0_SHIFT 8 95 #define TCR_ORGN0_SHIFT 10 96 #define TCR_SH0_SHIFT 12 97 #define TCR_T1SZ_SHIFT 16 98 #define TCR_A1 BIT32(22) 99 #define TCR_EPD1 BIT32(23) 100 #define TCR_IRGN1_SHIFT 24 101 #define TCR_ORGN1_SHIFT 26 102 #define TCR_SH1_SHIFT 28 103 #define TCR_EL1_IPS_SHIFT 32 104 #define TCR_TG1_4KB SHIFT_U32(2, 30) 105 #define TCR_RES1 BIT32(31) 106 107 108 /* Normal memory, Inner/Outer Non-cacheable */ 109 #define TCR_XRGNX_NC 0x0 110 /* Normal memory, Inner/Outer Write-Back Write-Allocate Cacheable */ 111 #define TCR_XRGNX_WB 0x1 112 /* Normal memory, Inner/Outer Write-Through Cacheable */ 113 #define TCR_XRGNX_WT 0x2 114 /* Normal memory, Inner/Outer Write-Back no Write-Allocate Cacheable */ 115 #define TCR_XRGNX_WBWA 0x3 116 117 /* Non-shareable */ 118 #define TCR_SHX_NSH 0x0 119 /* Outer Shareable */ 120 #define TCR_SHX_OSH 0x2 121 /* Inner Shareable */ 122 #define TCR_SHX_ISH 0x3 123 124 #define ESR_EC_SHIFT 26 125 #define ESR_EC_MASK 0x3f 126 127 #define ESR_EC_UNKNOWN 0x00 128 #define ESR_EC_WFI 0x01 129 #define ESR_EC_AARCH32_CP15_32 0x03 130 #define ESR_EC_AARCH32_CP15_64 0x04 131 #define ESR_EC_AARCH32_CP14_MR 0x05 132 #define ESR_EC_AARCH32_CP14_LS 0x06 133 #define ESR_EC_FP_ASIMD 0x07 134 #define ESR_EC_AARCH32_CP10_ID 0x08 135 #define ESR_EC_AARCH32_CP14_64 0x0c 136 #define ESR_EC_ILLEGAL 0x0e 137 #define ESR_EC_AARCH32_SVC 0x11 138 #define ESR_EC_AARCH64_SVC 0x15 139 #define ESR_EC_AARCH64_SYS 0x18 140 #define ESR_EC_IABT_EL0 0x20 141 #define ESR_EC_IABT_EL1 0x21 142 #define ESR_EC_PC_ALIGN 0x22 143 #define ESR_EC_DABT_EL0 0x24 144 #define ESR_EC_DABT_EL1 0x25 145 #define ESR_EC_SP_ALIGN 0x26 146 #define ESR_EC_AARCH32_FP 0x28 147 #define ESR_EC_AARCH64_FP 0x2c 148 #define ESR_EC_SERROR 0x2f 149 #define ESR_EC_BREAKPT_EL0 0x30 150 #define ESR_EC_BREAKPT_EL1 0x31 151 #define ESR_EC_SOFTSTP_EL0 0x32 152 #define ESR_EC_SOFTSTP_EL1 0x33 153 #define ESR_EC_WATCHPT_EL0 0x34 154 #define ESR_EC_WATCHPT_EL1 0x35 155 #define ESR_EC_AARCH32_BKPT 0x38 156 #define ESR_EC_AARCH64_BRK 0x3c 157 158 /* Combined defines for DFSC and IFSC */ 159 #define ESR_FSC_MASK 0x3f 160 #define ESR_FSC_SIZE_L0 0x00 161 #define ESR_FSC_SIZE_L1 0x01 162 #define ESR_FSC_SIZE_L2 0x02 163 #define ESR_FSC_SIZE_L3 0x03 164 #define ESR_FSC_TRANS_L0 0x04 165 #define ESR_FSC_TRANS_L1 0x05 166 #define ESR_FSC_TRANS_L2 0x06 167 #define ESR_FSC_TRANS_L3 0x07 168 #define ESR_FSC_ACCF_L1 0x09 169 #define ESR_FSC_ACCF_L2 0x0a 170 #define ESR_FSC_ACCF_L3 0x0b 171 #define ESR_FSC_PERMF_L1 0x0d 172 #define ESR_FSC_PERMF_L2 0x0e 173 #define ESR_FSC_PERMF_L3 0x0f 174 #define ESR_FSC_ALIGN 0x21 175 176 /* WnR for DABT and RES0 for IABT */ 177 #define ESR_ABT_WNR BIT32(6) 178 179 #define CPACR_EL1_FPEN_SHIFT 20 180 #define CPACR_EL1_FPEN_MASK 0x3 181 #define CPACR_EL1_FPEN_NONE 0x0 182 #define CPACR_EL1_FPEN_EL1 0x1 183 #define CPACR_EL1_FPEN_EL0EL1 0x3 184 #define CPACR_EL1_FPEN(x) ((x) >> CPACR_EL1_FPEN_SHIFT \ 185 & CPACR_EL1_FPEN_MASK) 186 187 188 #define PAR_F BIT32(0) 189 #define PAR_PA_SHIFT 12 190 #define PAR_PA_MASK (BIT64(36) - 1) 191 192 #define TLBI_MVA_SHIFT 12 193 #define TLBI_ASID_SHIFT 48 194 #define TLBI_ASID_MASK 0xff 195 196 #ifndef ASM 197 static inline void isb(void) 198 { 199 asm volatile ("isb"); 200 } 201 202 static inline void dsb(void) 203 { 204 asm volatile ("dsb sy"); 205 } 206 207 static inline void dsb_ish(void) 208 { 209 asm volatile ("dsb ish"); 210 } 211 212 static inline void dsb_ishst(void) 213 { 214 asm volatile ("dsb ishst"); 215 } 216 217 static inline void write_at_s1e1r(uint64_t va) 218 { 219 asm volatile ("at S1E1R, %0" : : "r" (va)); 220 } 221 222 static __always_inline uint64_t read_pc(void) 223 { 224 uint64_t val; 225 226 asm volatile ("adr %0, ." : "=r" (val)); 227 return val; 228 } 229 230 static __always_inline uint64_t read_fp(void) 231 { 232 uint64_t val; 233 234 asm volatile ("mov %0, x29" : "=r" (val)); 235 return val; 236 } 237 238 static inline uint64_t read_pmu_ccnt(void) 239 { 240 uint64_t val; 241 242 asm volatile("mrs %0, PMCCNTR_EL0" : "=r"(val)); 243 return val; 244 } 245 246 static inline void tlbi_vaae1is(uint64_t mva) 247 { 248 asm volatile ("tlbi vaae1is, %0" : : "r" (mva)); 249 } 250 251 /* 252 * Templates for register read/write functions based on mrs/msr 253 */ 254 255 #define DEFINE_REG_READ_FUNC_(reg, type, asmreg) \ 256 static inline type read_##reg(void) \ 257 { \ 258 type val; \ 259 \ 260 asm volatile("mrs %0, " #asmreg : "=r" (val)); \ 261 return val; \ 262 } 263 264 #define DEFINE_REG_WRITE_FUNC_(reg, type, asmreg) \ 265 static inline void write_##reg(type val) \ 266 { \ 267 asm volatile("msr " #asmreg ", %0" : : "r" (val)); \ 268 } 269 270 #define DEFINE_U32_REG_READ_FUNC(reg) \ 271 DEFINE_REG_READ_FUNC_(reg, uint32_t, reg) 272 273 #define DEFINE_U32_REG_WRITE_FUNC(reg) \ 274 DEFINE_REG_WRITE_FUNC_(reg, uint32_t, reg) 275 276 #define DEFINE_U32_REG_READWRITE_FUNCS(reg) \ 277 DEFINE_U32_REG_READ_FUNC(reg) \ 278 DEFINE_U32_REG_WRITE_FUNC(reg) 279 280 #define DEFINE_U64_REG_READ_FUNC(reg) \ 281 DEFINE_REG_READ_FUNC_(reg, uint64_t, reg) 282 283 #define DEFINE_U64_REG_WRITE_FUNC(reg) \ 284 DEFINE_REG_WRITE_FUNC_(reg, uint64_t, reg) 285 286 #define DEFINE_U64_REG_READWRITE_FUNCS(reg) \ 287 DEFINE_U64_REG_READ_FUNC(reg) \ 288 DEFINE_U64_REG_WRITE_FUNC(reg) 289 290 /* 291 * Define register access functions 292 */ 293 294 DEFINE_U32_REG_READWRITE_FUNCS(cpacr_el1) 295 DEFINE_U32_REG_READWRITE_FUNCS(daif) 296 DEFINE_U32_REG_READWRITE_FUNCS(fpcr) 297 DEFINE_U32_REG_READWRITE_FUNCS(fpsr) 298 299 DEFINE_U32_REG_READ_FUNC(contextidr_el1) 300 DEFINE_U32_REG_READ_FUNC(sctlr_el1) 301 302 /* ARM Generic timer functions */ 303 DEFINE_REG_READ_FUNC_(cntfrq, uint32_t, cntfrq_el0) 304 DEFINE_REG_READ_FUNC_(cntpct, uint64_t, cntpct_el0) 305 DEFINE_REG_READ_FUNC_(cntkctl, uint32_t, cntkctl_el1) 306 DEFINE_REG_WRITE_FUNC_(cntkctl, uint32_t, cntkctl_el1) 307 308 DEFINE_U64_REG_READWRITE_FUNCS(ttbr0_el1) 309 DEFINE_U64_REG_READWRITE_FUNCS(ttbr1_el1) 310 DEFINE_U64_REG_READWRITE_FUNCS(tcr_el1) 311 312 DEFINE_U64_REG_READ_FUNC(esr_el1) 313 DEFINE_U64_REG_READ_FUNC(far_el1) 314 DEFINE_U64_REG_READ_FUNC(mpidr_el1) 315 DEFINE_U64_REG_READ_FUNC(midr_el1) 316 /* Alias for reading this register to avoid ifdefs in code */ 317 #define read_midr() read_midr_el1() 318 DEFINE_U64_REG_READ_FUNC(par_el1) 319 320 DEFINE_U64_REG_WRITE_FUNC(mair_el1) 321 322 /* Register read/write functions for GICC registers by using system interface */ 323 DEFINE_REG_READ_FUNC_(icc_ctlr, uint32_t, S3_0_C12_C12_4) 324 DEFINE_REG_WRITE_FUNC_(icc_ctlr, uint32_t, S3_0_C12_C12_4) 325 DEFINE_REG_WRITE_FUNC_(icc_pmr, uint32_t, S3_0_C4_C6_0) 326 DEFINE_REG_READ_FUNC_(icc_iar0, uint32_t, S3_0_c12_c8_0) 327 DEFINE_REG_WRITE_FUNC_(icc_eoir0, uint32_t, S3_0_c12_c8_1) 328 #endif /*ASM*/ 329 330 #endif /*ARM64_H*/ 331 332