1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 */ 5 #ifndef ARM64_H 6 #define ARM64_H 7 8 #include <compiler.h> 9 #include <sys/cdefs.h> 10 #include <stdint.h> 11 #include <util.h> 12 13 #define SCTLR_M BIT32(0) 14 #define SCTLR_A BIT32(1) 15 #define SCTLR_C BIT32(2) 16 #define SCTLR_SA BIT32(3) 17 #define SCTLR_I BIT32(12) 18 #define SCTLR_WXN BIT32(19) 19 #define SCTLR_SPAN BIT32(23) 20 21 #define TTBR_ASID_MASK 0xff 22 #define TTBR_ASID_SHIFT 48 23 24 #define CLIDR_LOUIS_SHIFT 21 25 #define CLIDR_LOC_SHIFT 24 26 #define CLIDR_FIELD_WIDTH 3 27 28 #define CSSELR_LEVEL_SHIFT 1 29 30 #define DAIFBIT_FIQ BIT32(0) 31 #define DAIFBIT_IRQ BIT32(1) 32 #define DAIFBIT_ABT BIT32(2) 33 #define DAIFBIT_DBG BIT32(3) 34 #define DAIFBIT_ALL (DAIFBIT_FIQ | DAIFBIT_IRQ | \ 35 DAIFBIT_ABT | DAIFBIT_DBG) 36 37 #define DAIF_F_SHIFT 6 38 #define DAIF_F BIT32(6) 39 #define DAIF_I BIT32(7) 40 #define DAIF_A BIT32(8) 41 #define DAIF_D BIT32(9) 42 #define DAIF_AIF (DAIF_A | DAIF_I | DAIF_F) 43 44 #define SPSR_MODE_RW_SHIFT 4 45 #define SPSR_MODE_RW_MASK 0x1 46 #define SPSR_MODE_RW_64 0x0 47 #define SPSR_MODE_RW_32 0x1 48 49 #define SPSR_64_MODE_SP_SHIFT 0 50 #define SPSR_64_MODE_SP_MASK 0x1 51 #define SPSR_64_MODE_SP_EL0 0x0 52 #define SPSR_64_MODE_SP_ELX 0x1 53 54 #define SPSR_64_MODE_EL_SHIFT 2 55 #define SPSR_64_MODE_EL_MASK 0x3 56 #define SPSR_64_MODE_EL1 0x1 57 #define SPSR_64_MODE_EL0 0x0 58 59 #define SPSR_64_DAIF_SHIFT 6 60 #define SPSR_64_DAIF_MASK 0xf 61 62 #define SPSR_32_AIF_SHIFT 6 63 #define SPSR_32_AIF_MASK 0x7 64 65 #define SPSR_32_E_SHIFT 9 66 #define SPSR_32_E_MASK 0x1 67 #define SPSR_32_E_LITTLE 0x0 68 #define SPSR_32_E_BIG 0x1 69 70 #define SPSR_32_T_SHIFT 5 71 #define SPSR_32_T_MASK 0x1 72 #define SPSR_32_T_ARM 0x0 73 #define SPSR_32_T_THUMB 0x1 74 75 #define SPSR_32_MODE_SHIFT 0 76 #define SPSR_32_MODE_MASK 0xf 77 #define SPSR_32_MODE_USR 0x0 78 79 80 #define SPSR_64(el, sp, daif) \ 81 (SPSR_MODE_RW_64 << SPSR_MODE_RW_SHIFT | \ 82 ((el) & SPSR_64_MODE_EL_MASK) << SPSR_64_MODE_EL_SHIFT | \ 83 ((sp) & SPSR_64_MODE_SP_MASK) << SPSR_64_MODE_SP_SHIFT | \ 84 ((daif) & SPSR_64_DAIF_MASK) << SPSR_64_DAIF_SHIFT) 85 86 #define SPSR_32(mode, isa, aif) \ 87 (SPSR_MODE_RW_32 << SPSR_MODE_RW_SHIFT | \ 88 SPSR_32_E_LITTLE << SPSR_32_E_SHIFT | \ 89 ((mode) & SPSR_32_MODE_MASK) << SPSR_32_MODE_SHIFT | \ 90 ((isa) & SPSR_32_T_MASK) << SPSR_32_T_SHIFT | \ 91 ((aif) & SPSR_32_AIF_MASK) << SPSR_32_AIF_SHIFT) 92 93 94 #define TCR_T0SZ_SHIFT 0 95 #define TCR_EPD0 BIT32(7) 96 #define TCR_IRGN0_SHIFT 8 97 #define TCR_ORGN0_SHIFT 10 98 #define TCR_SH0_SHIFT 12 99 #define TCR_T1SZ_SHIFT 16 100 #define TCR_A1 BIT32(22) 101 #define TCR_EPD1 BIT32(23) 102 #define TCR_IRGN1_SHIFT 24 103 #define TCR_ORGN1_SHIFT 26 104 #define TCR_SH1_SHIFT 28 105 #define TCR_EL1_IPS_SHIFT 32 106 #define TCR_EL1_IPS_MASK UINT64_C(0x7) 107 #define TCR_TG1_4KB SHIFT_U32(2, 30) 108 #define TCR_RES1 BIT32(31) 109 110 111 /* Normal memory, Inner/Outer Non-cacheable */ 112 #define TCR_XRGNX_NC 0x0 113 /* Normal memory, Inner/Outer Write-Back Write-Allocate Cacheable */ 114 #define TCR_XRGNX_WB 0x1 115 /* Normal memory, Inner/Outer Write-Through Cacheable */ 116 #define TCR_XRGNX_WT 0x2 117 /* Normal memory, Inner/Outer Write-Back no Write-Allocate Cacheable */ 118 #define TCR_XRGNX_WBWA 0x3 119 120 /* Non-shareable */ 121 #define TCR_SHX_NSH 0x0 122 /* Outer Shareable */ 123 #define TCR_SHX_OSH 0x2 124 /* Inner Shareable */ 125 #define TCR_SHX_ISH 0x3 126 127 #define ESR_EC_SHIFT 26 128 #define ESR_EC_MASK 0x3f 129 130 #define ESR_EC_UNKNOWN 0x00 131 #define ESR_EC_WFI 0x01 132 #define ESR_EC_AARCH32_CP15_32 0x03 133 #define ESR_EC_AARCH32_CP15_64 0x04 134 #define ESR_EC_AARCH32_CP14_MR 0x05 135 #define ESR_EC_AARCH32_CP14_LS 0x06 136 #define ESR_EC_FP_ASIMD 0x07 137 #define ESR_EC_AARCH32_CP10_ID 0x08 138 #define ESR_EC_AARCH32_CP14_64 0x0c 139 #define ESR_EC_ILLEGAL 0x0e 140 #define ESR_EC_AARCH32_SVC 0x11 141 #define ESR_EC_AARCH64_SVC 0x15 142 #define ESR_EC_AARCH64_SYS 0x18 143 #define ESR_EC_IABT_EL0 0x20 144 #define ESR_EC_IABT_EL1 0x21 145 #define ESR_EC_PC_ALIGN 0x22 146 #define ESR_EC_DABT_EL0 0x24 147 #define ESR_EC_DABT_EL1 0x25 148 #define ESR_EC_SP_ALIGN 0x26 149 #define ESR_EC_AARCH32_FP 0x28 150 #define ESR_EC_AARCH64_FP 0x2c 151 #define ESR_EC_SERROR 0x2f 152 #define ESR_EC_BREAKPT_EL0 0x30 153 #define ESR_EC_BREAKPT_EL1 0x31 154 #define ESR_EC_SOFTSTP_EL0 0x32 155 #define ESR_EC_SOFTSTP_EL1 0x33 156 #define ESR_EC_WATCHPT_EL0 0x34 157 #define ESR_EC_WATCHPT_EL1 0x35 158 #define ESR_EC_AARCH32_BKPT 0x38 159 #define ESR_EC_AARCH64_BRK 0x3c 160 161 /* Combined defines for DFSC and IFSC */ 162 #define ESR_FSC_MASK 0x3f 163 #define ESR_FSC_SIZE_L0 0x00 164 #define ESR_FSC_SIZE_L1 0x01 165 #define ESR_FSC_SIZE_L2 0x02 166 #define ESR_FSC_SIZE_L3 0x03 167 #define ESR_FSC_TRANS_L0 0x04 168 #define ESR_FSC_TRANS_L1 0x05 169 #define ESR_FSC_TRANS_L2 0x06 170 #define ESR_FSC_TRANS_L3 0x07 171 #define ESR_FSC_ACCF_L1 0x09 172 #define ESR_FSC_ACCF_L2 0x0a 173 #define ESR_FSC_ACCF_L3 0x0b 174 #define ESR_FSC_PERMF_L1 0x0d 175 #define ESR_FSC_PERMF_L2 0x0e 176 #define ESR_FSC_PERMF_L3 0x0f 177 #define ESR_FSC_ALIGN 0x21 178 179 /* WnR for DABT and RES0 for IABT */ 180 #define ESR_ABT_WNR BIT32(6) 181 182 #define CPACR_EL1_FPEN_SHIFT 20 183 #define CPACR_EL1_FPEN_MASK 0x3 184 #define CPACR_EL1_FPEN_NONE 0x0 185 #define CPACR_EL1_FPEN_EL1 0x1 186 #define CPACR_EL1_FPEN_EL0EL1 0x3 187 #define CPACR_EL1_FPEN(x) ((x) >> CPACR_EL1_FPEN_SHIFT \ 188 & CPACR_EL1_FPEN_MASK) 189 190 191 #define PAR_F BIT32(0) 192 #define PAR_PA_SHIFT 12 193 #define PAR_PA_MASK (BIT64(36) - 1) 194 195 #define TLBI_MVA_SHIFT 12 196 #define TLBI_ASID_SHIFT 48 197 #define TLBI_ASID_MASK 0xff 198 199 #ifndef __ASSEMBLER__ 200 static inline __noprof void isb(void) 201 { 202 asm volatile ("isb"); 203 } 204 205 static inline __noprof void dsb(void) 206 { 207 asm volatile ("dsb sy"); 208 } 209 210 static inline __noprof void dsb_ish(void) 211 { 212 asm volatile ("dsb ish"); 213 } 214 215 static inline __noprof void dsb_ishst(void) 216 { 217 asm volatile ("dsb ishst"); 218 } 219 220 static inline __noprof void sev(void) 221 { 222 asm volatile ("sev"); 223 } 224 225 static inline __noprof void wfe(void) 226 { 227 asm volatile ("wfe"); 228 } 229 230 static inline __noprof void write_at_s1e1r(uint64_t va) 231 { 232 asm volatile ("at S1E1R, %0" : : "r" (va)); 233 } 234 235 static __always_inline __noprof uint64_t read_pc(void) 236 { 237 uint64_t val; 238 239 asm volatile ("adr %0, ." : "=r" (val)); 240 return val; 241 } 242 243 static __always_inline __noprof uint64_t read_fp(void) 244 { 245 uint64_t val; 246 247 asm volatile ("mov %0, x29" : "=r" (val)); 248 return val; 249 } 250 251 static inline __noprof uint64_t read_pmu_ccnt(void) 252 { 253 uint64_t val; 254 255 asm volatile("mrs %0, PMCCNTR_EL0" : "=r"(val)); 256 return val; 257 } 258 259 static inline __noprof void tlbi_vaae1is(uint64_t mva) 260 { 261 asm volatile ("tlbi vaae1is, %0" : : "r" (mva)); 262 } 263 264 static inline __noprof void tlbi_vale1is(uint64_t mva) 265 { 266 asm volatile ("tlbi vale1is, %0" : : "r" (mva)); 267 } 268 269 /* 270 * Templates for register read/write functions based on mrs/msr 271 */ 272 273 #define DEFINE_REG_READ_FUNC_(reg, type, asmreg) \ 274 static inline __noprof type read_##reg(void) \ 275 { \ 276 uint64_t val64 = 0; \ 277 \ 278 asm volatile("mrs %0, " #asmreg : "=r" (val64)); \ 279 return val64; \ 280 } 281 282 #define DEFINE_REG_WRITE_FUNC_(reg, type, asmreg) \ 283 static inline __noprof void write_##reg(type val) \ 284 { \ 285 uint64_t val64 = val; \ 286 \ 287 asm volatile("msr " #asmreg ", %0" : : "r" (val64)); \ 288 } 289 290 #define DEFINE_U32_REG_READ_FUNC(reg) \ 291 DEFINE_REG_READ_FUNC_(reg, uint32_t, reg) 292 293 #define DEFINE_U32_REG_WRITE_FUNC(reg) \ 294 DEFINE_REG_WRITE_FUNC_(reg, uint32_t, reg) 295 296 #define DEFINE_U32_REG_READWRITE_FUNCS(reg) \ 297 DEFINE_U32_REG_READ_FUNC(reg) \ 298 DEFINE_U32_REG_WRITE_FUNC(reg) 299 300 #define DEFINE_U64_REG_READ_FUNC(reg) \ 301 DEFINE_REG_READ_FUNC_(reg, uint64_t, reg) 302 303 #define DEFINE_U64_REG_WRITE_FUNC(reg) \ 304 DEFINE_REG_WRITE_FUNC_(reg, uint64_t, reg) 305 306 #define DEFINE_U64_REG_READWRITE_FUNCS(reg) \ 307 DEFINE_U64_REG_READ_FUNC(reg) \ 308 DEFINE_U64_REG_WRITE_FUNC(reg) 309 310 /* 311 * Define register access functions 312 */ 313 314 DEFINE_U32_REG_READWRITE_FUNCS(cpacr_el1) 315 DEFINE_U32_REG_READWRITE_FUNCS(daif) 316 DEFINE_U32_REG_READWRITE_FUNCS(fpcr) 317 DEFINE_U32_REG_READWRITE_FUNCS(fpsr) 318 319 DEFINE_U32_REG_READ_FUNC(ctr_el0) 320 #define read_ctr() read_ctr_el0() 321 DEFINE_U32_REG_READ_FUNC(contextidr_el1) 322 DEFINE_U32_REG_READ_FUNC(sctlr_el1) 323 324 /* ARM Generic timer functions */ 325 DEFINE_REG_READ_FUNC_(cntfrq, uint32_t, cntfrq_el0) 326 DEFINE_REG_READ_FUNC_(cntpct, uint64_t, cntpct_el0) 327 DEFINE_REG_READ_FUNC_(cntkctl, uint32_t, cntkctl_el1) 328 DEFINE_REG_WRITE_FUNC_(cntkctl, uint32_t, cntkctl_el1) 329 DEFINE_REG_READ_FUNC_(cntps_ctl, uint32_t, cntps_ctl_el1) 330 DEFINE_REG_WRITE_FUNC_(cntps_ctl, uint32_t, cntps_ctl_el1) 331 DEFINE_REG_READ_FUNC_(cntps_tval, uint32_t, cntps_tval_el1) 332 DEFINE_REG_WRITE_FUNC_(cntps_tval, uint32_t, cntps_tval_el1) 333 334 DEFINE_REG_READ_FUNC_(pmccntr, uint64_t, pmccntr_el0) 335 336 DEFINE_U64_REG_READWRITE_FUNCS(ttbr0_el1) 337 DEFINE_U64_REG_READWRITE_FUNCS(ttbr1_el1) 338 DEFINE_U64_REG_READWRITE_FUNCS(tcr_el1) 339 340 DEFINE_U64_REG_READ_FUNC(esr_el1) 341 DEFINE_U64_REG_READ_FUNC(far_el1) 342 DEFINE_U64_REG_READ_FUNC(mpidr_el1) 343 /* Alias for reading this register to avoid ifdefs in code */ 344 #define read_mpidr() read_mpidr_el1() 345 DEFINE_U64_REG_READ_FUNC(midr_el1) 346 /* Alias for reading this register to avoid ifdefs in code */ 347 #define read_midr() read_midr_el1() 348 DEFINE_U64_REG_READ_FUNC(par_el1) 349 350 DEFINE_U64_REG_WRITE_FUNC(mair_el1) 351 352 /* Register read/write functions for GICC registers by using system interface */ 353 DEFINE_REG_READ_FUNC_(icc_ctlr, uint32_t, S3_0_C12_C12_4) 354 DEFINE_REG_WRITE_FUNC_(icc_ctlr, uint32_t, S3_0_C12_C12_4) 355 DEFINE_REG_WRITE_FUNC_(icc_pmr, uint32_t, S3_0_C4_C6_0) 356 DEFINE_REG_READ_FUNC_(icc_iar0, uint32_t, S3_0_c12_c8_0) 357 DEFINE_REG_READ_FUNC_(icc_iar1, uint32_t, S3_0_c12_c12_0) 358 DEFINE_REG_WRITE_FUNC_(icc_eoir0, uint32_t, S3_0_c12_c8_1) 359 DEFINE_REG_WRITE_FUNC_(icc_eoir1, uint32_t, S3_0_c12_c12_1) 360 DEFINE_REG_WRITE_FUNC_(icc_igrpen0, uint32_t, S3_0_C12_C12_6) 361 DEFINE_REG_WRITE_FUNC_(icc_igrpen1, uint32_t, S3_0_C12_C12_7) 362 #endif /*__ASSEMBLER__*/ 363 364 #endif /*ARM64_H*/ 365 366