1 /* 2 * Copyright (c) 2015, Linaro Limited 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #ifndef ARM64_H 28 #define ARM64_H 29 30 #ifndef ASM 31 #include <stdint.h> 32 #endif 33 34 #define SCTLR_M (1 << 0) 35 #define SCTLR_A (1 << 1) 36 #define SCTLR_C (1 << 2) 37 #define SCTLR_SA (1 << 3) 38 #define SCTLR_I (1 << 12) 39 40 #define TTBR_ASID_MASK 0xff 41 #define TTBR_ASID_SHIFT 48 42 43 #define CLIDR_LOUIS_SHIFT 21 44 #define CLIDR_LOC_SHIFT 24 45 #define CLIDR_FIELD_WIDTH 3 46 47 #define CSSELR_LEVEL_SHIFT 1 48 49 #define DAIFBIT_FIQ (1 << 0) 50 #define DAIFBIT_IRQ (1 << 1) 51 #define DAIFBIT_ABT (1 << 2) 52 #define DAIFBIT_DBG (1 << 3) 53 #define DAIFBIT_ALL (DAIFBIT_FIQ | DAIFBIT_IRQ | \ 54 DAIFBIT_ABT | DAIFBIT_DBG) 55 56 #define DAIF_F_SHIFT 6 57 #define DAIF_F (1 << 6) 58 #define DAIF_I (1 << 7) 59 #define DAIF_A (1 << 8) 60 #define DAIF_D (1 << 9) 61 #define DAIF_AIF (DAIF_A | DAIF_I | DAIF_F) 62 63 #define SPSR_MODE_RW_SHIFT 4 64 #define SPSR_MODE_RW_MASK 0x1 65 #define SPSR_MODE_RW_64 0x0 66 #define SPSR_MODE_RW_32 0x1 67 68 #define SPSR_64_MODE_SP_SHIFT 0 69 #define SPSR_64_MODE_SP_MASK 0x1 70 #define SPSR_64_MODE_SP_EL0 0x0 71 #define SPSR_64_MODE_SP_ELX 0x1 72 73 #define SPSR_64_MODE_EL_SHIFT 2 74 #define SPSR_64_MODE_EL_MASK 0x3 75 #define SPSR_64_MODE_EL1 0x1 76 #define SPSR_64_MODE_EL0 0x0 77 78 #define SPSR_64_DAIF_SHIFT 6 79 #define SPSR_64_DAIF_MASK 0xf 80 81 #define SPSR_32_AIF_SHIFT 6 82 #define SPSR_32_AIF_MASK 0x7 83 84 #define SPSR_32_E_SHIFT 9 85 #define SPSR_32_E_MASK 0x1 86 #define SPSR_32_E_LITTLE 0x0 87 #define SPSR_32_E_BIG 0x1 88 89 #define SPSR_32_T_SHIFT 5 90 #define SPSR_32_T_MASK 0x1 91 #define SPSR_32_T_ARM 0x0 92 #define SPSR_32_T_THUMB 0x1 93 94 #define SPSR_32_MODE_SHIFT 0 95 #define SPSR_32_MODE_MASK 0xf 96 #define SPSR_32_MODE_USR 0x0 97 98 99 #define SPSR_64(el, sp, daif) \ 100 (SPSR_MODE_RW_64 << SPSR_MODE_RW_SHIFT | \ 101 ((el) & SPSR_64_MODE_EL_MASK) << SPSR_64_MODE_EL_SHIFT | \ 102 ((sp) & SPSR_64_MODE_SP_MASK) << SPSR_64_MODE_SP_SHIFT | \ 103 ((daif) & SPSR_64_DAIF_MASK) << SPSR_64_DAIF_SHIFT) 104 105 #define SPSR_32(mode, isa, aif) \ 106 (SPSR_MODE_RW_32 << SPSR_MODE_RW_SHIFT | \ 107 SPSR_32_E_LITTLE << SPSR_32_E_SHIFT | \ 108 ((mode) & SPSR_32_MODE_MASK) << SPSR_32_MODE_SHIFT | \ 109 ((isa) & SPSR_32_T_MASK) << SPSR_32_T_SHIFT | \ 110 ((aif) & SPSR_32_AIF_MASK) << SPSR_32_AIF_SHIFT) 111 112 113 #define TCR_T0SZ_SHIFT 0 114 #define TCR_EPD0 (1 << 7) 115 #define TCR_IRGN0_SHIFT 8 116 #define TCR_ORGN0_SHIFT 10 117 #define TCR_SH0_SHIFT 12 118 #define TCR_T1SZ_SHIFT 16 119 #define TCR_A1 (1 << 22) 120 #define TCR_EPD1 (1 << 23) 121 #define TCR_IRGN1_SHIFT 24 122 #define TCR_ORGN1_SHIFT 26 123 #define TCR_SH1_SHIFT 28 124 #define TCR_EL1_IPS_SHIFT 32 125 #define TCR_TG1_4KB (2ull << 30) 126 #define TCR_RES1 (1 << 31) 127 128 129 /* Normal memory, Inner/Outer Non-cacheable */ 130 #define TCR_XRGNX_NC 0x0 131 /* Normal memory, Inner/Outer Write-Back Write-Allocate Cacheable */ 132 #define TCR_XRGNX_WB 0x1 133 /* Normal memory, Inner/Outer Write-Through Cacheable */ 134 #define TCR_XRGNX_WT 0x2 135 /* Normal memory, Inner/Outer Write-Back no Write-Allocate Cacheable */ 136 #define TCR_XRGNX_WBWA 0x3 137 138 /* Non-shareable */ 139 #define TCR_SHX_NSH 0x0 140 /* Outer Shareable */ 141 #define TCR_SHX_OSH 0x2 142 /* Inner Shareable */ 143 #define TCR_SHX_ISH 0x3 144 145 #define ESR_EC_SHIFT 26 146 #define ESR_EC_MASK 0x3f 147 148 #define ESR_EC_UNKNOWN 0x00 149 #define ESR_EC_WFI 0x01 150 #define ESR_EC_AARCH32_CP15_32 0x03 151 #define ESR_EC_AARCH32_CP15_64 0x04 152 #define ESR_EC_AARCH32_CP14_MR 0x05 153 #define ESR_EC_AARCH32_CP14_LS 0x06 154 #define ESR_EC_FP_ASIMD 0x07 155 #define ESR_EC_AARCH32_CP10_ID 0x08 156 #define ESR_EC_AARCH32_CP14_64 0x0c 157 #define ESR_EC_ILLEGAL 0x0e 158 #define ESR_EC_AARCH32_SVC 0x11 159 #define ESR_EC_AARCH64_SVC 0x15 160 #define ESR_EC_AARCH64_SYS 0x18 161 #define ESR_EC_IABT_EL0 0x20 162 #define ESR_EC_IABT_EL1 0x21 163 #define ESR_EC_PC_ALIGN 0x22 164 #define ESR_EC_DABT_EL0 0x24 165 #define ESR_EC_DABT_EL1 0x25 166 #define ESR_EC_SP_ALIGN 0x26 167 #define ESR_EC_AARCH32_FP 0x28 168 #define ESR_EC_AARCH64_FP 0x2c 169 #define ESR_EC_SERROR 0x2f 170 #define ESR_EC_BREAKPT_EL0 0x30 171 #define ESR_EC_BREAKPT_EL1 0x31 172 #define ESR_EC_SOFTSTP_EL0 0x32 173 #define ESR_EC_SOFTSTP_EL1 0x33 174 #define ESR_EC_WATCHPT_EL0 0x34 175 #define ESR_EC_WATCHPT_EL1 0x35 176 #define ESR_EC_AARCH32_BKPT 0x38 177 #define ESR_EC_AARCH64_BRK 0x3c 178 179 /* Combined defines for DFSC and IFSC */ 180 #define ESR_FSC_MASK 0x3f 181 #define ESR_FSC_TRANS_L0 0x04 182 #define ESR_FSC_TRANS_L1 0x05 183 #define ESR_FSC_TRANS_L2 0x06 184 #define ESR_FSC_TRANS_L3 0x07 185 #define ESR_FSC_ACCF_L1 0x09 186 #define ESR_FSC_ACCF_L2 0x0a 187 #define ESR_FSC_ACCF_L3 0x0b 188 #define ESR_FSC_PERMF_L1 0x0d 189 #define ESR_FSC_PERMF_L2 0x0e 190 #define ESR_FSC_PERMF_L3 0x0f 191 #define ESR_FSC_ALIGN 0x21 192 193 /* WnR for DABT and RES0 for IABT */ 194 #define ESR_ABT_WNR (1 << 6) 195 196 #define CPACR_EL1_FPEN_SHIFT 20 197 #define CPACR_EL1_FPEN_MASK 0x3 198 #define CPACR_EL1_FPEN_NONE 0x0 199 #define CPACR_EL1_FPEN_EL1 0x1 200 #define CPACR_EL1_FPEN_EL0EL1 0x3 201 #define CPACR_EL1_FPEN(x) ((x) >> CPACR_EL1_FPEN_SHIFT \ 202 & CPACR_EL1_FPEN_MASK) 203 204 205 #define PAR_F (1 << 0) 206 #define PAR_PA_SHIFT 12 207 #define PAR_PA_MASK ((1ULL << 36) - 1) 208 209 #ifndef ASM 210 static inline void isb(void) 211 { 212 asm volatile ("isb"); 213 } 214 215 static inline void dsb(void) 216 { 217 asm volatile ("dsb sy"); 218 } 219 220 static inline void write_at_s1e1r(uint64_t va) 221 { 222 asm volatile ("at S1E1R, %0" : : "r" (va)); 223 } 224 225 /* 226 * Templates for register read/write functions based on mrs/msr 227 */ 228 229 #define DEFINE_REG_READ_FUNC_(reg, type, asmreg) \ 230 static inline type read_##reg(void) \ 231 { \ 232 type val; \ 233 \ 234 asm volatile("mrs %0, " #asmreg : "=r" (val)); \ 235 return val; \ 236 } 237 238 #define DEFINE_REG_WRITE_FUNC_(reg, type, asmreg) \ 239 static inline void write_##reg(type val) \ 240 { \ 241 asm volatile("msr " #asmreg ", %0" : : "r" (val)); \ 242 } 243 244 #define DEFINE_U32_REG_READ_FUNC(reg) \ 245 DEFINE_REG_READ_FUNC_(reg, uint32_t, reg) 246 247 #define DEFINE_U32_REG_WRITE_FUNC(reg) \ 248 DEFINE_REG_WRITE_FUNC_(reg, uint32_t, reg) 249 250 #define DEFINE_U32_REG_READWRITE_FUNCS(reg) \ 251 DEFINE_U32_REG_READ_FUNC(reg) \ 252 DEFINE_U32_REG_WRITE_FUNC(reg) 253 254 #define DEFINE_U64_REG_READ_FUNC(reg) \ 255 DEFINE_REG_READ_FUNC_(reg, uint64_t, reg) 256 257 #define DEFINE_U64_REG_WRITE_FUNC(reg) \ 258 DEFINE_REG_WRITE_FUNC_(reg, uint64_t, reg) 259 260 #define DEFINE_U64_REG_READWRITE_FUNCS(reg) \ 261 DEFINE_U64_REG_READ_FUNC(reg) \ 262 DEFINE_U64_REG_WRITE_FUNC(reg) 263 264 /* 265 * Define register access functions 266 */ 267 268 DEFINE_U32_REG_READWRITE_FUNCS(cpacr_el1) 269 DEFINE_U32_REG_READWRITE_FUNCS(daif) 270 DEFINE_U32_REG_READWRITE_FUNCS(fpcr) 271 DEFINE_U32_REG_READWRITE_FUNCS(fpsr) 272 273 DEFINE_U32_REG_READ_FUNC(contextidr_el1) 274 DEFINE_U32_REG_READ_FUNC(sctlr_el1) 275 276 DEFINE_REG_READ_FUNC_(cntfrq, uint32_t, cntfrq_el0) 277 278 DEFINE_U64_REG_READWRITE_FUNCS(ttbr0_el1) 279 DEFINE_U64_REG_READWRITE_FUNCS(ttbr1_el1) 280 DEFINE_U64_REG_READWRITE_FUNCS(tcr_el1) 281 282 DEFINE_U64_REG_READ_FUNC(esr_el1) 283 DEFINE_U64_REG_READ_FUNC(far_el1) 284 DEFINE_U64_REG_READ_FUNC(mpidr_el1) 285 DEFINE_U64_REG_READ_FUNC(par_el1) 286 287 DEFINE_U64_REG_WRITE_FUNC(mair_el1) 288 289 DEFINE_REG_READ_FUNC_(cntpct, uint64_t, cntpct_el0) 290 291 #endif /*ASM*/ 292 293 #endif /*ARM64_H*/ 294 295