1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 */ 5 #ifndef ARM64_H 6 #define ARM64_H 7 8 #include <sys/cdefs.h> 9 #include <stdint.h> 10 #include <util.h> 11 12 #define SCTLR_M BIT32(0) 13 #define SCTLR_A BIT32(1) 14 #define SCTLR_C BIT32(2) 15 #define SCTLR_SA BIT32(3) 16 #define SCTLR_I BIT32(12) 17 #define SCTLR_WXN BIT32(19) 18 #define SCTLR_SPAN BIT32(23) 19 20 #define TTBR_ASID_MASK 0xff 21 #define TTBR_ASID_SHIFT 48 22 23 #define CLIDR_LOUIS_SHIFT 21 24 #define CLIDR_LOC_SHIFT 24 25 #define CLIDR_FIELD_WIDTH 3 26 27 #define CSSELR_LEVEL_SHIFT 1 28 29 #define DAIFBIT_FIQ BIT32(0) 30 #define DAIFBIT_IRQ BIT32(1) 31 #define DAIFBIT_ABT BIT32(2) 32 #define DAIFBIT_DBG BIT32(3) 33 #define DAIFBIT_ALL (DAIFBIT_FIQ | DAIFBIT_IRQ | \ 34 DAIFBIT_ABT | DAIFBIT_DBG) 35 36 #define DAIF_F_SHIFT 6 37 #define DAIF_F BIT32(6) 38 #define DAIF_I BIT32(7) 39 #define DAIF_A BIT32(8) 40 #define DAIF_D BIT32(9) 41 #define DAIF_AIF (DAIF_A | DAIF_I | DAIF_F) 42 43 #define SPSR_MODE_RW_SHIFT 4 44 #define SPSR_MODE_RW_MASK 0x1 45 #define SPSR_MODE_RW_64 0x0 46 #define SPSR_MODE_RW_32 0x1 47 48 #define SPSR_64_MODE_SP_SHIFT 0 49 #define SPSR_64_MODE_SP_MASK 0x1 50 #define SPSR_64_MODE_SP_EL0 0x0 51 #define SPSR_64_MODE_SP_ELX 0x1 52 53 #define SPSR_64_MODE_EL_SHIFT 2 54 #define SPSR_64_MODE_EL_MASK 0x3 55 #define SPSR_64_MODE_EL1 0x1 56 #define SPSR_64_MODE_EL0 0x0 57 58 #define SPSR_64_DAIF_SHIFT 6 59 #define SPSR_64_DAIF_MASK 0xf 60 61 #define SPSR_32_AIF_SHIFT 6 62 #define SPSR_32_AIF_MASK 0x7 63 64 #define SPSR_32_E_SHIFT 9 65 #define SPSR_32_E_MASK 0x1 66 #define SPSR_32_E_LITTLE 0x0 67 #define SPSR_32_E_BIG 0x1 68 69 #define SPSR_32_T_SHIFT 5 70 #define SPSR_32_T_MASK 0x1 71 #define SPSR_32_T_ARM 0x0 72 #define SPSR_32_T_THUMB 0x1 73 74 #define SPSR_32_MODE_SHIFT 0 75 #define SPSR_32_MODE_MASK 0xf 76 #define SPSR_32_MODE_USR 0x0 77 78 79 #define SPSR_64(el, sp, daif) \ 80 (SPSR_MODE_RW_64 << SPSR_MODE_RW_SHIFT | \ 81 ((el) & SPSR_64_MODE_EL_MASK) << SPSR_64_MODE_EL_SHIFT | \ 82 ((sp) & SPSR_64_MODE_SP_MASK) << SPSR_64_MODE_SP_SHIFT | \ 83 ((daif) & SPSR_64_DAIF_MASK) << SPSR_64_DAIF_SHIFT) 84 85 #define SPSR_32(mode, isa, aif) \ 86 (SPSR_MODE_RW_32 << SPSR_MODE_RW_SHIFT | \ 87 SPSR_32_E_LITTLE << SPSR_32_E_SHIFT | \ 88 ((mode) & SPSR_32_MODE_MASK) << SPSR_32_MODE_SHIFT | \ 89 ((isa) & SPSR_32_T_MASK) << SPSR_32_T_SHIFT | \ 90 ((aif) & SPSR_32_AIF_MASK) << SPSR_32_AIF_SHIFT) 91 92 93 #define TCR_T0SZ_SHIFT 0 94 #define TCR_EPD0 BIT32(7) 95 #define TCR_IRGN0_SHIFT 8 96 #define TCR_ORGN0_SHIFT 10 97 #define TCR_SH0_SHIFT 12 98 #define TCR_T1SZ_SHIFT 16 99 #define TCR_A1 BIT32(22) 100 #define TCR_EPD1 BIT32(23) 101 #define TCR_IRGN1_SHIFT 24 102 #define TCR_ORGN1_SHIFT 26 103 #define TCR_SH1_SHIFT 28 104 #define TCR_EL1_IPS_SHIFT 32 105 #define TCR_EL1_IPS_MASK UINT64_C(0x7) 106 #define TCR_TG1_4KB SHIFT_U32(2, 30) 107 #define TCR_RES1 BIT32(31) 108 109 110 /* Normal memory, Inner/Outer Non-cacheable */ 111 #define TCR_XRGNX_NC 0x0 112 /* Normal memory, Inner/Outer Write-Back Write-Allocate Cacheable */ 113 #define TCR_XRGNX_WB 0x1 114 /* Normal memory, Inner/Outer Write-Through Cacheable */ 115 #define TCR_XRGNX_WT 0x2 116 /* Normal memory, Inner/Outer Write-Back no Write-Allocate Cacheable */ 117 #define TCR_XRGNX_WBWA 0x3 118 119 /* Non-shareable */ 120 #define TCR_SHX_NSH 0x0 121 /* Outer Shareable */ 122 #define TCR_SHX_OSH 0x2 123 /* Inner Shareable */ 124 #define TCR_SHX_ISH 0x3 125 126 #define ESR_EC_SHIFT 26 127 #define ESR_EC_MASK 0x3f 128 129 #define ESR_EC_UNKNOWN 0x00 130 #define ESR_EC_WFI 0x01 131 #define ESR_EC_AARCH32_CP15_32 0x03 132 #define ESR_EC_AARCH32_CP15_64 0x04 133 #define ESR_EC_AARCH32_CP14_MR 0x05 134 #define ESR_EC_AARCH32_CP14_LS 0x06 135 #define ESR_EC_FP_ASIMD 0x07 136 #define ESR_EC_AARCH32_CP10_ID 0x08 137 #define ESR_EC_AARCH32_CP14_64 0x0c 138 #define ESR_EC_ILLEGAL 0x0e 139 #define ESR_EC_AARCH32_SVC 0x11 140 #define ESR_EC_AARCH64_SVC 0x15 141 #define ESR_EC_AARCH64_SYS 0x18 142 #define ESR_EC_IABT_EL0 0x20 143 #define ESR_EC_IABT_EL1 0x21 144 #define ESR_EC_PC_ALIGN 0x22 145 #define ESR_EC_DABT_EL0 0x24 146 #define ESR_EC_DABT_EL1 0x25 147 #define ESR_EC_SP_ALIGN 0x26 148 #define ESR_EC_AARCH32_FP 0x28 149 #define ESR_EC_AARCH64_FP 0x2c 150 #define ESR_EC_SERROR 0x2f 151 #define ESR_EC_BREAKPT_EL0 0x30 152 #define ESR_EC_BREAKPT_EL1 0x31 153 #define ESR_EC_SOFTSTP_EL0 0x32 154 #define ESR_EC_SOFTSTP_EL1 0x33 155 #define ESR_EC_WATCHPT_EL0 0x34 156 #define ESR_EC_WATCHPT_EL1 0x35 157 #define ESR_EC_AARCH32_BKPT 0x38 158 #define ESR_EC_AARCH64_BRK 0x3c 159 160 /* Combined defines for DFSC and IFSC */ 161 #define ESR_FSC_MASK 0x3f 162 #define ESR_FSC_SIZE_L0 0x00 163 #define ESR_FSC_SIZE_L1 0x01 164 #define ESR_FSC_SIZE_L2 0x02 165 #define ESR_FSC_SIZE_L3 0x03 166 #define ESR_FSC_TRANS_L0 0x04 167 #define ESR_FSC_TRANS_L1 0x05 168 #define ESR_FSC_TRANS_L2 0x06 169 #define ESR_FSC_TRANS_L3 0x07 170 #define ESR_FSC_ACCF_L1 0x09 171 #define ESR_FSC_ACCF_L2 0x0a 172 #define ESR_FSC_ACCF_L3 0x0b 173 #define ESR_FSC_PERMF_L1 0x0d 174 #define ESR_FSC_PERMF_L2 0x0e 175 #define ESR_FSC_PERMF_L3 0x0f 176 #define ESR_FSC_ALIGN 0x21 177 178 /* WnR for DABT and RES0 for IABT */ 179 #define ESR_ABT_WNR BIT32(6) 180 181 #define CPACR_EL1_FPEN_SHIFT 20 182 #define CPACR_EL1_FPEN_MASK 0x3 183 #define CPACR_EL1_FPEN_NONE 0x0 184 #define CPACR_EL1_FPEN_EL1 0x1 185 #define CPACR_EL1_FPEN_EL0EL1 0x3 186 #define CPACR_EL1_FPEN(x) ((x) >> CPACR_EL1_FPEN_SHIFT \ 187 & CPACR_EL1_FPEN_MASK) 188 189 190 #define PAR_F BIT32(0) 191 #define PAR_PA_SHIFT 12 192 #define PAR_PA_MASK (BIT64(36) - 1) 193 194 #define TLBI_MVA_SHIFT 12 195 #define TLBI_ASID_SHIFT 48 196 #define TLBI_ASID_MASK 0xff 197 198 #ifndef __ASSEMBLER__ 199 static inline void isb(void) 200 { 201 asm volatile ("isb"); 202 } 203 204 static inline void dsb(void) 205 { 206 asm volatile ("dsb sy"); 207 } 208 209 static inline void dsb_ish(void) 210 { 211 asm volatile ("dsb ish"); 212 } 213 214 static inline void dsb_ishst(void) 215 { 216 asm volatile ("dsb ishst"); 217 } 218 219 static inline void sev(void) 220 { 221 asm volatile ("sev"); 222 } 223 224 static inline void wfe(void) 225 { 226 asm volatile ("wfe"); 227 } 228 229 static inline void write_at_s1e1r(uint64_t va) 230 { 231 asm volatile ("at S1E1R, %0" : : "r" (va)); 232 } 233 234 static __always_inline uint64_t read_pc(void) 235 { 236 uint64_t val; 237 238 asm volatile ("adr %0, ." : "=r" (val)); 239 return val; 240 } 241 242 static __always_inline uint64_t read_fp(void) 243 { 244 uint64_t val; 245 246 asm volatile ("mov %0, x29" : "=r" (val)); 247 return val; 248 } 249 250 static inline uint64_t read_pmu_ccnt(void) 251 { 252 uint64_t val; 253 254 asm volatile("mrs %0, PMCCNTR_EL0" : "=r"(val)); 255 return val; 256 } 257 258 static inline void tlbi_vaae1is(uint64_t mva) 259 { 260 asm volatile ("tlbi vaae1is, %0" : : "r" (mva)); 261 } 262 263 static inline void tlbi_vale1is(uint64_t mva) 264 { 265 asm volatile ("tlbi vale1is, %0" : : "r" (mva)); 266 } 267 268 /* 269 * Templates for register read/write functions based on mrs/msr 270 */ 271 272 #define DEFINE_REG_READ_FUNC_(reg, type, asmreg) \ 273 static inline type read_##reg(void) \ 274 { \ 275 uint64_t val64 = 0; \ 276 \ 277 asm volatile("mrs %0, " #asmreg : "=r" (val64)); \ 278 return val64; \ 279 } 280 281 #define DEFINE_REG_WRITE_FUNC_(reg, type, asmreg) \ 282 static inline void write_##reg(type val) \ 283 { \ 284 uint64_t val64 = val; \ 285 \ 286 asm volatile("msr " #asmreg ", %0" : : "r" (val64)); \ 287 } 288 289 #define DEFINE_U32_REG_READ_FUNC(reg) \ 290 DEFINE_REG_READ_FUNC_(reg, uint32_t, reg) 291 292 #define DEFINE_U32_REG_WRITE_FUNC(reg) \ 293 DEFINE_REG_WRITE_FUNC_(reg, uint32_t, reg) 294 295 #define DEFINE_U32_REG_READWRITE_FUNCS(reg) \ 296 DEFINE_U32_REG_READ_FUNC(reg) \ 297 DEFINE_U32_REG_WRITE_FUNC(reg) 298 299 #define DEFINE_U64_REG_READ_FUNC(reg) \ 300 DEFINE_REG_READ_FUNC_(reg, uint64_t, reg) 301 302 #define DEFINE_U64_REG_WRITE_FUNC(reg) \ 303 DEFINE_REG_WRITE_FUNC_(reg, uint64_t, reg) 304 305 #define DEFINE_U64_REG_READWRITE_FUNCS(reg) \ 306 DEFINE_U64_REG_READ_FUNC(reg) \ 307 DEFINE_U64_REG_WRITE_FUNC(reg) 308 309 /* 310 * Define register access functions 311 */ 312 313 DEFINE_U32_REG_READWRITE_FUNCS(cpacr_el1) 314 DEFINE_U32_REG_READWRITE_FUNCS(daif) 315 DEFINE_U32_REG_READWRITE_FUNCS(fpcr) 316 DEFINE_U32_REG_READWRITE_FUNCS(fpsr) 317 318 DEFINE_U32_REG_READ_FUNC(ctr_el0) 319 DEFINE_U32_REG_READ_FUNC(contextidr_el1) 320 DEFINE_U32_REG_READ_FUNC(sctlr_el1) 321 322 /* ARM Generic timer functions */ 323 DEFINE_REG_READ_FUNC_(cntfrq, uint32_t, cntfrq_el0) 324 DEFINE_REG_READ_FUNC_(cntpct, uint64_t, cntpct_el0) 325 DEFINE_REG_READ_FUNC_(cntkctl, uint32_t, cntkctl_el1) 326 DEFINE_REG_WRITE_FUNC_(cntkctl, uint32_t, cntkctl_el1) 327 DEFINE_REG_READ_FUNC_(cntps_ctl, uint32_t, cntps_ctl_el1) 328 DEFINE_REG_WRITE_FUNC_(cntps_ctl, uint32_t, cntps_ctl_el1) 329 DEFINE_REG_READ_FUNC_(cntps_tval, uint32_t, cntps_tval_el1) 330 DEFINE_REG_WRITE_FUNC_(cntps_tval, uint32_t, cntps_tval_el1) 331 332 DEFINE_REG_READ_FUNC_(pmccntr, uint64_t, pmccntr_el0) 333 334 DEFINE_U64_REG_READWRITE_FUNCS(ttbr0_el1) 335 DEFINE_U64_REG_READWRITE_FUNCS(ttbr1_el1) 336 DEFINE_U64_REG_READWRITE_FUNCS(tcr_el1) 337 338 DEFINE_U64_REG_READ_FUNC(esr_el1) 339 DEFINE_U64_REG_READ_FUNC(far_el1) 340 DEFINE_U64_REG_READ_FUNC(mpidr_el1) 341 /* Alias for reading this register to avoid ifdefs in code */ 342 #define read_mpidr() read_mpidr_el1() 343 DEFINE_U64_REG_READ_FUNC(midr_el1) 344 /* Alias for reading this register to avoid ifdefs in code */ 345 #define read_midr() read_midr_el1() 346 DEFINE_U64_REG_READ_FUNC(par_el1) 347 348 DEFINE_U64_REG_WRITE_FUNC(mair_el1) 349 350 /* Register read/write functions for GICC registers by using system interface */ 351 DEFINE_REG_READ_FUNC_(icc_ctlr, uint32_t, S3_0_C12_C12_4) 352 DEFINE_REG_WRITE_FUNC_(icc_ctlr, uint32_t, S3_0_C12_C12_4) 353 DEFINE_REG_WRITE_FUNC_(icc_pmr, uint32_t, S3_0_C4_C6_0) 354 DEFINE_REG_READ_FUNC_(icc_iar0, uint32_t, S3_0_c12_c8_0) 355 DEFINE_REG_READ_FUNC_(icc_iar1, uint32_t, S3_0_c12_c12_0) 356 DEFINE_REG_WRITE_FUNC_(icc_eoir0, uint32_t, S3_0_c12_c8_1) 357 DEFINE_REG_WRITE_FUNC_(icc_eoir1, uint32_t, S3_0_c12_c12_1) 358 DEFINE_REG_WRITE_FUNC_(icc_igrpen0, uint32_t, S3_0_C12_C12_6) 359 DEFINE_REG_WRITE_FUNC_(icc_igrpen1, uint32_t, S3_0_C12_C12_7) 360 #endif /*__ASSEMBLER__*/ 361 362 #endif /*ARM64_H*/ 363 364