1 /* 2 * Copyright (c) 2015, Linaro Limited 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #ifndef ARM64_H 28 #define ARM64_H 29 30 #include <stdint.h> 31 #include <util.h> 32 33 #define SCTLR_M BIT32(0) 34 #define SCTLR_A BIT32(1) 35 #define SCTLR_C BIT32(2) 36 #define SCTLR_SA BIT32(3) 37 #define SCTLR_I BIT32(12) 38 39 #define TTBR_ASID_MASK 0xff 40 #define TTBR_ASID_SHIFT 48 41 42 #define CLIDR_LOUIS_SHIFT 21 43 #define CLIDR_LOC_SHIFT 24 44 #define CLIDR_FIELD_WIDTH 3 45 46 #define CSSELR_LEVEL_SHIFT 1 47 48 #define DAIFBIT_FIQ BIT32(0) 49 #define DAIFBIT_IRQ BIT32(1) 50 #define DAIFBIT_ABT BIT32(2) 51 #define DAIFBIT_DBG BIT32(3) 52 #define DAIFBIT_ALL (DAIFBIT_FIQ | DAIFBIT_IRQ | \ 53 DAIFBIT_ABT | DAIFBIT_DBG) 54 55 #define DAIF_F_SHIFT 6 56 #define DAIF_F BIT32(6) 57 #define DAIF_I BIT32(7) 58 #define DAIF_A BIT32(8) 59 #define DAIF_D BIT32(9) 60 #define DAIF_AIF (DAIF_A | DAIF_I | DAIF_F) 61 62 #define SPSR_MODE_RW_SHIFT 4 63 #define SPSR_MODE_RW_MASK 0x1 64 #define SPSR_MODE_RW_64 0x0 65 #define SPSR_MODE_RW_32 0x1 66 67 #define SPSR_64_MODE_SP_SHIFT 0 68 #define SPSR_64_MODE_SP_MASK 0x1 69 #define SPSR_64_MODE_SP_EL0 0x0 70 #define SPSR_64_MODE_SP_ELX 0x1 71 72 #define SPSR_64_MODE_EL_SHIFT 2 73 #define SPSR_64_MODE_EL_MASK 0x3 74 #define SPSR_64_MODE_EL1 0x1 75 #define SPSR_64_MODE_EL0 0x0 76 77 #define SPSR_64_DAIF_SHIFT 6 78 #define SPSR_64_DAIF_MASK 0xf 79 80 #define SPSR_32_AIF_SHIFT 6 81 #define SPSR_32_AIF_MASK 0x7 82 83 #define SPSR_32_E_SHIFT 9 84 #define SPSR_32_E_MASK 0x1 85 #define SPSR_32_E_LITTLE 0x0 86 #define SPSR_32_E_BIG 0x1 87 88 #define SPSR_32_T_SHIFT 5 89 #define SPSR_32_T_MASK 0x1 90 #define SPSR_32_T_ARM 0x0 91 #define SPSR_32_T_THUMB 0x1 92 93 #define SPSR_32_MODE_SHIFT 0 94 #define SPSR_32_MODE_MASK 0xf 95 #define SPSR_32_MODE_USR 0x0 96 97 98 #define SPSR_64(el, sp, daif) \ 99 (SPSR_MODE_RW_64 << SPSR_MODE_RW_SHIFT | \ 100 ((el) & SPSR_64_MODE_EL_MASK) << SPSR_64_MODE_EL_SHIFT | \ 101 ((sp) & SPSR_64_MODE_SP_MASK) << SPSR_64_MODE_SP_SHIFT | \ 102 ((daif) & SPSR_64_DAIF_MASK) << SPSR_64_DAIF_SHIFT) 103 104 #define SPSR_32(mode, isa, aif) \ 105 (SPSR_MODE_RW_32 << SPSR_MODE_RW_SHIFT | \ 106 SPSR_32_E_LITTLE << SPSR_32_E_SHIFT | \ 107 ((mode) & SPSR_32_MODE_MASK) << SPSR_32_MODE_SHIFT | \ 108 ((isa) & SPSR_32_T_MASK) << SPSR_32_T_SHIFT | \ 109 ((aif) & SPSR_32_AIF_MASK) << SPSR_32_AIF_SHIFT) 110 111 112 #define TCR_T0SZ_SHIFT 0 113 #define TCR_EPD0 BIT32(7) 114 #define TCR_IRGN0_SHIFT 8 115 #define TCR_ORGN0_SHIFT 10 116 #define TCR_SH0_SHIFT 12 117 #define TCR_T1SZ_SHIFT 16 118 #define TCR_A1 BIT32(22) 119 #define TCR_EPD1 BIT32(23) 120 #define TCR_IRGN1_SHIFT 24 121 #define TCR_ORGN1_SHIFT 26 122 #define TCR_SH1_SHIFT 28 123 #define TCR_EL1_IPS_SHIFT 32 124 #define TCR_TG1_4KB SHIFT_U32(2, 30) 125 #define TCR_RES1 BIT32(31) 126 127 128 /* Normal memory, Inner/Outer Non-cacheable */ 129 #define TCR_XRGNX_NC 0x0 130 /* Normal memory, Inner/Outer Write-Back Write-Allocate Cacheable */ 131 #define TCR_XRGNX_WB 0x1 132 /* Normal memory, Inner/Outer Write-Through Cacheable */ 133 #define TCR_XRGNX_WT 0x2 134 /* Normal memory, Inner/Outer Write-Back no Write-Allocate Cacheable */ 135 #define TCR_XRGNX_WBWA 0x3 136 137 /* Non-shareable */ 138 #define TCR_SHX_NSH 0x0 139 /* Outer Shareable */ 140 #define TCR_SHX_OSH 0x2 141 /* Inner Shareable */ 142 #define TCR_SHX_ISH 0x3 143 144 #define ESR_EC_SHIFT 26 145 #define ESR_EC_MASK 0x3f 146 147 #define ESR_EC_UNKNOWN 0x00 148 #define ESR_EC_WFI 0x01 149 #define ESR_EC_AARCH32_CP15_32 0x03 150 #define ESR_EC_AARCH32_CP15_64 0x04 151 #define ESR_EC_AARCH32_CP14_MR 0x05 152 #define ESR_EC_AARCH32_CP14_LS 0x06 153 #define ESR_EC_FP_ASIMD 0x07 154 #define ESR_EC_AARCH32_CP10_ID 0x08 155 #define ESR_EC_AARCH32_CP14_64 0x0c 156 #define ESR_EC_ILLEGAL 0x0e 157 #define ESR_EC_AARCH32_SVC 0x11 158 #define ESR_EC_AARCH64_SVC 0x15 159 #define ESR_EC_AARCH64_SYS 0x18 160 #define ESR_EC_IABT_EL0 0x20 161 #define ESR_EC_IABT_EL1 0x21 162 #define ESR_EC_PC_ALIGN 0x22 163 #define ESR_EC_DABT_EL0 0x24 164 #define ESR_EC_DABT_EL1 0x25 165 #define ESR_EC_SP_ALIGN 0x26 166 #define ESR_EC_AARCH32_FP 0x28 167 #define ESR_EC_AARCH64_FP 0x2c 168 #define ESR_EC_SERROR 0x2f 169 #define ESR_EC_BREAKPT_EL0 0x30 170 #define ESR_EC_BREAKPT_EL1 0x31 171 #define ESR_EC_SOFTSTP_EL0 0x32 172 #define ESR_EC_SOFTSTP_EL1 0x33 173 #define ESR_EC_WATCHPT_EL0 0x34 174 #define ESR_EC_WATCHPT_EL1 0x35 175 #define ESR_EC_AARCH32_BKPT 0x38 176 #define ESR_EC_AARCH64_BRK 0x3c 177 178 /* Combined defines for DFSC and IFSC */ 179 #define ESR_FSC_MASK 0x3f 180 #define ESR_FSC_TRANS_L0 0x04 181 #define ESR_FSC_TRANS_L1 0x05 182 #define ESR_FSC_TRANS_L2 0x06 183 #define ESR_FSC_TRANS_L3 0x07 184 #define ESR_FSC_ACCF_L1 0x09 185 #define ESR_FSC_ACCF_L2 0x0a 186 #define ESR_FSC_ACCF_L3 0x0b 187 #define ESR_FSC_PERMF_L1 0x0d 188 #define ESR_FSC_PERMF_L2 0x0e 189 #define ESR_FSC_PERMF_L3 0x0f 190 #define ESR_FSC_ALIGN 0x21 191 192 /* WnR for DABT and RES0 for IABT */ 193 #define ESR_ABT_WNR BIT32(6) 194 195 #define CPACR_EL1_FPEN_SHIFT 20 196 #define CPACR_EL1_FPEN_MASK 0x3 197 #define CPACR_EL1_FPEN_NONE 0x0 198 #define CPACR_EL1_FPEN_EL1 0x1 199 #define CPACR_EL1_FPEN_EL0EL1 0x3 200 #define CPACR_EL1_FPEN(x) ((x) >> CPACR_EL1_FPEN_SHIFT \ 201 & CPACR_EL1_FPEN_MASK) 202 203 204 #define PAR_F BIT32(0) 205 #define PAR_PA_SHIFT 12 206 #define PAR_PA_MASK (BIT64(36) - 1) 207 208 #ifndef ASM 209 static inline void isb(void) 210 { 211 asm volatile ("isb"); 212 } 213 214 static inline void dsb(void) 215 { 216 asm volatile ("dsb sy"); 217 } 218 219 static inline void write_at_s1e1r(uint64_t va) 220 { 221 asm volatile ("at S1E1R, %0" : : "r" (va)); 222 } 223 224 /* 225 * Templates for register read/write functions based on mrs/msr 226 */ 227 228 #define DEFINE_REG_READ_FUNC_(reg, type, asmreg) \ 229 static inline type read_##reg(void) \ 230 { \ 231 type val; \ 232 \ 233 asm volatile("mrs %0, " #asmreg : "=r" (val)); \ 234 return val; \ 235 } 236 237 #define DEFINE_REG_WRITE_FUNC_(reg, type, asmreg) \ 238 static inline void write_##reg(type val) \ 239 { \ 240 asm volatile("msr " #asmreg ", %0" : : "r" (val)); \ 241 } 242 243 #define DEFINE_U32_REG_READ_FUNC(reg) \ 244 DEFINE_REG_READ_FUNC_(reg, uint32_t, reg) 245 246 #define DEFINE_U32_REG_WRITE_FUNC(reg) \ 247 DEFINE_REG_WRITE_FUNC_(reg, uint32_t, reg) 248 249 #define DEFINE_U32_REG_READWRITE_FUNCS(reg) \ 250 DEFINE_U32_REG_READ_FUNC(reg) \ 251 DEFINE_U32_REG_WRITE_FUNC(reg) 252 253 #define DEFINE_U64_REG_READ_FUNC(reg) \ 254 DEFINE_REG_READ_FUNC_(reg, uint64_t, reg) 255 256 #define DEFINE_U64_REG_WRITE_FUNC(reg) \ 257 DEFINE_REG_WRITE_FUNC_(reg, uint64_t, reg) 258 259 #define DEFINE_U64_REG_READWRITE_FUNCS(reg) \ 260 DEFINE_U64_REG_READ_FUNC(reg) \ 261 DEFINE_U64_REG_WRITE_FUNC(reg) 262 263 /* 264 * Define register access functions 265 */ 266 267 DEFINE_U32_REG_READWRITE_FUNCS(cpacr_el1) 268 DEFINE_U32_REG_READWRITE_FUNCS(daif) 269 DEFINE_U32_REG_READWRITE_FUNCS(fpcr) 270 DEFINE_U32_REG_READWRITE_FUNCS(fpsr) 271 272 DEFINE_U32_REG_READ_FUNC(contextidr_el1) 273 DEFINE_U32_REG_READ_FUNC(sctlr_el1) 274 275 DEFINE_REG_READ_FUNC_(cntfrq, uint32_t, cntfrq_el0) 276 277 DEFINE_U64_REG_READWRITE_FUNCS(ttbr0_el1) 278 DEFINE_U64_REG_READWRITE_FUNCS(ttbr1_el1) 279 DEFINE_U64_REG_READWRITE_FUNCS(tcr_el1) 280 281 DEFINE_U64_REG_READ_FUNC(esr_el1) 282 DEFINE_U64_REG_READ_FUNC(far_el1) 283 DEFINE_U64_REG_READ_FUNC(mpidr_el1) 284 DEFINE_U64_REG_READ_FUNC(par_el1) 285 286 DEFINE_U64_REG_WRITE_FUNC(mair_el1) 287 288 DEFINE_REG_READ_FUNC_(cntpct, uint64_t, cntpct_el0) 289 290 #endif /*ASM*/ 291 292 #endif /*ARM64_H*/ 293 294