1/* 2 * Copyright (c) 2014, STMicroelectronics International N.V. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* Please keep them sorted based on the CRn register */ 29 .macro read_mpidr reg 30 mrc p15, 0, \reg, c0, c0, 5 31 .endm 32 33 .macro read_sctlr reg 34 mrc p15, 0, \reg, c1, c0, 0 35 .endm 36 37 .macro write_sctlr reg 38 mcr p15, 0, \reg, c1, c0, 0 39 .endm 40 41 .macro write_actlr reg 42 mcr p15, 0, \reg, c1, c0, 1 43 .endm 44 45 .macro read_scr reg 46 mrc p15, 0, \reg, c1, c1, 0 47 .endm 48 49 .macro write_scr reg 50 mcr p15, 0, \reg, c1, c1, 0 51 .endm 52 53 .macro write_nsacr reg 54 mcr p15, 0, \reg, c1, c1, 2 55 .endm 56 57 .macro write_ttbr0 reg 58 mcr p15, 0, \reg, c2, c0, 0 59 .endm 60 61 .macro write_dacr reg 62 mcr p15, 0, \reg, c3, c0, 0 63 .endm 64 65 .macro read_dfsr reg 66 mrc p15, 0, \reg, c5, c0, 0 67 .endm 68 69 .macro write_iciallu 70 /* Invalidate all instruction caches to PoU (register ignored) */ 71 mcr p15, 0, r0, c7, c5, 0 72 .endm 73 74 .macro write_bpiall 75 /* Invalidate entire branch predictor array (register ignored) */ 76 mcr p15, 0, r0, c7, c5, 0 77 .endm 78 79 .macro write_tlbiall 80 /* Invalidate entire unified TLB (register ignored) */ 81 mcr p15, 0, r0, c8, c7, 0 82 .endm 83 84 .macro write_tlbiallis 85 /* Invalidate entire unified TLB Inner Sharable (register ignored) */ 86 mcr p15, 0, r0, c8, c3, 0 87 .endm 88 89 .macro write_tlbiasidis reg 90 /* Invalidate unified TLB by ASID Inner Sharable */ 91 mcr p15, 0, \reg, c8, c3, 2 92 .endm 93 94 .macro write_vbar reg 95 mcr p15, 0, \reg, c12, c0, 0 96 .endm 97 98 .macro write_mvbar reg 99 mcr p15, 0, \reg, c12, c0, 1 100 .endm 101 102 .macro write_contextidr reg 103 mcr p15, 0, \reg, c13, c0, 1 104 .endm 105 106 .macro read_contextidr reg 107 mrc p15, 0, \reg, c13, c0, 1 108 .endm 109 110 .macro write_pcr reg 111 mcr p15, 0, \reg, c15, c0, 0 112 .endm 113 114 .macro read_actlr reg 115 mrc p15, 0, \reg, c1, c0, 1 116 .endm 117 118 .macro read_nsacr reg 119 mrc p15, 0, \reg, c1, c1, 2 120 .endm 121 122