1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2016, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 * Copyright (c) 2026, Arm Limited 6 */ 7 8 #ifndef __ARM32_H 9 #define __ARM32_H 10 11 #include <compiler.h> 12 #include <sys/cdefs.h> 13 #include <stdint.h> 14 #include <util.h> 15 16 #define CPSR_MODE_MASK ARM32_CPSR_MODE_MASK 17 #define CPSR_MODE_USR ARM32_CPSR_MODE_USR 18 #define CPSR_MODE_FIQ ARM32_CPSR_MODE_FIQ 19 #define CPSR_MODE_IRQ ARM32_CPSR_MODE_IRQ 20 #define CPSR_MODE_SVC ARM32_CPSR_MODE_SVC 21 #define CPSR_MODE_MON ARM32_CPSR_MODE_MON 22 #define CPSR_MODE_ABT ARM32_CPSR_MODE_ABT 23 #define CPSR_MODE_UND ARM32_CPSR_MODE_UND 24 #define CPSR_MODE_SYS ARM32_CPSR_MODE_SYS 25 26 #define CPSR_T ARM32_CPSR_T 27 #define CPSR_F_SHIFT ARM32_CPSR_F_SHIFT 28 #define CPSR_F ARM32_CPSR_F 29 #define CPSR_I ARM32_CPSR_I 30 #define CPSR_A ARM32_CPSR_A 31 #define CPSR_FIA ARM32_CPSR_FIA 32 #define CPSR_IT_MASK ARM32_CPSR_IT_MASK 33 #define CPSR_IT_MASK1 ARM32_CPSR_IT_MASK1 34 #define CPSR_IT_MASK2 ARM32_CPSR_IT_MASK2 35 36 #define PMCR_DP BIT32(5) 37 38 #define SCR_NS BIT32(0) 39 #define SCR_IRQ BIT32(1) 40 #define SCR_FIQ BIT32(2) 41 #define SCR_EA BIT32(3) 42 #define SCR_FW BIT32(4) 43 #define SCR_AW BIT32(5) 44 #define SCR_NET BIT32(6) 45 #define SCR_SCD BIT32(7) 46 #define SCR_HCE BIT32(8) 47 #define SCR_SIF BIT32(9) 48 49 #define SCTLR_M BIT32(0) 50 #define SCTLR_A BIT32(1) 51 #define SCTLR_C BIT32(2) 52 #define SCTLR_CP15BEN BIT32(5) 53 #define SCTLR_SW BIT32(10) 54 #define SCTLR_Z BIT32(11) 55 #define SCTLR_I BIT32(12) 56 #define SCTLR_V BIT32(13) 57 #define SCTLR_RR BIT32(14) 58 #define SCTLR_HA BIT32(17) 59 #define SCTLR_WXN BIT32(19) 60 #define SCTLR_UWXN BIT32(20) 61 #define SCTLR_FI BIT32(21) 62 #define SCTLR_SPAN BIT32(23) 63 #define SCTLR_VE BIT32(24) 64 #define SCTLR_EE BIT32(25) 65 #define SCTLR_NMFI BIT32(27) 66 #define SCTLR_TRE BIT32(28) 67 #define SCTLR_AFE BIT32(29) 68 #define SCTLR_TE BIT32(30) 69 70 /* Only valid for Cortex-A15 */ 71 #define ACTLR_CA15_ENABLE_INVALIDATE_BTB BIT(0) 72 /* Only valid for Cortex-A8 */ 73 #define ACTLR_CA8_ENABLE_INVALIDATE_BTB BIT(6) 74 /* Only valid for Cortex-A9 */ 75 #define ACTLR_CA9_WFLZ BIT(3) 76 77 #define ACTLR_SMP BIT32(6) 78 79 #define NSACR_CP10 BIT32(10) 80 #define NSACR_CP11 BIT32(11) 81 #define NSACR_NSD32DIS BIT32(14) 82 #define NSACR_NSASEDIS BIT32(15) 83 #define NSACR_NS_L2ERR BIT32(17) 84 #define NSACR_NS_SMP BIT32(18) 85 86 #define CPACR_ASEDIS BIT32(31) 87 #define CPACR_D32DIS BIT32(30) 88 #define CPACR_CP(co_proc, access) SHIFT_U32((access), ((co_proc) * 2)) 89 #define CPACR_CP_ACCESS_DENIED U(0x0) 90 #define CPACR_CP_ACCESS_PL1_ONLY U(0x1) 91 #define CPACR_CP_ACCESS_FULL U(0x3) 92 93 94 #define DACR_DOMAIN(num, perm) SHIFT_U32((perm), ((num) * 2)) 95 #define DACR_DOMAIN_PERM_NO_ACCESS U(0x0) 96 #define DACR_DOMAIN_PERM_CLIENT U(0x1) 97 #define DACR_DOMAIN_PERM_MANAGER U(0x3) 98 99 #define PAR_F BIT32(0) 100 #define PAR_SS BIT32(1) 101 #define PAR_LPAE BIT32(11) 102 #define PAR_PA_SHIFT U(12) 103 #define PAR32_PA_MASK (BIT32(20) - 1) 104 #define PAR64_PA_MASK (BIT64(28) - 1) 105 106 /* 107 * TTBCR has different register layout if LPAE is enabled or not. 108 * TTBCR.EAE == 0 => LPAE is not enabled 109 * TTBCR.EAE == 1 => LPAE is enabled 110 */ 111 #define TTBCR_EAE BIT32(31) 112 113 /* When TTBCR.EAE == 0 */ 114 #define TTBCR_PD0 BIT32(4) 115 #define TTBCR_PD1 BIT32(5) 116 117 /* When TTBCR.EAE == 1 */ 118 #define TTBCR_T0SZ_SHIFT U(0) 119 #define TTBCR_EPD0 BIT32(7) 120 #define TTBCR_IRGN0_SHIFT U(8) 121 #define TTBCR_ORGN0_SHIFT U(10) 122 #define TTBCR_SH0_SHIFT U(12) 123 #define TTBCR_T1SZ_SHIFT U(16) 124 #define TTBCR_A1 BIT32(22) 125 #define TTBCR_EPD1 BIT32(23) 126 #define TTBCR_IRGN1_SHIFT U(24) 127 #define TTBCR_ORGN1_SHIFT U(26) 128 #define TTBCR_SH1_SHIFT U(28) 129 130 /* Normal memory, Inner/Outer Non-cacheable */ 131 #define TTBCR_XRGNX_NC U(0x0) 132 /* Normal memory, Inner/Outer Write-Back Write-Allocate Cacheable */ 133 #define TTBCR_XRGNX_WB U(0x1) 134 /* Normal memory, Inner/Outer Write-Through Cacheable */ 135 #define TTBCR_XRGNX_WT U(0x2) 136 /* Normal memory, Inner/Outer Write-Back no Write-Allocate Cacheable */ 137 #define TTBCR_XRGNX_WBWA U(0x3) 138 139 /* Non-shareable */ 140 #define TTBCR_SHX_NSH U(0x0) 141 /* Outer Shareable */ 142 #define TTBCR_SHX_OSH U(0x2) 143 /* Inner Shareable */ 144 #define TTBCR_SHX_ISH U(0x3) 145 146 #define TTBR_ASID_MASK U(0xff) 147 #define TTBR_ASID_SHIFT U(48) 148 149 #define TLBI_MVA_SHIFT U(12) 150 #define TLBI_ASID_MASK U(0xff) 151 152 #define FSR_LPAE BIT32(9) 153 #define FSR_WNR BIT32(11) 154 155 /* Valid if FSR.LPAE is 1 */ 156 #define FSR_STATUS_MASK (BIT32(6) - 1) 157 158 /* Valid if FSR.LPAE is 0 */ 159 #define FSR_FS_MASK (BIT32(10) | (BIT32(4) - 1)) 160 161 /* ID_PFR1 bit fields */ 162 #define IDPFR1_VIRT_SHIFT U(12) 163 #define IDPFR1_VIRT_MASK SHIFT_U32(0xF, IDPFR1_VIRT_SHIFT) 164 #define IDPFR1_GENTIMER_SHIFT U(16) 165 #define IDPFR1_GENTIMER_MASK SHIFT_U32(0xF, IDPFR1_GENTIMER_SHIFT) 166 167 #ifndef __ASSEMBLER__ 168 #include <generated/arm32_sysreg.h> 169 #ifdef _CFG_ARM_V3_OR_V4 170 #include <generated/arm32_gicv3_sysreg.h> 171 #endif 172 173 static inline __noprof void isb(void) 174 { 175 asm volatile ("isb" : : : "memory"); 176 } 177 178 static inline __noprof void dsb(void) 179 { 180 asm volatile ("dsb" : : : "memory"); 181 } 182 183 static inline __noprof void dsb_ish(void) 184 { 185 asm volatile ("dsb ish" : : : "memory"); 186 } 187 188 static inline __noprof void dsb_ishst(void) 189 { 190 asm volatile ("dsb ishst" : : : "memory"); 191 } 192 193 static inline __noprof void dmb(void) 194 { 195 asm volatile ("dmb" : : : "memory"); 196 } 197 198 static inline __noprof void sev(void) 199 { 200 asm volatile ("sev" : : : "memory"); 201 } 202 203 static inline __noprof void wfe(void) 204 { 205 asm volatile ("wfe" : : : "memory"); 206 } 207 208 static inline __noprof uint32_t read_cpsr(void) 209 { 210 uint32_t cpsr; 211 212 asm volatile ("mrs %[cpsr], cpsr" 213 : [cpsr] "=r" (cpsr) 214 ); 215 return cpsr; 216 } 217 218 static inline __noprof void write_cpsr(uint32_t cpsr) 219 { 220 asm volatile ("msr cpsr_fsxc, %[cpsr]" 221 : : [cpsr] "r" (cpsr) 222 ); 223 } 224 225 static inline __noprof uint32_t read_spsr(void) 226 { 227 uint32_t spsr; 228 229 asm volatile ("mrs %[spsr], spsr" 230 : [spsr] "=r" (spsr) 231 ); 232 return spsr; 233 } 234 235 static inline __noprof void wfi(void) 236 { 237 asm volatile("wfi" : : : "memory"); 238 } 239 240 static __always_inline __noprof uint32_t read_pc(void) 241 { 242 uint32_t val; 243 244 asm volatile ("adr %0, ." : "=r" (val)); 245 return val; 246 } 247 248 static __always_inline __noprof uint32_t read_sp(void) 249 { 250 uint32_t val; 251 252 asm volatile ("mov %0, sp" : "=r" (val)); 253 return val; 254 } 255 256 static __always_inline __noprof uint32_t read_lr(void) 257 { 258 uint32_t val; 259 260 asm volatile ("mov %0, lr" : "=r" (val)); 261 return val; 262 } 263 264 static __always_inline __noprof uint32_t read_fp(void) 265 { 266 uint32_t val; 267 268 asm volatile ("mov %0, fp" : "=r" (val)); 269 return val; 270 } 271 272 static __always_inline __noprof uint32_t read_r7(void) 273 { 274 uint32_t val; 275 276 asm volatile ("mov %0, r7" : "=r" (val)); 277 return val; 278 } 279 280 #endif /*__ASSEMBLER__*/ 281 282 #endif /*__ARM32_H*/ 283