1 /* 2 * Copyright (c) 2014, STMicroelectronics International N.V. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #ifndef ARM32_H 29 #define ARM32_H 30 31 #ifndef ASM 32 #include <stdint.h> 33 #endif 34 35 #define CPSR_MODE_MASK ARM32_CPSR_MODE_MASK 36 #define CPSR_MODE_USR ARM32_CPSR_MODE_USR 37 #define CPSR_MODE_FIQ ARM32_CPSR_MODE_FIQ 38 #define CPSR_MODE_IRQ ARM32_CPSR_MODE_IRQ 39 #define CPSR_MODE_SVC ARM32_CPSR_MODE_SVC 40 #define CPSR_MODE_MON ARM32_CPSR_MODE_MON 41 #define CPSR_MODE_ABT ARM32_CPSR_MODE_ABT 42 #define CPSR_MODE_UND ARM32_CPSR_MODE_UND 43 #define CPSR_MODE_SYS ARM32_CPSR_MODE_SYS 44 45 #define CPSR_T ARM32_CPSR_T 46 #define CPSR_F_SHIFT ARM32_CPSR_F_SHIFT 47 #define CPSR_F ARM32_CPSR_F 48 #define CPSR_I ARM32_CPSR_I 49 #define CPSR_A ARM32_CPSR_A 50 #define CPSR_FIA ARM32_CPSR_FIA 51 #define CPSR_IT_MASK ARM32_CPSR_IT_MASK 52 #define CPSR_IT_MASK1 ARM32_CPSR_IT_MASK1 53 #define CPSR_IT_MASK2 ARM32_CPSR_IT_MASK2 54 55 #define SCR_NS (1 << 0) 56 #define SCR_IRQ (1 << 1) 57 #define SCR_FIQ (1 << 2) 58 #define SCR_EA (1 << 3) 59 #define SCR_FW (1 << 4) 60 #define SCR_AW (1 << 5) 61 #define SCR_NET (1 << 6) 62 #define SCR_SCD (1 << 7) 63 #define SCR_HCE (1 << 8) 64 #define SCR_SIF (1 << 9) 65 66 #define SCTLR_M (1 << 0) 67 #define SCTLR_A (1 << 1) 68 #define SCTLR_C (1 << 2) 69 #define SCTLR_CP15BEN (1 << 5) 70 #define SCTLR_SW (1 << 10) 71 #define SCTLR_Z (1 << 11) 72 #define SCTLR_I (1 << 12) 73 #define SCTLR_V (1 << 13) 74 #define SCTLR_RR (1 << 14) 75 #define SCTLR_HA (1 << 17) 76 #define SCTLR_WXN (1 << 19) 77 #define SCTLR_UWXN (1 << 20) 78 #define SCTLR_FI (1 << 21) 79 #define SCTLR_VE (1 << 24) 80 #define SCTLR_EE (1 << 25) 81 #define SCTLR_NMFI (1 << 26) 82 #define SCTLR_TRE (1 << 28) 83 #define SCTLR_AFE (1 << 29) 84 #define SCTLR_TE (1 << 30) 85 86 #define ACTLR_SMP (1 << 6) 87 #define ACTLR_DODMBS (1 << 10) 88 #define ACTLR_L2RADIS (1 << 11) 89 #define ACTLR_L1RADIS (1 << 12) 90 #define ACTLR_L1PCTL (1 << 13) 91 #define ACTLR_DDVM (1 << 15) 92 #define ACTLR_DDI (1 << 28) 93 94 #define NSACR_CP10 (1 << 10) 95 #define NSACR_CP11 (1 << 11) 96 #define NSACR_NSD32DIS (1 << 14) 97 #define NSACR_NSASEDIS (1 << 15) 98 #define NSACR_NS_L2ERR (1 << 17) 99 #define NSACR_NS_SMP (1 << 18) 100 101 #define CPACR_CP(co_proc, access) ((access) << ((co_proc) * 2)) 102 #define CPACR_CP_ACCESS_DENIED 0x0 103 #define CPACR_CP_ACCESS_PL1_ONLY 0x1 104 #define CPACR_CP_ACCESS_FULL 0x2 105 106 107 #define DACR_DOMAIN(num, perm) ((perm) << ((num) * 2)) 108 #define DACR_DOMAIN_PERM_NO_ACCESS 0x0 109 #define DACR_DOMAIN_PERM_CLIENT 0x1 110 #define DACR_DOMAIN_PERM_MANAGER 0x3 111 112 /* 113 * TTBCR has different register layout if LPAE is enabled or not. 114 * TTBCR.EAE == 0 => LPAE is not enabled 115 * TTBCR.EAE == 1 => LPAE is enabled 116 */ 117 #define TTBCR_EAE (1 << 31) 118 119 /* When TTBCR.EAE == 0 */ 120 #define TTBCR_PD0 (1 << 4) 121 #define TTBCR_PD1 (1 << 5) 122 123 /* When TTBCR.EAE == 1 */ 124 #define TTBCR_T0SZ_SHIFT 0 125 #define TTBCR_EPD0 (1 << 7) 126 #define TTBCR_IRGN0_SHIFT 8 127 #define TTBCR_ORGN0_SHIFT 10 128 #define TTBCR_SH0_SHIFT 12 129 #define TTBCR_T1SZ_SHIFT 16 130 #define TTBCR_A1 (1 << 22) 131 #define TTBCR_EPD1 (1 << 23) 132 #define TTBCR_IRGN1_SHIFT 24 133 #define TTBCR_ORGN1_SHIFT 26 134 #define TTBCR_SH1_SHIFT 28 135 136 /* Normal memory, Inner/Outer Non-cacheable */ 137 #define TTBCR_XRGNX_NC 0x0 138 /* Normal memory, Inner/Outer Write-Back Write-Allocate Cacheable */ 139 #define TTBCR_XRGNX_WB 0x1 140 /* Normal memory, Inner/Outer Write-Through Cacheable */ 141 #define TTBCR_XRGNX_WT 0x2 142 /* Normal memory, Inner/Outer Write-Back no Write-Allocate Cacheable */ 143 #define TTBCR_XRGNX_WBWA 0x3 144 145 /* Non-shareable */ 146 #define TTBCR_SHX_NSH 0x0 147 /* Outer Shareable */ 148 #define TTBCR_SHX_OSH 0x2 149 /* Inner Shareable */ 150 #define TTBCR_SHX_ISH 0x3 151 152 #define TTBR_ASID_MASK 0xff 153 #define TTBR_ASID_SHIFT 48 154 155 156 #define FSR_LPAE (1 << 9) 157 158 /* Valid if FSR.LPAE is 1 */ 159 #define FSR_STATUS_MASK ((1 << 6) - 1) 160 161 /* Valid if FSR.LPAE is 0 */ 162 #define FSR_FS_MASK ((1 << 10) | ((1 << 3) - 1)) 163 164 #ifndef ASM 165 static inline uint32_t read_mpidr(void) 166 { 167 uint32_t mpidr; 168 169 asm volatile ("mrc p15, 0, %[mpidr], c0, c0, 5" 170 : [mpidr] "=r" (mpidr) 171 ); 172 173 return mpidr; 174 } 175 176 static inline uint32_t read_sctlr(void) 177 { 178 uint32_t sctlr; 179 180 asm volatile ("mrc p15, 0, %[sctlr], c1, c0, 0" 181 : [sctlr] "=r" (sctlr) 182 ); 183 184 return sctlr; 185 } 186 187 static inline void write_sctlr(uint32_t sctlr) 188 { 189 asm volatile ("mcr p15, 0, %[sctlr], c1, c0, 0" 190 : : [sctlr] "r" (sctlr) 191 ); 192 } 193 194 static inline uint32_t read_cpacr(void) 195 { 196 uint32_t cpacr; 197 198 asm volatile ("mrc p15, 0, %[cpacr], c1, c0, 2" 199 : [cpacr] "=r" (cpacr) 200 ); 201 202 return cpacr; 203 } 204 205 static inline void write_cpacr(uint32_t cpacr) 206 { 207 asm volatile ("mcr p15, 0, %[cpacr], c1, c0, 2" 208 : : [cpacr] "r" (cpacr) 209 ); 210 } 211 212 static inline void write_ttbr0(uint32_t ttbr0) 213 { 214 asm volatile ("mcr p15, 0, %[ttbr0], c2, c0, 0" 215 : : [ttbr0] "r" (ttbr0) 216 ); 217 } 218 219 static inline void write_ttbr0_64bit(uint64_t ttbr0) 220 { 221 asm volatile ("mcrr p15, 0, %Q[ttbr0], %R[ttbr0], c2" 222 : : [ttbr0] "r" (ttbr0) 223 ); 224 } 225 226 static inline uint32_t read_ttbr0(void) 227 { 228 uint32_t ttbr0; 229 230 asm volatile ("mrc p15, 0, %[ttbr0], c2, c0, 0" 231 : [ttbr0] "=r" (ttbr0) 232 ); 233 234 return ttbr0; 235 } 236 237 static inline uint64_t read_ttbr0_64bit(void) 238 { 239 uint64_t ttbr0; 240 241 asm volatile ("mrrc p15, 0, %Q[ttbr0], %R[ttbr0], c2" 242 : [ttbr0] "=r" (ttbr0) 243 ); 244 245 return ttbr0; 246 } 247 248 static inline void write_ttbr1(uint32_t ttbr1) 249 { 250 asm volatile ("mcr p15, 0, %[ttbr1], c2, c0, 1" 251 : : [ttbr1] "r" (ttbr1) 252 ); 253 } 254 255 static inline void write_ttbr1_64bit(uint64_t ttbr1) 256 { 257 asm volatile ("mcrr p15, 1, %Q[ttbr1], %R[ttbr1], c2" 258 : : [ttbr1] "r" (ttbr1) 259 ); 260 } 261 262 static inline uint32_t read_ttbr1(void) 263 { 264 uint32_t ttbr1; 265 266 asm volatile ("mrc p15, 0, %[ttbr1], c2, c0, 1" 267 : [ttbr1] "=r" (ttbr1) 268 ); 269 270 return ttbr1; 271 } 272 273 274 static inline void write_ttbcr(uint32_t ttbcr) 275 { 276 asm volatile ("mcr p15, 0, %[ttbcr], c2, c0, 2" 277 : : [ttbcr] "r" (ttbcr) 278 ); 279 } 280 281 static inline uint32_t read_ttbcr(void) 282 { 283 uint32_t ttbcr; 284 285 asm volatile ("mrc p15, 0, %[ttbcr], c2, c0, 2" 286 : [ttbcr] "=r" (ttbcr) 287 ); 288 289 return ttbcr; 290 } 291 292 static inline void write_dacr(uint32_t dacr) 293 { 294 asm volatile ("mcr p15, 0, %[dacr], c3, c0, 0" 295 : : [dacr] "r" (dacr) 296 ); 297 } 298 299 static inline uint32_t read_ifar(void) 300 { 301 uint32_t ifar; 302 303 asm volatile ("mrc p15, 0, %[ifar], c6, c0, 2" 304 : [ifar] "=r" (ifar) 305 ); 306 307 return ifar; 308 } 309 310 static inline uint32_t read_dfar(void) 311 { 312 uint32_t dfar; 313 314 asm volatile ("mrc p15, 0, %[dfar], c6, c0, 0" 315 : [dfar] "=r" (dfar) 316 ); 317 318 return dfar; 319 } 320 321 static inline uint32_t read_dfsr(void) 322 { 323 uint32_t dfsr; 324 325 asm volatile ("mrc p15, 0, %[dfsr], c5, c0, 0" 326 : [dfsr] "=r" (dfsr) 327 ); 328 329 return dfsr; 330 } 331 332 static inline uint32_t read_ifsr(void) 333 { 334 uint32_t ifsr; 335 336 asm volatile ("mrc p15, 0, %[ifsr], c5, c0, 1" 337 : [ifsr] "=r" (ifsr) 338 ); 339 340 return ifsr; 341 } 342 343 344 345 static inline void isb(void) 346 { 347 asm volatile ("isb"); 348 } 349 350 static inline void dsb(void) 351 { 352 asm volatile ("dsb"); 353 } 354 355 static inline void write_ats1cpw(uint32_t va) 356 { 357 asm volatile ("mcr p15, 0, %[va], c7, c8, 1" 358 : : [va] "r" (va) 359 ); 360 } 361 362 static inline uint32_t read_par(void) 363 { 364 uint32_t par; 365 366 asm volatile ("mrc p15, 0, %[par], c7, c4, 0" 367 : [par] "=r" (par) 368 ); 369 return par; 370 } 371 372 static inline void write_mair0(uint32_t mair0) 373 { 374 asm volatile ("mcr p15, 0, %[mair0], c10, c2, 0" 375 : : [mair0] "r" (mair0) 376 ); 377 } 378 379 static inline void write_prrr(uint32_t prrr) 380 { 381 /* 382 * Same physical register as MAIR0. 383 * 384 * When an implementation includes the Large Physical Address 385 * Extension, and address translation is using the Long-descriptor 386 * translation table formats, MAIR0 replaces the PRRR 387 */ 388 write_mair0(prrr); 389 } 390 391 static inline void write_mair1(uint32_t mair1) 392 { 393 asm volatile ("mcr p15, 0, %[mair1], c10, c2, 1" 394 : : [mair1] "r" (mair1) 395 ); 396 } 397 398 static inline void write_nmrr(uint32_t nmrr) 399 { 400 /* 401 * Same physical register as MAIR1. 402 * 403 * When an implementation includes the Large Physical Address 404 * Extension, and address translation is using the Long-descriptor 405 * translation table formats, MAIR1 replaces the NMRR 406 */ 407 write_mair1(nmrr); 408 } 409 410 static inline uint32_t read_contextidr(void) 411 { 412 uint32_t contextidr; 413 414 asm volatile ("mrc p15, 0, %[contextidr], c13, c0, 1" 415 : [contextidr] "=r" (contextidr) 416 ); 417 418 return contextidr; 419 } 420 421 static inline void write_contextidr(uint32_t contextidr) 422 { 423 asm volatile ("mcr p15, 0, %[contextidr], c13, c0, 1" 424 : : [contextidr] "r" (contextidr) 425 ); 426 } 427 428 static inline uint32_t read_cpsr(void) 429 { 430 uint32_t cpsr; 431 432 asm volatile ("mrs %[cpsr], cpsr" 433 : [cpsr] "=r" (cpsr) 434 ); 435 return cpsr; 436 } 437 438 static inline void write_cpsr(uint32_t cpsr) 439 { 440 asm volatile ("msr cpsr_fsxc, %[cpsr]" 441 : : [cpsr] "r" (cpsr) 442 ); 443 } 444 445 static inline uint32_t read_spsr(void) 446 { 447 uint32_t spsr; 448 449 asm volatile ("mrs %[spsr], spsr" 450 : [spsr] "=r" (spsr) 451 ); 452 return spsr; 453 } 454 455 static inline uint32_t read_actlr(void) 456 { 457 uint32_t actlr; 458 459 asm volatile ("mrc p15, 0, %[actlr], c1, c0, 1" 460 : [actlr] "=r" (actlr) 461 ); 462 463 return actlr; 464 } 465 466 static inline void write_actlr(uint32_t actlr) 467 { 468 asm volatile ("mcr p15, 0, %[actlr], c1, c0, 1" 469 : : [actlr] "r" (actlr) 470 ); 471 } 472 473 static inline uint32_t read_nsacr(void) 474 { 475 uint32_t nsacr; 476 477 asm volatile ("mrc p15, 0, %[nsacr], c1, c1, 2" 478 : [nsacr] "=r" (nsacr) 479 ); 480 481 return nsacr; 482 } 483 484 static inline void write_nsacr(uint32_t nsacr) 485 { 486 asm volatile ("mcr p15, 0, %[nsacr], c1, c1, 2" 487 : : [nsacr] "r" (nsacr) 488 ); 489 } 490 491 static inline uint64_t read_cntpct(void) 492 { 493 uint64_t val; 494 495 asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (val)); 496 return val; 497 } 498 499 static inline uint32_t read_cntfrq(void) 500 { 501 uint32_t frq; 502 503 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (frq)); 504 return frq; 505 } 506 #endif /*ASM*/ 507 508 #endif /*ARM32_H*/ 509