1 /* 2 * Copyright (c) 2016, Linaro Limited 3 * Copyright (c) 2014, STMicroelectronics International N.V. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef ARM32_H 30 #define ARM32_H 31 32 #ifndef ASM 33 #include <stdint.h> 34 #endif 35 36 #define CPSR_MODE_MASK ARM32_CPSR_MODE_MASK 37 #define CPSR_MODE_USR ARM32_CPSR_MODE_USR 38 #define CPSR_MODE_FIQ ARM32_CPSR_MODE_FIQ 39 #define CPSR_MODE_IRQ ARM32_CPSR_MODE_IRQ 40 #define CPSR_MODE_SVC ARM32_CPSR_MODE_SVC 41 #define CPSR_MODE_MON ARM32_CPSR_MODE_MON 42 #define CPSR_MODE_ABT ARM32_CPSR_MODE_ABT 43 #define CPSR_MODE_UND ARM32_CPSR_MODE_UND 44 #define CPSR_MODE_SYS ARM32_CPSR_MODE_SYS 45 46 #define CPSR_T ARM32_CPSR_T 47 #define CPSR_F_SHIFT ARM32_CPSR_F_SHIFT 48 #define CPSR_F ARM32_CPSR_F 49 #define CPSR_I ARM32_CPSR_I 50 #define CPSR_A ARM32_CPSR_A 51 #define CPSR_FIA ARM32_CPSR_FIA 52 #define CPSR_IT_MASK ARM32_CPSR_IT_MASK 53 #define CPSR_IT_MASK1 ARM32_CPSR_IT_MASK1 54 #define CPSR_IT_MASK2 ARM32_CPSR_IT_MASK2 55 56 #define SCR_NS (1 << 0) 57 #define SCR_IRQ (1 << 1) 58 #define SCR_FIQ (1 << 2) 59 #define SCR_EA (1 << 3) 60 #define SCR_FW (1 << 4) 61 #define SCR_AW (1 << 5) 62 #define SCR_NET (1 << 6) 63 #define SCR_SCD (1 << 7) 64 #define SCR_HCE (1 << 8) 65 #define SCR_SIF (1 << 9) 66 67 #define SCTLR_M (1 << 0) 68 #define SCTLR_A (1 << 1) 69 #define SCTLR_C (1 << 2) 70 #define SCTLR_CP15BEN (1 << 5) 71 #define SCTLR_SW (1 << 10) 72 #define SCTLR_Z (1 << 11) 73 #define SCTLR_I (1 << 12) 74 #define SCTLR_V (1 << 13) 75 #define SCTLR_RR (1 << 14) 76 #define SCTLR_HA (1 << 17) 77 #define SCTLR_WXN (1 << 19) 78 #define SCTLR_UWXN (1 << 20) 79 #define SCTLR_FI (1 << 21) 80 #define SCTLR_VE (1 << 24) 81 #define SCTLR_EE (1 << 25) 82 #define SCTLR_NMFI (1 << 26) 83 #define SCTLR_TRE (1 << 28) 84 #define SCTLR_AFE (1 << 29) 85 #define SCTLR_TE (1 << 30) 86 87 #define ACTLR_SMP (1 << 6) 88 #define ACTLR_DODMBS (1 << 10) 89 #define ACTLR_L2RADIS (1 << 11) 90 #define ACTLR_L1RADIS (1 << 12) 91 #define ACTLR_L1PCTL (1 << 13) 92 #define ACTLR_DDVM (1 << 15) 93 #define ACTLR_DDI (1 << 28) 94 95 #define NSACR_CP10 (1 << 10) 96 #define NSACR_CP11 (1 << 11) 97 #define NSACR_NSD32DIS (1 << 14) 98 #define NSACR_NSASEDIS (1 << 15) 99 #define NSACR_NS_L2ERR (1 << 17) 100 #define NSACR_NS_SMP (1 << 18) 101 102 #define CPACR_ASEDIS (1 << 31) 103 #define CPACR_D32DIS (1 << 30) 104 #define CPACR_CP(co_proc, access) ((access) << ((co_proc) * 2)) 105 #define CPACR_CP_ACCESS_DENIED 0x0 106 #define CPACR_CP_ACCESS_PL1_ONLY 0x1 107 #define CPACR_CP_ACCESS_FULL 0x3 108 109 110 #define DACR_DOMAIN(num, perm) ((perm) << ((num) * 2)) 111 #define DACR_DOMAIN_PERM_NO_ACCESS 0x0 112 #define DACR_DOMAIN_PERM_CLIENT 0x1 113 #define DACR_DOMAIN_PERM_MANAGER 0x3 114 115 #define PAR_F (1 << 0) 116 #define PAR_SS (1 << 1) 117 #define PAR_LPAE (1 << 11) 118 #define PAR_PA_SHIFT 12 119 #define PAR32_PA_MASK ((1 << 20) - 1) 120 #define PAR64_PA_MASK ((1ULL << 28) - 1) 121 122 /* 123 * TTBCR has different register layout if LPAE is enabled or not. 124 * TTBCR.EAE == 0 => LPAE is not enabled 125 * TTBCR.EAE == 1 => LPAE is enabled 126 */ 127 #define TTBCR_EAE (1 << 31) 128 129 /* When TTBCR.EAE == 0 */ 130 #define TTBCR_PD0 (1 << 4) 131 #define TTBCR_PD1 (1 << 5) 132 133 /* When TTBCR.EAE == 1 */ 134 #define TTBCR_T0SZ_SHIFT 0 135 #define TTBCR_EPD0 (1 << 7) 136 #define TTBCR_IRGN0_SHIFT 8 137 #define TTBCR_ORGN0_SHIFT 10 138 #define TTBCR_SH0_SHIFT 12 139 #define TTBCR_T1SZ_SHIFT 16 140 #define TTBCR_A1 (1 << 22) 141 #define TTBCR_EPD1 (1 << 23) 142 #define TTBCR_IRGN1_SHIFT 24 143 #define TTBCR_ORGN1_SHIFT 26 144 #define TTBCR_SH1_SHIFT 28 145 146 /* Normal memory, Inner/Outer Non-cacheable */ 147 #define TTBCR_XRGNX_NC 0x0 148 /* Normal memory, Inner/Outer Write-Back Write-Allocate Cacheable */ 149 #define TTBCR_XRGNX_WB 0x1 150 /* Normal memory, Inner/Outer Write-Through Cacheable */ 151 #define TTBCR_XRGNX_WT 0x2 152 /* Normal memory, Inner/Outer Write-Back no Write-Allocate Cacheable */ 153 #define TTBCR_XRGNX_WBWA 0x3 154 155 /* Non-shareable */ 156 #define TTBCR_SHX_NSH 0x0 157 /* Outer Shareable */ 158 #define TTBCR_SHX_OSH 0x2 159 /* Inner Shareable */ 160 #define TTBCR_SHX_ISH 0x3 161 162 #define TTBR_ASID_MASK 0xff 163 #define TTBR_ASID_SHIFT 48 164 165 166 #define FSR_LPAE (1 << 9) 167 #define FSR_WNR (1 << 11) 168 169 /* Valid if FSR.LPAE is 1 */ 170 #define FSR_STATUS_MASK ((1 << 6) - 1) 171 172 /* Valid if FSR.LPAE is 0 */ 173 #define FSR_FS_MASK ((1 << 10) | ((1 << 4) - 1)) 174 175 #ifndef ASM 176 static inline uint32_t read_mpidr(void) 177 { 178 uint32_t mpidr; 179 180 asm volatile ("mrc p15, 0, %[mpidr], c0, c0, 5" 181 : [mpidr] "=r" (mpidr) 182 ); 183 184 return mpidr; 185 } 186 187 static inline uint32_t read_sctlr(void) 188 { 189 uint32_t sctlr; 190 191 asm volatile ("mrc p15, 0, %[sctlr], c1, c0, 0" 192 : [sctlr] "=r" (sctlr) 193 ); 194 195 return sctlr; 196 } 197 198 static inline void write_sctlr(uint32_t sctlr) 199 { 200 asm volatile ("mcr p15, 0, %[sctlr], c1, c0, 0" 201 : : [sctlr] "r" (sctlr) 202 ); 203 } 204 205 static inline uint32_t read_cpacr(void) 206 { 207 uint32_t cpacr; 208 209 asm volatile ("mrc p15, 0, %[cpacr], c1, c0, 2" 210 : [cpacr] "=r" (cpacr) 211 ); 212 213 return cpacr; 214 } 215 216 static inline void write_cpacr(uint32_t cpacr) 217 { 218 asm volatile ("mcr p15, 0, %[cpacr], c1, c0, 2" 219 : : [cpacr] "r" (cpacr) 220 ); 221 } 222 223 static inline void write_ttbr0(uint32_t ttbr0) 224 { 225 asm volatile ("mcr p15, 0, %[ttbr0], c2, c0, 0" 226 : : [ttbr0] "r" (ttbr0) 227 ); 228 } 229 230 static inline void write_ttbr0_64bit(uint64_t ttbr0) 231 { 232 asm volatile ("mcrr p15, 0, %Q[ttbr0], %R[ttbr0], c2" 233 : : [ttbr0] "r" (ttbr0) 234 ); 235 } 236 237 static inline uint32_t read_ttbr0(void) 238 { 239 uint32_t ttbr0; 240 241 asm volatile ("mrc p15, 0, %[ttbr0], c2, c0, 0" 242 : [ttbr0] "=r" (ttbr0) 243 ); 244 245 return ttbr0; 246 } 247 248 static inline uint64_t read_ttbr0_64bit(void) 249 { 250 uint64_t ttbr0; 251 252 asm volatile ("mrrc p15, 0, %Q[ttbr0], %R[ttbr0], c2" 253 : [ttbr0] "=r" (ttbr0) 254 ); 255 256 return ttbr0; 257 } 258 259 static inline void write_ttbr1(uint32_t ttbr1) 260 { 261 asm volatile ("mcr p15, 0, %[ttbr1], c2, c0, 1" 262 : : [ttbr1] "r" (ttbr1) 263 ); 264 } 265 266 static inline void write_ttbr1_64bit(uint64_t ttbr1) 267 { 268 asm volatile ("mcrr p15, 1, %Q[ttbr1], %R[ttbr1], c2" 269 : : [ttbr1] "r" (ttbr1) 270 ); 271 } 272 273 static inline uint32_t read_ttbr1(void) 274 { 275 uint32_t ttbr1; 276 277 asm volatile ("mrc p15, 0, %[ttbr1], c2, c0, 1" 278 : [ttbr1] "=r" (ttbr1) 279 ); 280 281 return ttbr1; 282 } 283 284 285 static inline void write_ttbcr(uint32_t ttbcr) 286 { 287 asm volatile ("mcr p15, 0, %[ttbcr], c2, c0, 2" 288 : : [ttbcr] "r" (ttbcr) 289 ); 290 } 291 292 static inline uint32_t read_ttbcr(void) 293 { 294 uint32_t ttbcr; 295 296 asm volatile ("mrc p15, 0, %[ttbcr], c2, c0, 2" 297 : [ttbcr] "=r" (ttbcr) 298 ); 299 300 return ttbcr; 301 } 302 303 static inline void write_dacr(uint32_t dacr) 304 { 305 asm volatile ("mcr p15, 0, %[dacr], c3, c0, 0" 306 : : [dacr] "r" (dacr) 307 ); 308 } 309 310 static inline uint32_t read_ifar(void) 311 { 312 uint32_t ifar; 313 314 asm volatile ("mrc p15, 0, %[ifar], c6, c0, 2" 315 : [ifar] "=r" (ifar) 316 ); 317 318 return ifar; 319 } 320 321 static inline uint32_t read_dfar(void) 322 { 323 uint32_t dfar; 324 325 asm volatile ("mrc p15, 0, %[dfar], c6, c0, 0" 326 : [dfar] "=r" (dfar) 327 ); 328 329 return dfar; 330 } 331 332 static inline uint32_t read_dfsr(void) 333 { 334 uint32_t dfsr; 335 336 asm volatile ("mrc p15, 0, %[dfsr], c5, c0, 0" 337 : [dfsr] "=r" (dfsr) 338 ); 339 340 return dfsr; 341 } 342 343 static inline uint32_t read_ifsr(void) 344 { 345 uint32_t ifsr; 346 347 asm volatile ("mrc p15, 0, %[ifsr], c5, c0, 1" 348 : [ifsr] "=r" (ifsr) 349 ); 350 351 return ifsr; 352 } 353 354 static inline void isb(void) 355 { 356 asm volatile ("isb"); 357 } 358 359 static inline void dsb(void) 360 { 361 asm volatile ("dsb"); 362 } 363 364 /* Address translate privileged write translation (current state secure PL1) */ 365 static inline void write_ats1cpw(uint32_t va) 366 { 367 asm volatile ("mcr p15, 0, %0, c7, c8, 1" : : "r" (va)); 368 } 369 370 static inline uint32_t read_par32(void) 371 { 372 uint32_t val; 373 374 asm volatile ("mrc p15, 0, %0, c7, c4, 0" : "=r" (val)); 375 return val; 376 } 377 378 #ifdef CFG_WITH_LPAE 379 static inline uint64_t read_par64(void) 380 { 381 uint64_t val; 382 383 asm volatile ("mrrc p15, 0, %Q0, %R0, c7" : "=r" (val)); 384 return val; 385 } 386 #endif 387 388 static inline void write_mair0(uint32_t mair0) 389 { 390 asm volatile ("mcr p15, 0, %[mair0], c10, c2, 0" 391 : : [mair0] "r" (mair0) 392 ); 393 } 394 395 static inline void write_prrr(uint32_t prrr) 396 { 397 /* 398 * Same physical register as MAIR0. 399 * 400 * When an implementation includes the Large Physical Address 401 * Extension, and address translation is using the Long-descriptor 402 * translation table formats, MAIR0 replaces the PRRR 403 */ 404 write_mair0(prrr); 405 } 406 407 static inline void write_mair1(uint32_t mair1) 408 { 409 asm volatile ("mcr p15, 0, %[mair1], c10, c2, 1" 410 : : [mair1] "r" (mair1) 411 ); 412 } 413 414 static inline void write_nmrr(uint32_t nmrr) 415 { 416 /* 417 * Same physical register as MAIR1. 418 * 419 * When an implementation includes the Large Physical Address 420 * Extension, and address translation is using the Long-descriptor 421 * translation table formats, MAIR1 replaces the NMRR 422 */ 423 write_mair1(nmrr); 424 } 425 426 static inline uint32_t read_contextidr(void) 427 { 428 uint32_t contextidr; 429 430 asm volatile ("mrc p15, 0, %[contextidr], c13, c0, 1" 431 : [contextidr] "=r" (contextidr) 432 ); 433 434 return contextidr; 435 } 436 437 static inline void write_contextidr(uint32_t contextidr) 438 { 439 asm volatile ("mcr p15, 0, %[contextidr], c13, c0, 1" 440 : : [contextidr] "r" (contextidr) 441 ); 442 } 443 444 static inline uint32_t read_cpsr(void) 445 { 446 uint32_t cpsr; 447 448 asm volatile ("mrs %[cpsr], cpsr" 449 : [cpsr] "=r" (cpsr) 450 ); 451 return cpsr; 452 } 453 454 static inline void write_cpsr(uint32_t cpsr) 455 { 456 asm volatile ("msr cpsr_fsxc, %[cpsr]" 457 : : [cpsr] "r" (cpsr) 458 ); 459 } 460 461 static inline uint32_t read_spsr(void) 462 { 463 uint32_t spsr; 464 465 asm volatile ("mrs %[spsr], spsr" 466 : [spsr] "=r" (spsr) 467 ); 468 return spsr; 469 } 470 471 static inline uint32_t read_actlr(void) 472 { 473 uint32_t actlr; 474 475 asm volatile ("mrc p15, 0, %[actlr], c1, c0, 1" 476 : [actlr] "=r" (actlr) 477 ); 478 479 return actlr; 480 } 481 482 static inline void write_actlr(uint32_t actlr) 483 { 484 asm volatile ("mcr p15, 0, %[actlr], c1, c0, 1" 485 : : [actlr] "r" (actlr) 486 ); 487 } 488 489 static inline uint32_t read_nsacr(void) 490 { 491 uint32_t nsacr; 492 493 asm volatile ("mrc p15, 0, %[nsacr], c1, c1, 2" 494 : [nsacr] "=r" (nsacr) 495 ); 496 497 return nsacr; 498 } 499 500 static inline void write_nsacr(uint32_t nsacr) 501 { 502 asm volatile ("mcr p15, 0, %[nsacr], c1, c1, 2" 503 : : [nsacr] "r" (nsacr) 504 ); 505 } 506 507 static inline uint64_t read_cntpct(void) 508 { 509 uint64_t val; 510 511 asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (val)); 512 return val; 513 } 514 515 static inline uint32_t read_cntfrq(void) 516 { 517 uint32_t frq; 518 519 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (frq)); 520 return frq; 521 } 522 #endif /*ASM*/ 523 524 #endif /*ARM32_H*/ 525