1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2016, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 */ 6 7 #ifndef ARM32_H 8 #define ARM32_H 9 10 #include <sys/cdefs.h> 11 #include <stdint.h> 12 #include <util.h> 13 14 #define CPSR_MODE_MASK ARM32_CPSR_MODE_MASK 15 #define CPSR_MODE_USR ARM32_CPSR_MODE_USR 16 #define CPSR_MODE_FIQ ARM32_CPSR_MODE_FIQ 17 #define CPSR_MODE_IRQ ARM32_CPSR_MODE_IRQ 18 #define CPSR_MODE_SVC ARM32_CPSR_MODE_SVC 19 #define CPSR_MODE_MON ARM32_CPSR_MODE_MON 20 #define CPSR_MODE_ABT ARM32_CPSR_MODE_ABT 21 #define CPSR_MODE_UND ARM32_CPSR_MODE_UND 22 #define CPSR_MODE_SYS ARM32_CPSR_MODE_SYS 23 24 #define CPSR_T ARM32_CPSR_T 25 #define CPSR_F_SHIFT ARM32_CPSR_F_SHIFT 26 #define CPSR_F ARM32_CPSR_F 27 #define CPSR_I ARM32_CPSR_I 28 #define CPSR_A ARM32_CPSR_A 29 #define CPSR_FIA ARM32_CPSR_FIA 30 #define CPSR_IT_MASK ARM32_CPSR_IT_MASK 31 #define CPSR_IT_MASK1 ARM32_CPSR_IT_MASK1 32 #define CPSR_IT_MASK2 ARM32_CPSR_IT_MASK2 33 34 #define PMCR_DP BIT32(5) 35 36 #define SCR_NS BIT32(0) 37 #define SCR_IRQ BIT32(1) 38 #define SCR_FIQ BIT32(2) 39 #define SCR_EA BIT32(3) 40 #define SCR_FW BIT32(4) 41 #define SCR_AW BIT32(5) 42 #define SCR_NET BIT32(6) 43 #define SCR_SCD BIT32(7) 44 #define SCR_HCE BIT32(8) 45 #define SCR_SIF BIT32(9) 46 47 #define SCTLR_M BIT32(0) 48 #define SCTLR_A BIT32(1) 49 #define SCTLR_C BIT32(2) 50 #define SCTLR_CP15BEN BIT32(5) 51 #define SCTLR_SW BIT32(10) 52 #define SCTLR_Z BIT32(11) 53 #define SCTLR_I BIT32(12) 54 #define SCTLR_V BIT32(13) 55 #define SCTLR_RR BIT32(14) 56 #define SCTLR_HA BIT32(17) 57 #define SCTLR_WXN BIT32(19) 58 #define SCTLR_UWXN BIT32(20) 59 #define SCTLR_FI BIT32(21) 60 #define SCTLR_SPAN BIT32(23) 61 #define SCTLR_VE BIT32(24) 62 #define SCTLR_EE BIT32(25) 63 #define SCTLR_NMFI BIT32(26) 64 #define SCTLR_TRE BIT32(28) 65 #define SCTLR_AFE BIT32(29) 66 #define SCTLR_TE BIT32(30) 67 68 /* Only valid for Cortex-A15 */ 69 #define ACTLR_CA15_ENABLE_INVALIDATE_BTB BIT(0) 70 /* Only valid for Cortex-A8 */ 71 #define ACTLR_CA8_ENABLE_INVALIDATE_BTB BIT(6) 72 /* Only valid for Cortex-A9 */ 73 #define ACTLR_CA9_WFLZ BIT(3) 74 75 #define ACTLR_SMP BIT32(6) 76 77 #define NSACR_CP10 BIT32(10) 78 #define NSACR_CP11 BIT32(11) 79 #define NSACR_NSD32DIS BIT32(14) 80 #define NSACR_NSASEDIS BIT32(15) 81 #define NSACR_NS_L2ERR BIT32(17) 82 #define NSACR_NS_SMP BIT32(18) 83 84 #define CPACR_ASEDIS BIT32(31) 85 #define CPACR_D32DIS BIT32(30) 86 #define CPACR_CP(co_proc, access) SHIFT_U32((access), ((co_proc) * 2)) 87 #define CPACR_CP_ACCESS_DENIED 0x0 88 #define CPACR_CP_ACCESS_PL1_ONLY 0x1 89 #define CPACR_CP_ACCESS_FULL 0x3 90 91 92 #define DACR_DOMAIN(num, perm) SHIFT_U32((perm), ((num) * 2)) 93 #define DACR_DOMAIN_PERM_NO_ACCESS 0x0 94 #define DACR_DOMAIN_PERM_CLIENT 0x1 95 #define DACR_DOMAIN_PERM_MANAGER 0x3 96 97 #define PAR_F BIT32(0) 98 #define PAR_SS BIT32(1) 99 #define PAR_LPAE BIT32(11) 100 #define PAR_PA_SHIFT 12 101 #define PAR32_PA_MASK (BIT32(20) - 1) 102 #define PAR64_PA_MASK (BIT64(28) - 1) 103 104 /* 105 * TTBCR has different register layout if LPAE is enabled or not. 106 * TTBCR.EAE == 0 => LPAE is not enabled 107 * TTBCR.EAE == 1 => LPAE is enabled 108 */ 109 #define TTBCR_EAE BIT32(31) 110 111 /* When TTBCR.EAE == 0 */ 112 #define TTBCR_PD0 BIT32(4) 113 #define TTBCR_PD1 BIT32(5) 114 115 /* When TTBCR.EAE == 1 */ 116 #define TTBCR_T0SZ_SHIFT 0 117 #define TTBCR_EPD0 BIT32(7) 118 #define TTBCR_IRGN0_SHIFT 8 119 #define TTBCR_ORGN0_SHIFT 10 120 #define TTBCR_SH0_SHIFT 12 121 #define TTBCR_T1SZ_SHIFT 16 122 #define TTBCR_A1 BIT32(22) 123 #define TTBCR_EPD1 BIT32(23) 124 #define TTBCR_IRGN1_SHIFT 24 125 #define TTBCR_ORGN1_SHIFT 26 126 #define TTBCR_SH1_SHIFT 28 127 128 /* Normal memory, Inner/Outer Non-cacheable */ 129 #define TTBCR_XRGNX_NC 0x0 130 /* Normal memory, Inner/Outer Write-Back Write-Allocate Cacheable */ 131 #define TTBCR_XRGNX_WB 0x1 132 /* Normal memory, Inner/Outer Write-Through Cacheable */ 133 #define TTBCR_XRGNX_WT 0x2 134 /* Normal memory, Inner/Outer Write-Back no Write-Allocate Cacheable */ 135 #define TTBCR_XRGNX_WBWA 0x3 136 137 /* Non-shareable */ 138 #define TTBCR_SHX_NSH 0x0 139 /* Outer Shareable */ 140 #define TTBCR_SHX_OSH 0x2 141 /* Inner Shareable */ 142 #define TTBCR_SHX_ISH 0x3 143 144 #define TTBR_ASID_MASK 0xff 145 #define TTBR_ASID_SHIFT 48 146 147 #define TLBI_MVA_SHIFT 12 148 #define TLBI_ASID_MASK 0xff 149 150 #define FSR_LPAE BIT32(9) 151 #define FSR_WNR BIT32(11) 152 153 /* Valid if FSR.LPAE is 1 */ 154 #define FSR_STATUS_MASK (BIT32(6) - 1) 155 156 /* Valid if FSR.LPAE is 0 */ 157 #define FSR_FS_MASK (BIT32(10) | (BIT32(4) - 1)) 158 159 /* ID_PFR1 bit fields */ 160 #define IDPFR1_VIRT_SHIFT 12 161 #define IDPFR1_VIRT_MASK (0xF << IDPFR1_VIRT_SHIFT) 162 #define IDPFR1_GENTIMER_SHIFT 16 163 #define IDPFR1_GENTIMER_MASK (0xF << IDPFR1_GENTIMER_SHIFT) 164 165 #ifndef __ASSEMBLER__ 166 #include <generated/arm32_sysreg.h> 167 #ifdef CFG_ARM_GICV3 168 #include <generated/arm32_gicv3_sysreg.h> 169 #endif 170 171 static inline void isb(void) 172 { 173 asm volatile ("isb"); 174 } 175 176 static inline void dsb(void) 177 { 178 asm volatile ("dsb"); 179 } 180 181 static inline void dsb_ish(void) 182 { 183 asm volatile ("dsb ish"); 184 } 185 186 static inline void dsb_ishst(void) 187 { 188 asm volatile ("dsb ishst"); 189 } 190 191 static inline void dmb(void) 192 { 193 asm volatile ("dmb"); 194 } 195 196 static inline void sev(void) 197 { 198 asm volatile ("sev"); 199 } 200 201 static inline void wfe(void) 202 { 203 asm volatile ("wfe"); 204 } 205 206 static inline uint32_t read_cpsr(void) 207 { 208 uint32_t cpsr; 209 210 asm volatile ("mrs %[cpsr], cpsr" 211 : [cpsr] "=r" (cpsr) 212 ); 213 return cpsr; 214 } 215 216 static inline void write_cpsr(uint32_t cpsr) 217 { 218 asm volatile ("msr cpsr_fsxc, %[cpsr]" 219 : : [cpsr] "r" (cpsr) 220 ); 221 } 222 223 static inline uint32_t read_spsr(void) 224 { 225 uint32_t spsr; 226 227 asm volatile ("mrs %[spsr], spsr" 228 : [spsr] "=r" (spsr) 229 ); 230 return spsr; 231 } 232 233 static inline void wfi(void) 234 { 235 asm volatile("wfi"); 236 } 237 238 static __always_inline uint32_t read_pc(void) 239 { 240 uint32_t val; 241 242 asm volatile ("adr %0, ." : "=r" (val)); 243 return val; 244 } 245 246 static __always_inline uint32_t read_sp(void) 247 { 248 uint32_t val; 249 250 asm volatile ("mov %0, sp" : "=r" (val)); 251 return val; 252 } 253 254 static __always_inline uint32_t read_lr(void) 255 { 256 uint32_t val; 257 258 asm volatile ("mov %0, lr" : "=r" (val)); 259 return val; 260 } 261 262 static __always_inline uint32_t read_fp(void) 263 { 264 uint32_t val; 265 266 asm volatile ("mov %0, fp" : "=r" (val)); 267 return val; 268 } 269 270 static __always_inline uint32_t read_r7(void) 271 { 272 uint32_t val; 273 274 asm volatile ("mov %0, r7" : "=r" (val)); 275 return val; 276 } 277 278 #endif /*__ASSEMBLER__*/ 279 280 #endif /*ARM32_H*/ 281