1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2016, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 */ 6 7 #ifndef ARM32_H 8 #define ARM32_H 9 10 #include <sys/cdefs.h> 11 #include <stdint.h> 12 #include <util.h> 13 14 #define CPSR_MODE_MASK ARM32_CPSR_MODE_MASK 15 #define CPSR_MODE_USR ARM32_CPSR_MODE_USR 16 #define CPSR_MODE_FIQ ARM32_CPSR_MODE_FIQ 17 #define CPSR_MODE_IRQ ARM32_CPSR_MODE_IRQ 18 #define CPSR_MODE_SVC ARM32_CPSR_MODE_SVC 19 #define CPSR_MODE_MON ARM32_CPSR_MODE_MON 20 #define CPSR_MODE_ABT ARM32_CPSR_MODE_ABT 21 #define CPSR_MODE_UND ARM32_CPSR_MODE_UND 22 #define CPSR_MODE_SYS ARM32_CPSR_MODE_SYS 23 24 #define CPSR_T ARM32_CPSR_T 25 #define CPSR_F_SHIFT ARM32_CPSR_F_SHIFT 26 #define CPSR_F ARM32_CPSR_F 27 #define CPSR_I ARM32_CPSR_I 28 #define CPSR_A ARM32_CPSR_A 29 #define CPSR_FIA ARM32_CPSR_FIA 30 #define CPSR_IT_MASK ARM32_CPSR_IT_MASK 31 #define CPSR_IT_MASK1 ARM32_CPSR_IT_MASK1 32 #define CPSR_IT_MASK2 ARM32_CPSR_IT_MASK2 33 34 #define PMCR_DP BIT32(5) 35 36 #define SCR_NS BIT32(0) 37 #define SCR_IRQ BIT32(1) 38 #define SCR_FIQ BIT32(2) 39 #define SCR_EA BIT32(3) 40 #define SCR_FW BIT32(4) 41 #define SCR_AW BIT32(5) 42 #define SCR_NET BIT32(6) 43 #define SCR_SCD BIT32(7) 44 #define SCR_HCE BIT32(8) 45 #define SCR_SIF BIT32(9) 46 47 #define SCTLR_M BIT32(0) 48 #define SCTLR_A BIT32(1) 49 #define SCTLR_C BIT32(2) 50 #define SCTLR_CP15BEN BIT32(5) 51 #define SCTLR_SW BIT32(10) 52 #define SCTLR_Z BIT32(11) 53 #define SCTLR_I BIT32(12) 54 #define SCTLR_V BIT32(13) 55 #define SCTLR_RR BIT32(14) 56 #define SCTLR_HA BIT32(17) 57 #define SCTLR_WXN BIT32(19) 58 #define SCTLR_UWXN BIT32(20) 59 #define SCTLR_FI BIT32(21) 60 #define SCTLR_VE BIT32(24) 61 #define SCTLR_EE BIT32(25) 62 #define SCTLR_NMFI BIT32(26) 63 #define SCTLR_TRE BIT32(28) 64 #define SCTLR_AFE BIT32(29) 65 #define SCTLR_TE BIT32(30) 66 67 /* Only valid for Cortex-A15 */ 68 #define ACTLR_CA15_ENABLE_INVALIDATE_BTB BIT(0) 69 /* Only valid for Cortex-A8 */ 70 #define ACTLR_CA8_ENABLE_INVALIDATE_BTB BIT(6) 71 /* Only valid for Cortex-A9 */ 72 #define ACTLR_CA9_WFLZ BIT(3) 73 74 #define ACTLR_SMP BIT32(6) 75 76 #define NSACR_CP10 BIT32(10) 77 #define NSACR_CP11 BIT32(11) 78 #define NSACR_NSD32DIS BIT32(14) 79 #define NSACR_NSASEDIS BIT32(15) 80 #define NSACR_NS_L2ERR BIT32(17) 81 #define NSACR_NS_SMP BIT32(18) 82 83 #define CPACR_ASEDIS BIT32(31) 84 #define CPACR_D32DIS BIT32(30) 85 #define CPACR_CP(co_proc, access) SHIFT_U32((access), ((co_proc) * 2)) 86 #define CPACR_CP_ACCESS_DENIED 0x0 87 #define CPACR_CP_ACCESS_PL1_ONLY 0x1 88 #define CPACR_CP_ACCESS_FULL 0x3 89 90 91 #define DACR_DOMAIN(num, perm) SHIFT_U32((perm), ((num) * 2)) 92 #define DACR_DOMAIN_PERM_NO_ACCESS 0x0 93 #define DACR_DOMAIN_PERM_CLIENT 0x1 94 #define DACR_DOMAIN_PERM_MANAGER 0x3 95 96 #define PAR_F BIT32(0) 97 #define PAR_SS BIT32(1) 98 #define PAR_LPAE BIT32(11) 99 #define PAR_PA_SHIFT 12 100 #define PAR32_PA_MASK (BIT32(20) - 1) 101 #define PAR64_PA_MASK (BIT64(28) - 1) 102 103 /* 104 * TTBCR has different register layout if LPAE is enabled or not. 105 * TTBCR.EAE == 0 => LPAE is not enabled 106 * TTBCR.EAE == 1 => LPAE is enabled 107 */ 108 #define TTBCR_EAE BIT32(31) 109 110 /* When TTBCR.EAE == 0 */ 111 #define TTBCR_PD0 BIT32(4) 112 #define TTBCR_PD1 BIT32(5) 113 114 /* When TTBCR.EAE == 1 */ 115 #define TTBCR_T0SZ_SHIFT 0 116 #define TTBCR_EPD0 BIT32(7) 117 #define TTBCR_IRGN0_SHIFT 8 118 #define TTBCR_ORGN0_SHIFT 10 119 #define TTBCR_SH0_SHIFT 12 120 #define TTBCR_T1SZ_SHIFT 16 121 #define TTBCR_A1 BIT32(22) 122 #define TTBCR_EPD1 BIT32(23) 123 #define TTBCR_IRGN1_SHIFT 24 124 #define TTBCR_ORGN1_SHIFT 26 125 #define TTBCR_SH1_SHIFT 28 126 127 /* Normal memory, Inner/Outer Non-cacheable */ 128 #define TTBCR_XRGNX_NC 0x0 129 /* Normal memory, Inner/Outer Write-Back Write-Allocate Cacheable */ 130 #define TTBCR_XRGNX_WB 0x1 131 /* Normal memory, Inner/Outer Write-Through Cacheable */ 132 #define TTBCR_XRGNX_WT 0x2 133 /* Normal memory, Inner/Outer Write-Back no Write-Allocate Cacheable */ 134 #define TTBCR_XRGNX_WBWA 0x3 135 136 /* Non-shareable */ 137 #define TTBCR_SHX_NSH 0x0 138 /* Outer Shareable */ 139 #define TTBCR_SHX_OSH 0x2 140 /* Inner Shareable */ 141 #define TTBCR_SHX_ISH 0x3 142 143 #define TTBR_ASID_MASK 0xff 144 #define TTBR_ASID_SHIFT 48 145 146 147 #define FSR_LPAE BIT32(9) 148 #define FSR_WNR BIT32(11) 149 150 /* Valid if FSR.LPAE is 1 */ 151 #define FSR_STATUS_MASK (BIT32(6) - 1) 152 153 /* Valid if FSR.LPAE is 0 */ 154 #define FSR_FS_MASK (BIT32(10) | (BIT32(4) - 1)) 155 156 /* ID_PFR1 bit fields */ 157 #define IDPFR1_VIRT_SHIFT 12 158 #define IDPFR1_VIRT_MASK (0xF << IDPFR1_VIRT_SHIFT) 159 #define IDPFR1_GENTIMER_SHIFT 16 160 #define IDPFR1_GENTIMER_MASK (0xF << IDPFR1_GENTIMER_SHIFT) 161 162 #ifndef ASM 163 #include <generated/arm32_sysreg.h> 164 165 static inline void isb(void) 166 { 167 asm volatile ("isb"); 168 } 169 170 static inline void dsb(void) 171 { 172 asm volatile ("dsb"); 173 } 174 175 static inline void dsb_ish(void) 176 { 177 asm volatile ("dsb ish"); 178 } 179 180 static inline void dsb_ishst(void) 181 { 182 asm volatile ("dsb ishst"); 183 } 184 185 static inline void dmb(void) 186 { 187 asm volatile ("dmb"); 188 } 189 190 static inline void sev(void) 191 { 192 asm volatile ("sev"); 193 } 194 195 static inline void wfe(void) 196 { 197 asm volatile ("wfe"); 198 } 199 200 static inline uint32_t read_cpsr(void) 201 { 202 uint32_t cpsr; 203 204 asm volatile ("mrs %[cpsr], cpsr" 205 : [cpsr] "=r" (cpsr) 206 ); 207 return cpsr; 208 } 209 210 static inline void write_cpsr(uint32_t cpsr) 211 { 212 asm volatile ("msr cpsr_fsxc, %[cpsr]" 213 : : [cpsr] "r" (cpsr) 214 ); 215 } 216 217 static inline uint32_t read_spsr(void) 218 { 219 uint32_t spsr; 220 221 asm volatile ("mrs %[spsr], spsr" 222 : [spsr] "=r" (spsr) 223 ); 224 return spsr; 225 } 226 227 static inline void wfi(void) 228 { 229 asm volatile("wfi"); 230 } 231 232 static __always_inline uint32_t read_pc(void) 233 { 234 uint32_t val; 235 236 asm volatile ("adr %0, ." : "=r" (val)); 237 return val; 238 } 239 240 static __always_inline uint32_t read_sp(void) 241 { 242 uint32_t val; 243 244 asm volatile ("mov %0, sp" : "=r" (val)); 245 return val; 246 } 247 248 static __always_inline uint32_t read_lr(void) 249 { 250 uint32_t val; 251 252 asm volatile ("mov %0, lr" : "=r" (val)); 253 return val; 254 } 255 256 static __always_inline uint32_t read_fp(void) 257 { 258 uint32_t val; 259 260 asm volatile ("mov %0, fp" : "=r" (val)); 261 return val; 262 } 263 264 static __always_inline uint32_t read_r7(void) 265 { 266 uint32_t val; 267 268 asm volatile ("mov %0, r7" : "=r" (val)); 269 return val; 270 } 271 272 /* Register read/write functions for GICC registers by using system interface */ 273 static inline uint32_t read_icc_ctlr(void) 274 { 275 uint32_t v; 276 277 asm volatile ("mrc p15,0,%0,c12,c12,4" : "=r" (v)); 278 return v; 279 } 280 281 static inline void write_icc_ctlr(uint32_t v) 282 { 283 asm volatile ("mcr p15,0,%0,c12,c12,4" : : "r" (v)); 284 } 285 286 static inline void write_icc_pmr(uint32_t v) 287 { 288 asm volatile ("mcr p15,0,%0,c4,c6,0" : : "r" (v)); 289 } 290 291 static inline uint32_t read_icc_iar0(void) 292 { 293 uint32_t v; 294 295 asm volatile ("mrc p15,0,%0,c12,c8,0" : "=r" (v)); 296 return v; 297 } 298 299 static inline void write_icc_eoir0(uint32_t v) 300 { 301 asm volatile ("mcr p15,0,%0,c12,c8,1" : : "r" (v)); 302 } 303 304 305 #endif /*ASM*/ 306 307 #endif /*ARM32_H*/ 308