1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 * Copyright (c) 2019-2023, Arm Limited. All rights reserved. 5 */ 6 #ifndef __ARM_H 7 #define __ARM_H 8 9 #include <stdbool.h> 10 #include <stdint.h> 11 #include <util.h> 12 13 /* MIDR definitions */ 14 #define MIDR_PRIMARY_PART_NUM_SHIFT U(4) 15 #define MIDR_PRIMARY_PART_NUM_WIDTH U(12) 16 #define MIDR_PRIMARY_PART_NUM_MASK (BIT(MIDR_PRIMARY_PART_NUM_WIDTH) - 1) 17 18 #define MIDR_IMPLEMENTER_SHIFT U(24) 19 #define MIDR_IMPLEMENTER_WIDTH U(8) 20 #define MIDR_IMPLEMENTER_MASK (BIT(MIDR_IMPLEMENTER_WIDTH) - 1) 21 #define MIDR_IMPLEMENTER_ARM U(0x41) 22 23 #define MIDR_VARIANT_SHIFT U(20) 24 #define MIDR_VARIANT_WIDTH U(4) 25 #define MIDR_VARIANT_MASK (BIT(MIDR_VARIANT_WIDTH) - 1) 26 27 #define MIDR_REVISION_SHIFT U(0) 28 #define MIDR_REVISION_WIDTH U(4) 29 #define MIDR_REVISION_MASK (BIT(MIDR_REVISION_WIDTH) - 1) 30 31 #define CORTEX_A5_PART_NUM U(0xC05) 32 #define CORTEX_A7_PART_NUM U(0xC07) 33 #define CORTEX_A8_PART_NUM U(0xC08) 34 #define CORTEX_A9_PART_NUM U(0xC09) 35 #define CORTEX_A15_PART_NUM U(0xC0F) 36 #define CORTEX_A17_PART_NUM U(0xC0E) 37 #define CORTEX_A57_PART_NUM U(0xD07) 38 #define CORTEX_A72_PART_NUM U(0xD08) 39 #define CORTEX_A73_PART_NUM U(0xD09) 40 #define CORTEX_A75_PART_NUM U(0xD0A) 41 #define CORTEX_A65_PART_NUM U(0xD06) 42 #define CORTEX_A65AE_PART_NUM U(0xD43) 43 #define CORTEX_A76_PART_NUM U(0xD0B) 44 #define CORTEX_A76AE_PART_NUM U(0xD0E) 45 #define CORTEX_A77_PART_NUM U(0xD0D) 46 #define CORTEX_A78_PART_NUM U(0xD41) 47 #define CORTEX_A78AE_PART_NUM U(0xD42) 48 #define CORTEX_A78C_PART_NUM U(0xD4B) 49 #define CORTEX_A710_PART_NUM U(0xD47) 50 #define CORTEX_X1_PART_NUM U(0xD44) 51 #define CORTEX_X2_PART_NUM U(0xD48) 52 #define NEOVERSE_E1_PART_NUM U(0xD4A) 53 #define NEOVERSE_N1_PART_NUM U(0xD0C) 54 #define NEOVERSE_N2_PART_NUM U(0xD49) 55 #define NEOVERSE_V1_PART_NUM U(0xD40) 56 57 /* MPIDR definitions */ 58 #define MPIDR_AFFINITY_BITS U(8) 59 #define MPIDR_AFFLVL_MASK ULL(0xff) 60 #define MPIDR_AFF0_SHIFT U(0) 61 #define MPIDR_AFF0_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT) 62 #define MPIDR_AFF1_SHIFT U(8) 63 #define MPIDR_AFF1_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) 64 #define MPIDR_AFF2_SHIFT U(16) 65 #define MPIDR_AFF2_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) 66 #define MPIDR_AFF3_SHIFT U(32) 67 #define MPIDR_AFF3_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) 68 69 #define MPIDR_MT_SHIFT U(24) 70 #define MPIDR_MT_MASK BIT(MPIDR_MT_SHIFT) 71 72 #define MPIDR_CPU_MASK MPIDR_AFF0_MASK 73 #define MPIDR_CLUSTER_SHIFT MPIDR_AFF1_SHIFT 74 #define MPIDR_CLUSTER_MASK MPIDR_AFF1_MASK 75 76 #define MPIDR_AARCH32_AFF_MASK (MPIDR_AFF0_MASK | MPIDR_AFF1_MASK | \ 77 MPIDR_AFF2_MASK) 78 79 /* MPIDR definitions for VCPU */ 80 #define MPIDR_VCPU_MASK ULL(0xffffff) 81 82 /* ID_ISAR5 Cryptography Extension masks */ 83 #define ID_ISAR5_AES GENMASK_32(7, 4) 84 #define ID_ISAR5_SHA1 GENMASK_32(11, 8) 85 #define ID_ISAR5_SHA2 GENMASK_32(15, 12) 86 #define ID_ISAR5_CRC32 GENMASK_32(19, 16) 87 88 /* CLIDR definitions */ 89 #define CLIDR_LOUIS_SHIFT U(21) 90 #define CLIDR_LOC_SHIFT U(24) 91 #define CLIDR_FIELD_WIDTH U(3) 92 93 /* CSSELR definitions */ 94 #define CSSELR_LEVEL_SHIFT U(1) 95 96 /* CTR definitions */ 97 #define CTR_CWG_SHIFT U(24) 98 #define CTR_CWG_MASK U(0xf) 99 #define CTR_ERG_SHIFT U(20) 100 #define CTR_ERG_MASK U(0xf) 101 #define CTR_DMINLINE_SHIFT U(16) 102 #define CTR_DMINLINE_WIDTH U(4) 103 #define CTR_DMINLINE_MASK (BIT(4) - 1) 104 #define CTR_L1IP_SHIFT U(14) 105 #define CTR_L1IP_MASK U(0x3) 106 #define CTR_IMINLINE_SHIFT U(0) 107 #define CTR_IMINLINE_MASK U(0xf) 108 #define CTR_WORD_SIZE U(4) 109 110 #define ARM32_CPSR_MODE_MASK U(0x1f) 111 #define ARM32_CPSR_MODE_USR U(0x10) 112 #define ARM32_CPSR_MODE_FIQ U(0x11) 113 #define ARM32_CPSR_MODE_IRQ U(0x12) 114 #define ARM32_CPSR_MODE_SVC U(0x13) 115 #define ARM32_CPSR_MODE_MON U(0x16) 116 #define ARM32_CPSR_MODE_ABT U(0x17) 117 #define ARM32_CPSR_MODE_UND U(0x1b) 118 #define ARM32_CPSR_MODE_SYS U(0x1f) 119 120 #define ARM32_CPSR_T BIT(5) 121 #define ARM32_CPSR_F_SHIFT U(6) 122 #define ARM32_CPSR_F BIT(6) 123 #define ARM32_CPSR_I BIT(7) 124 #define ARM32_CPSR_A BIT(8) 125 #define ARM32_CPSR_E BIT(9) 126 #define ARM32_CPSR_FIA (ARM32_CPSR_F | ARM32_CPSR_I | ARM32_CPSR_A) 127 #define ARM32_CPSR_IT_MASK (ARM32_CPSR_IT_MASK1 | ARM32_CPSR_IT_MASK2) 128 #define ARM32_CPSR_IT_MASK1 U(0x06000000) 129 #define ARM32_CPSR_IT_MASK2 U(0x0000fc00) 130 131 /* ARM Generic timer definitions */ 132 #define CNTKCTL_PL0PCTEN BIT(0) /* physical counter el0 access enable */ 133 #define CNTKCTL_PL0VCTEN BIT(1) /* virtual counter el0 access enable */ 134 135 #ifdef ARM32 136 #include <arm32.h> 137 #endif 138 139 #ifdef ARM64 140 #include <arm64.h> 141 #endif 142 143 #ifndef __ASSEMBLER__ 144 static inline __noprof uint64_t barrier_read_counter_timer(void) 145 { 146 isb(); 147 #ifdef CFG_CORE_SEL2_SPMC 148 return read_cntvct(); 149 #else 150 return read_cntpct(); 151 #endif 152 } 153 154 static inline bool feat_bti_is_implemented(void) 155 { 156 #ifdef ARM32 157 return false; 158 #else 159 return ((read_id_aa64pfr1_el1() & ID_AA64PFR1_EL1_BT_MASK) == 160 FEAT_BTI_IMPLEMENTED); 161 #endif 162 } 163 164 static inline unsigned int feat_mte_implemented(void) 165 { 166 #ifdef ARM32 167 return 0; 168 #else 169 return (read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_MTE_SHIFT) & 170 ID_AA64PFR1_EL1_MTE_MASK; 171 #endif 172 } 173 174 static inline unsigned int feat_pan_implemented(void) 175 { 176 #ifdef ARM32 177 return 0; 178 #else 179 return (read_id_aa64mmfr1_el1() >> ID_AA64MMFR1_EL1_PAN_SHIFT) & 180 ID_AA64MMFR1_EL1_PAN_MASK; 181 #endif 182 } 183 184 static inline bool feat_crc32_implemented(void) 185 { 186 #ifdef ARM32 187 return read_id_isar5() & ID_ISAR5_CRC32; 188 #else 189 return read_id_aa64isar0_el1() & ID_AA64ISAR0_CRC32; 190 #endif 191 } 192 193 static inline bool feat_aes_implemented(void) 194 { 195 #ifdef ARM32 196 return read_id_isar5() & ID_ISAR5_AES; 197 #else 198 return read_id_aa64isar0_el1() & ID_AA64ISAR0_AES; 199 #endif 200 } 201 202 static inline bool feat_sha1_implemented(void) 203 { 204 #ifdef ARM32 205 return read_id_isar5() & ID_ISAR5_SHA1; 206 #else 207 return read_id_aa64isar0_el1() & ID_AA64ISAR0_SHA1; 208 #endif 209 } 210 211 static inline bool feat_sha256_implemented(void) 212 { 213 #ifdef ARM32 214 return read_id_isar5() & ID_ISAR5_SHA2; 215 #else 216 return read_id_aa64isar0_el1() & ID_AA64ISAR0_SHA2; 217 #endif 218 } 219 220 static inline bool feat_sha512_implemented(void) 221 { 222 #ifdef ARM32 223 return false; 224 #else 225 return ((read_id_aa64isar0_el1() & ID_AA64ISAR0_SHA2) >> 226 ID_AA64ISAR0_SHA2_SHIFT) == ID_AA64ISAR0_SHA2_FEAT_SHA512; 227 #endif 228 } 229 230 static inline bool feat_sha3_implemented(void) 231 { 232 #ifdef ARM32 233 return false; 234 #else 235 return read_id_aa64isar0_el1() & ID_AA64ISAR0_SHA3; 236 #endif 237 } 238 239 static inline bool feat_sm3_implemented(void) 240 { 241 #ifdef ARM32 242 return false; 243 #else 244 return read_id_aa64isar0_el1() & ID_AA64ISAR0_SM3; 245 #endif 246 } 247 248 static inline bool feat_sm4_implemented(void) 249 { 250 #ifdef ARM32 251 return false; 252 #else 253 return read_id_aa64isar0_el1() & ID_AA64ISAR0_SM4; 254 #endif 255 } 256 257 static inline bool feat_pauth_is_implemented(void) 258 { 259 #ifdef ARM32 260 return false; 261 #else 262 uint64_t mask = 263 SHIFT_U64(ID_AA64ISAR1_GPI_MASK, ID_AA64ISAR1_GPI_SHIFT) | 264 SHIFT_U64(ID_AA64ISAR1_GPA_MASK, ID_AA64ISAR1_GPA_SHIFT) | 265 SHIFT_U64(ID_AA64ISAR1_API_MASK, ID_AA64ISAR1_API_SHIFT) | 266 SHIFT_U64(ID_AA64ISAR1_APA_MASK, ID_AA64ISAR1_APA_SHIFT); 267 268 /* If any of the fields is not zero, PAuth is implemented by arch */ 269 return (read_id_aa64isar1_el1() & mask) != 0U; 270 #endif 271 } 272 273 #endif 274 275 #endif /*__ARM_H*/ 276