1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 * Copyright (c) 2019-2023, Arm Limited. All rights reserved. 5 */ 6 #ifndef __ARM_H 7 #define __ARM_H 8 9 #include <stdbool.h> 10 #include <stdint.h> 11 #include <util.h> 12 13 /* MIDR definitions */ 14 #define MIDR_PRIMARY_PART_NUM_SHIFT U(4) 15 #define MIDR_PRIMARY_PART_NUM_WIDTH U(12) 16 #define MIDR_PRIMARY_PART_NUM_MASK (BIT(MIDR_PRIMARY_PART_NUM_WIDTH) - 1) 17 18 #define MIDR_IMPLEMENTER_SHIFT U(24) 19 #define MIDR_IMPLEMENTER_WIDTH U(8) 20 #define MIDR_IMPLEMENTER_MASK (BIT(MIDR_IMPLEMENTER_WIDTH) - 1) 21 #define MIDR_IMPLEMENTER_ARM U(0x41) 22 23 #define MIDR_VARIANT_SHIFT U(20) 24 #define MIDR_VARIANT_WIDTH U(4) 25 #define MIDR_VARIANT_MASK (BIT(MIDR_VARIANT_WIDTH) - 1) 26 27 #define MIDR_REVISION_SHIFT U(0) 28 #define MIDR_REVISION_WIDTH U(4) 29 #define MIDR_REVISION_MASK (BIT(MIDR_REVISION_WIDTH) - 1) 30 31 #define CORTEX_A5_PART_NUM U(0xC05) 32 #define CORTEX_A7_PART_NUM U(0xC07) 33 #define CORTEX_A8_PART_NUM U(0xC08) 34 #define CORTEX_A9_PART_NUM U(0xC09) 35 #define CORTEX_A15_PART_NUM U(0xC0F) 36 #define CORTEX_A17_PART_NUM U(0xC0E) 37 #define CORTEX_A57_PART_NUM U(0xD07) 38 #define CORTEX_A72_PART_NUM U(0xD08) 39 #define CORTEX_A73_PART_NUM U(0xD09) 40 #define CORTEX_A75_PART_NUM U(0xD0A) 41 #define CORTEX_A65_PART_NUM U(0xD06) 42 #define CORTEX_A65AE_PART_NUM U(0xD43) 43 #define CORTEX_A76_PART_NUM U(0xD0B) 44 #define CORTEX_A76AE_PART_NUM U(0xD0E) 45 #define CORTEX_A77_PART_NUM U(0xD0D) 46 #define CORTEX_A78_PART_NUM U(0xD41) 47 #define CORTEX_A78AE_PART_NUM U(0xD42) 48 #define CORTEX_A78C_PART_NUM U(0xD4B) 49 #define CORTEX_A710_PART_NUM U(0xD47) 50 #define CORTEX_X1_PART_NUM U(0xD44) 51 #define CORTEX_X2_PART_NUM U(0xD48) 52 #define NEOVERSE_E1_PART_NUM U(0xD4A) 53 #define NEOVERSE_N1_PART_NUM U(0xD0C) 54 #define NEOVERSE_N2_PART_NUM U(0xD49) 55 #define NEOVERSE_V1_PART_NUM U(0xD40) 56 57 /* MPIDR definitions */ 58 #define MPIDR_AFFINITY_BITS U(8) 59 #define MPIDR_AFFLVL_MASK ULL(0xff) 60 #define MPIDR_AFF0_SHIFT U(0) 61 #define MPIDR_AFF0_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT) 62 #define MPIDR_AFF1_SHIFT U(8) 63 #define MPIDR_AFF1_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) 64 #define MPIDR_AFF2_SHIFT U(16) 65 #define MPIDR_AFF2_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) 66 #define MPIDR_AFF3_SHIFT U(32) 67 #define MPIDR_AFF3_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) 68 69 #define MPIDR_MT_SHIFT U(24) 70 #define MPIDR_MT_MASK BIT(MPIDR_MT_SHIFT) 71 72 #define MPIDR_CPU_MASK MPIDR_AFF0_MASK 73 #define MPIDR_CLUSTER_SHIFT MPIDR_AFF1_SHIFT 74 #define MPIDR_CLUSTER_MASK MPIDR_AFF1_MASK 75 76 #define MPIDR_AARCH32_AFF_MASK (MPIDR_AFF0_MASK | MPIDR_AFF1_MASK | \ 77 MPIDR_AFF2_MASK) 78 79 /* ID_ISAR5 Cryptography Extension masks */ 80 #define ID_ISAR5_AES GENMASK_32(7, 4) 81 #define ID_ISAR5_SHA1 GENMASK_32(11, 8) 82 #define ID_ISAR5_SHA2 GENMASK_32(15, 12) 83 #define ID_ISAR5_CRC32 GENMASK_32(19, 16) 84 85 /* CLIDR definitions */ 86 #define CLIDR_LOUIS_SHIFT U(21) 87 #define CLIDR_LOC_SHIFT U(24) 88 #define CLIDR_FIELD_WIDTH U(3) 89 90 /* CSSELR definitions */ 91 #define CSSELR_LEVEL_SHIFT U(1) 92 93 /* CTR definitions */ 94 #define CTR_CWG_SHIFT U(24) 95 #define CTR_CWG_MASK U(0xf) 96 #define CTR_ERG_SHIFT U(20) 97 #define CTR_ERG_MASK U(0xf) 98 #define CTR_DMINLINE_SHIFT U(16) 99 #define CTR_DMINLINE_WIDTH U(4) 100 #define CTR_DMINLINE_MASK (BIT(4) - 1) 101 #define CTR_L1IP_SHIFT U(14) 102 #define CTR_L1IP_MASK U(0x3) 103 #define CTR_IMINLINE_SHIFT U(0) 104 #define CTR_IMINLINE_MASK U(0xf) 105 #define CTR_WORD_SIZE U(4) 106 107 #define ARM32_CPSR_MODE_MASK U(0x1f) 108 #define ARM32_CPSR_MODE_USR U(0x10) 109 #define ARM32_CPSR_MODE_FIQ U(0x11) 110 #define ARM32_CPSR_MODE_IRQ U(0x12) 111 #define ARM32_CPSR_MODE_SVC U(0x13) 112 #define ARM32_CPSR_MODE_MON U(0x16) 113 #define ARM32_CPSR_MODE_ABT U(0x17) 114 #define ARM32_CPSR_MODE_UND U(0x1b) 115 #define ARM32_CPSR_MODE_SYS U(0x1f) 116 117 #define ARM32_CPSR_T BIT(5) 118 #define ARM32_CPSR_F_SHIFT U(6) 119 #define ARM32_CPSR_F BIT(6) 120 #define ARM32_CPSR_I BIT(7) 121 #define ARM32_CPSR_A BIT(8) 122 #define ARM32_CPSR_E BIT(9) 123 #define ARM32_CPSR_FIA (ARM32_CPSR_F | ARM32_CPSR_I | ARM32_CPSR_A) 124 #define ARM32_CPSR_IT_MASK (ARM32_CPSR_IT_MASK1 | ARM32_CPSR_IT_MASK2) 125 #define ARM32_CPSR_IT_MASK1 U(0x06000000) 126 #define ARM32_CPSR_IT_MASK2 U(0x0000fc00) 127 128 /* ARM Generic timer definitions */ 129 #define CNTKCTL_PL0PCTEN BIT(0) /* physical counter el0 access enable */ 130 #define CNTKCTL_PL0VCTEN BIT(1) /* virtual counter el0 access enable */ 131 132 #ifdef ARM32 133 #include <arm32.h> 134 #endif 135 136 #ifdef ARM64 137 #include <arm64.h> 138 #endif 139 140 #ifndef __ASSEMBLER__ 141 static inline __noprof uint64_t barrier_read_counter_timer(void) 142 { 143 isb(); 144 #ifdef CFG_CORE_SEL2_SPMC 145 return read_cntvct(); 146 #else 147 return read_cntpct(); 148 #endif 149 } 150 151 static inline bool feat_bti_is_implemented(void) 152 { 153 #ifdef ARM32 154 return false; 155 #else 156 return ((read_id_aa64pfr1_el1() & ID_AA64PFR1_EL1_BT_MASK) == 157 FEAT_BTI_IMPLEMENTED); 158 #endif 159 } 160 161 static inline unsigned int feat_mte_implemented(void) 162 { 163 #ifdef ARM32 164 return 0; 165 #else 166 return (read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_MTE_SHIFT) & 167 ID_AA64PFR1_EL1_MTE_MASK; 168 #endif 169 } 170 171 static inline unsigned int feat_pan_implemented(void) 172 { 173 #ifdef ARM32 174 return 0; 175 #else 176 return (read_id_aa64mmfr1_el1() >> ID_AA64MMFR1_EL1_PAN_SHIFT) & 177 ID_AA64MMFR1_EL1_PAN_MASK; 178 #endif 179 } 180 181 static inline bool feat_crc32_implemented(void) 182 { 183 #ifdef ARM32 184 return read_id_isar5() & ID_ISAR5_CRC32; 185 #else 186 return read_id_aa64isar0_el1() & ID_AA64ISAR0_CRC32; 187 #endif 188 } 189 190 static inline bool feat_aes_implemented(void) 191 { 192 #ifdef ARM32 193 return read_id_isar5() & ID_ISAR5_AES; 194 #else 195 return read_id_aa64isar0_el1() & ID_AA64ISAR0_AES; 196 #endif 197 } 198 199 static inline bool feat_sha1_implemented(void) 200 { 201 #ifdef ARM32 202 return read_id_isar5() & ID_ISAR5_SHA1; 203 #else 204 return read_id_aa64isar0_el1() & ID_AA64ISAR0_SHA1; 205 #endif 206 } 207 208 static inline bool feat_sha256_implemented(void) 209 { 210 #ifdef ARM32 211 return read_id_isar5() & ID_ISAR5_SHA2; 212 #else 213 return read_id_aa64isar0_el1() & ID_AA64ISAR0_SHA2; 214 #endif 215 } 216 217 static inline bool feat_sha512_implemented(void) 218 { 219 #ifdef ARM32 220 return false; 221 #else 222 return ((read_id_aa64isar0_el1() & ID_AA64ISAR0_SHA2) >> 223 ID_AA64ISAR0_SHA2_SHIFT) == ID_AA64ISAR0_SHA2_FEAT_SHA512; 224 #endif 225 } 226 227 static inline bool feat_sha3_implemented(void) 228 { 229 #ifdef ARM32 230 return false; 231 #else 232 return read_id_aa64isar0_el1() & ID_AA64ISAR0_SHA3; 233 #endif 234 } 235 236 static inline bool feat_sm3_implemented(void) 237 { 238 #ifdef ARM32 239 return false; 240 #else 241 return read_id_aa64isar0_el1() & ID_AA64ISAR0_SM3; 242 #endif 243 } 244 245 static inline bool feat_sm4_implemented(void) 246 { 247 #ifdef ARM32 248 return false; 249 #else 250 return read_id_aa64isar0_el1() & ID_AA64ISAR0_SM4; 251 #endif 252 } 253 254 static inline bool feat_pauth_is_implemented(void) 255 { 256 #ifdef ARM32 257 return false; 258 #else 259 uint64_t mask = 260 SHIFT_U64(ID_AA64ISAR1_GPI_MASK, ID_AA64ISAR1_GPI_SHIFT) | 261 SHIFT_U64(ID_AA64ISAR1_GPA_MASK, ID_AA64ISAR1_GPA_SHIFT) | 262 SHIFT_U64(ID_AA64ISAR1_API_MASK, ID_AA64ISAR1_API_SHIFT) | 263 SHIFT_U64(ID_AA64ISAR1_APA_MASK, ID_AA64ISAR1_APA_SHIFT); 264 265 /* If any of the fields is not zero, PAuth is implemented by arch */ 266 return (read_id_aa64isar1_el1() & mask) != 0U; 267 #endif 268 } 269 270 #endif 271 272 #endif /*__ARM_H*/ 273