1 /* 2 * Copyright (c) 2015, Linaro Limited 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #ifndef ARM_H 28 #define ARM_H 29 30 31 #define MPIDR_CPU_MASK 0xff 32 #define MPIDR_CLUSTER_SHIFT 8 33 #define MPIDR_CLUSTER_MASK (0xff << MPIDR_CLUSTER_SHIFT) 34 35 #define ARM32_CPSR_MODE_MASK 0x1f 36 #define ARM32_CPSR_MODE_USR 0x10 37 #define ARM32_CPSR_MODE_FIQ 0x11 38 #define ARM32_CPSR_MODE_IRQ 0x12 39 #define ARM32_CPSR_MODE_SVC 0x13 40 #define ARM32_CPSR_MODE_MON 0x16 41 #define ARM32_CPSR_MODE_ABT 0x17 42 #define ARM32_CPSR_MODE_UND 0x1b 43 #define ARM32_CPSR_MODE_SYS 0x1f 44 45 #define ARM32_CPSR_T (1 << 5) 46 #define ARM32_CPSR_F_SHIFT 6 47 #define ARM32_CPSR_F (1 << 6) 48 #define ARM32_CPSR_I (1 << 7) 49 #define ARM32_CPSR_A (1 << 8) 50 #define ARM32_CPSR_E (1 << 9) 51 #define ARM32_CPSR_FIA (ARM32_CPSR_F | ARM32_CPSR_I | ARM32_CPSR_A) 52 #define ARM32_CPSR_IT_MASK (ARM32_CPSR_IT_MASK1 | ARM32_CPSR_IT_MASK2) 53 #define ARM32_CPSR_IT_MASK1 0x06000000 54 #define ARM32_CPSR_IT_MASK2 0x0000fc00 55 56 57 #ifdef ARM32 58 #include <arm32.h> 59 #endif 60 61 #ifdef ARM64 62 #include <arm64.h> 63 #endif 64 65 #endif /*ARM_H*/ 66