1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 */ 5 #ifndef ARM_H 6 #define ARM_H 7 8 #include <util.h> 9 10 /* MIDR definitions */ 11 #define MIDR_PRIMARY_PART_NUM_SHIFT 4 12 #define MIDR_PRIMARY_PART_NUM_WIDTH 12 13 #define MIDR_PRIMARY_PART_NUM_MASK (BIT(MIDR_PRIMARY_PART_NUM_WIDTH) - 1) 14 15 #define MIDR_IMPLEMENTER_SHIFT 24 16 #define MIDR_IMPLEMENTER_WIDTH 8 17 #define MIDR_IMPLEMENTER_MASK (BIT(MIDR_IMPLEMENTER_WIDTH) - 1) 18 #define MIDR_IMPLEMENTER_ARM 0x41 19 20 #define CORTEX_A7_PART_NUM 0xC07 21 #define CORTEX_A8_PART_NUM 0xC08 22 #define CORTEX_A9_PART_NUM 0xC09 23 #define CORTEX_A15_PART_NUM 0xC0F 24 #define CORTEX_A17_PART_NUM 0xC0E 25 #define CORTEX_A57_PART_NUM 0xD07 26 #define CORTEX_A72_PART_NUM 0xD08 27 #define CORTEX_A73_PART_NUM 0xD09 28 #define CORTEX_A75_PART_NUM 0xD0A 29 30 /* MPIDR definitions */ 31 #define MPIDR_CPU_MASK 0xff 32 #define MPIDR_CLUSTER_SHIFT 8 33 #define MPIDR_CLUSTER_MASK (0xff << MPIDR_CLUSTER_SHIFT) 34 35 /* CLIDR definitions */ 36 #define CLIDR_LOUIS_SHIFT 21 37 #define CLIDR_LOC_SHIFT 24 38 #define CLIDR_FIELD_WIDTH 3 39 40 /* CSSELR definitions */ 41 #define CSSELR_LEVEL_SHIFT 1 42 43 /* CTR definitions */ 44 #define CTR_CWG_SHIFT 24 45 #define CTR_CWG_MASK 0xf 46 #define CTR_ERG_SHIFT 20 47 #define CTR_ERG_MASK 0xf 48 #define CTR_DMINLINE_SHIFT 16 49 #define CTR_DMINLINE_WIDTH 4 50 #define CTR_DMINLINE_MASK ((1 << 4) - 1) 51 #define CTR_L1IP_SHIFT 14 52 #define CTR_L1IP_MASK 0x3 53 #define CTR_IMINLINE_SHIFT 0 54 #define CTR_IMINLINE_MASK 0xf 55 #define CTR_WORD_SIZE 4 56 57 #define ARM32_CPSR_MODE_MASK 0x1f 58 #define ARM32_CPSR_MODE_USR 0x10 59 #define ARM32_CPSR_MODE_FIQ 0x11 60 #define ARM32_CPSR_MODE_IRQ 0x12 61 #define ARM32_CPSR_MODE_SVC 0x13 62 #define ARM32_CPSR_MODE_MON 0x16 63 #define ARM32_CPSR_MODE_ABT 0x17 64 #define ARM32_CPSR_MODE_UND 0x1b 65 #define ARM32_CPSR_MODE_SYS 0x1f 66 67 #define ARM32_CPSR_T (1 << 5) 68 #define ARM32_CPSR_F_SHIFT 6 69 #define ARM32_CPSR_F (1 << 6) 70 #define ARM32_CPSR_I (1 << 7) 71 #define ARM32_CPSR_A (1 << 8) 72 #define ARM32_CPSR_E (1 << 9) 73 #define ARM32_CPSR_FIA (ARM32_CPSR_F | ARM32_CPSR_I | ARM32_CPSR_A) 74 #define ARM32_CPSR_IT_MASK (ARM32_CPSR_IT_MASK1 | ARM32_CPSR_IT_MASK2) 75 #define ARM32_CPSR_IT_MASK1 0x06000000 76 #define ARM32_CPSR_IT_MASK2 0x0000fc00 77 78 /* ARM Generic timer definitions */ 79 #define CNTKCTL_PL0PCTEN BIT(0) /* physical counter el0 access enable */ 80 #define CNTKCTL_PL0VCTEN BIT(1) /* virtual counter el0 access enable */ 81 82 #ifdef ARM32 83 #include <arm32.h> 84 #endif 85 86 #ifdef ARM64 87 #include <arm64.h> 88 #endif 89 90 #endif /*ARM_H*/ 91