xref: /optee_os/core/arch/arm/dts/stm32mp257f-ev1-ca35tdcid-rcc.dtsi (revision 9f34db38245c9b3a4e6e7e63eb78a75e23ab2da3) 
1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2024 - All Rights Reserved
4 */
5
6&clk_hse {
7	clock-frequency = <40000000>;
8};
9
10&clk_hsi {
11	clock-frequency = <64000000>;
12};
13
14&clk_lse {
15	clock-frequency = <32768>;
16};
17
18&clk_lsi {
19	clock-frequency = <32000>;
20};
21
22&clk_msi {
23	clock-frequency = <16000000>;
24};
25
26&rcc {
27	st,busclk = <
28		DIV_CFG(DIV_LSMCU, 1)
29		DIV_CFG(DIV_APB1, 0)
30		DIV_CFG(DIV_APB2, 0)
31		DIV_CFG(DIV_APB3, 0)
32		DIV_CFG(DIV_APB4, 0)
33		DIV_CFG(DIV_APBDBG, 0)
34	>;
35
36	st,flexgen = <
37		FLEXGEN_CFG(0, XBAR_SRC_PLL4, 0, 2)
38		FLEXGEN_CFG(1, XBAR_SRC_PLL4, 0, 5)
39		FLEXGEN_CFG(2, XBAR_SRC_PLL4, 0, 1)
40		FLEXGEN_CFG(3, XBAR_SRC_PLL4, 0, 2)
41		FLEXGEN_CFG(4, XBAR_SRC_PLL4, 0, 3)
42		FLEXGEN_CFG(5, XBAR_SRC_PLL4, 0, 2)
43		FLEXGEN_CFG(6, XBAR_SRC_PLL4, 0, 1)
44		FLEXGEN_CFG(7, XBAR_SRC_PLL4, 0, 11)
45		FLEXGEN_CFG(8, XBAR_SRC_HSI_KER, 0, 0)
46		FLEXGEN_CFG(9, XBAR_SRC_HSI_KER, 0, 0)
47		FLEXGEN_CFG(10, XBAR_SRC_PLL7, 0, 16)
48		FLEXGEN_CFG(11, XBAR_SRC_PLL4, 0, 5)
49		FLEXGEN_CFG(12, XBAR_SRC_PLL4, 0, 11)
50		FLEXGEN_CFG(13, XBAR_SRC_PLL4, 0, 11)
51		FLEXGEN_CFG(14, XBAR_SRC_PLL4, 0, 11)
52		FLEXGEN_CFG(15, XBAR_SRC_PLL4, 0, 11)
53		FLEXGEN_CFG(16, XBAR_SRC_PLL4, 0, 23)
54		FLEXGEN_CFG(17, XBAR_SRC_PLL5, 0, 3)
55		FLEXGEN_CFG(18, XBAR_SRC_PLL5, 0, 3)
56		FLEXGEN_CFG(19, XBAR_SRC_HSI_KER, 0, 3)
57		FLEXGEN_CFG(20, XBAR_SRC_HSI_KER, 0, 0)
58		FLEXGEN_CFG(21, XBAR_SRC_HSI_KER, 0, 0)
59		FLEXGEN_CFG(22, XBAR_SRC_HSI_KER, 0, 0)
60		FLEXGEN_CFG(23, XBAR_SRC_PLL7, 0, 16)
61		FLEXGEN_CFG(24, XBAR_SRC_PLL7, 0, 16)
62		FLEXGEN_CFG(25, XBAR_SRC_PLL7, 0, 16)
63		FLEXGEN_CFG(26, XBAR_SRC_PLL4, 0, 11)
64		FLEXGEN_CFG(27, XBAR_SRC_PLL8, 0, 3)
65		FLEXGEN_CFG(28, XBAR_SRC_PLL8, 0, 21)
66		FLEXGEN_CFG(29, XBAR_SRC_PLL5, 0, 1)
67		FLEXGEN_CFG(30, XBAR_SRC_HSE_KER, 0, 1)
68		FLEXGEN_CFG(31, XBAR_SRC_PLL5, 0, 19)
69		FLEXGEN_CFG(32, XBAR_SRC_PLL5, 0, 19)
70		FLEXGEN_CFG(33, XBAR_SRC_HSE_KER, 0, 0)
71		FLEXGEN_CFG(34, XBAR_SRC_PLL4, 0, 59)
72		FLEXGEN_CFG(35, XBAR_SRC_HSI_KER, 0, 3)
73		FLEXGEN_CFG(36, XBAR_SRC_PLL5, 0, 3)
74		FLEXGEN_CFG(37, XBAR_SRC_PLL5, 0, 3)
75		FLEXGEN_CFG(38, XBAR_SRC_PLL5, 0, 3)
76		FLEXGEN_CFG(39, XBAR_SRC_MSI_KER, 0, 0)
77		FLEXGEN_CFG(40, XBAR_SRC_LSE, 0, 0)
78		FLEXGEN_CFG(41, XBAR_SRC_PLL4, 0, 11)
79		FLEXGEN_CFG(42, XBAR_SRC_PLL7, 0, 16)
80		FLEXGEN_CFG(43, XBAR_SRC_PLL4, 0, 23)
81		FLEXGEN_CFG(44, XBAR_SRC_PLL4, 0, 5)
82		FLEXGEN_CFG(45, XBAR_SRC_PLL4, 0, 2)
83		FLEXGEN_CFG(46, XBAR_SRC_PLL5, 0, 3)
84		FLEXGEN_CFG(47, XBAR_SRC_PLL5, 0, 3)
85		FLEXGEN_CFG(48, XBAR_SRC_PLL5, 0, 3)
86		FLEXGEN_CFG(49, XBAR_SRC_PLL5, 0, 3)
87		FLEXGEN_CFG(51, XBAR_SRC_PLL4, 0, 5)
88		FLEXGEN_CFG(52, XBAR_SRC_PLL4, 0, 5)
89		FLEXGEN_CFG(53, XBAR_SRC_PLL4, 0, 5)
90		FLEXGEN_CFG(54, XBAR_SRC_PLL6, 0, 3)
91		FLEXGEN_CFG(55, XBAR_SRC_PLL6, 0, 3)
92		FLEXGEN_CFG(56, XBAR_SRC_PLL4, 0, 5)
93		FLEXGEN_CFG(57, XBAR_SRC_HSE_KER, 0, 1)
94		FLEXGEN_CFG(58, XBAR_SRC_HSE_KER, 0, 1)
95		FLEXGEN_CFG(59, XBAR_SRC_PLL4, 0, 1)
96		FLEXGEN_CFG(60, XBAR_SRC_PLL4, 0, 23)
97		FLEXGEN_CFG(61, XBAR_SRC_PLL4, 0, 7)
98		FLEXGEN_CFG(62, XBAR_SRC_PLL4, 0, 7)
99		FLEXGEN_CFG(63, XBAR_SRC_PLL4, 0, 2)
100	>;
101
102	st,kerclk = <
103		MUX_CFG(MUX_ADC12, MUX_ADC12_FLEX46)
104		MUX_CFG(MUX_USB2PHY1, MUX_USB2PHY1_FLEX57)
105		MUX_CFG(MUX_USB2PHY2, MUX_USB2PHY2_FLEX58)
106		MUX_CFG(MUX_USB3PCIEPHY, MUX_USB3PCIEPHY_HSE)
107		MUX_CFG(MUX_DSIPHY, MUX_DSIPHY_FLEX28)
108		MUX_CFG(MUX_DSIBLANE, MUX_DSIBLANE_DSIPHY)
109		MUX_CFG(MUX_LVDSPHY, MUX_LVDSPHY_FLEX32)
110		MUX_CFG(MUX_DTS, MUX_DTS_HSE)
111		MUX_CFG(MUX_RTC, MUX_RTC_LSE)
112		MUX_CFG(MUX_D3PER, MUX_D3PER_MSI)
113		MCO_CFG(MCO1, MUX_MCO1_FLEX61, MCO_OFF)
114		MCO_CFG(MCO2, MUX_MCO2_FLEX62, MCO_OFF)
115	>;
116
117	pll1: st,pll-1 {
118		st,pll = <&pll1_cfg_1200Mhz>;
119
120		pll1_cfg_1200Mhz: pll1-cfg-1200Mhz {
121			cfg = <30 1 1 1>;
122			src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>;
123		};
124
125		pll1_cfg_1500Mhz: pll1-cfg-1500Mhz {
126			cfg = <75 2 1 1>;
127			src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>;
128		};
129	};
130
131	pll2: st,pll-2 {
132		st,pll = <&pll2_cfg_600Mhz>;
133
134		pll2_cfg_600Mhz: pll2-cfg-600Mhz {
135			cfg = <30 1 1 2>;
136			src = <MUX_CFG(MUX_MUXSEL6, MUXSEL_HSE)>;
137		};
138	};
139
140	pll3: st,pll-3 {
141		st,pll = <&pll3_cfg_800Mhz>;
142
143		pll3_cfg_800Mhz: pll3-cfg-800Mhz {
144			cfg = <20 1 1 1>;
145			src = <MUX_CFG(MUX_MUXSEL7, MUXSEL_HSE)>;
146		};
147
148		pll3_cfg_900Mhz: pll3-cfg-900Mhz {
149			cfg = <45 2 1 1>;
150			src = <MUX_CFG(MUX_MUXSEL7, MUXSEL_HSE)>;
151		};
152	};
153
154	pll4: st,pll-4 {
155		st,pll = <&pll4_cfg_1200Mhz>;
156
157		pll4_cfg_1200Mhz: pll4-cfg-1200Mhz {
158			cfg = <30 1 1 1>;
159			src = <MUX_CFG(MUX_MUXSEL0, MUXSEL_HSE)>;
160		};
161	};
162
163	pll5: st,pll-5 {
164		st,pll = <&pll5_cfg_532Mhz>;
165
166		pll5_cfg_532Mhz: pll5-cfg-532Mhz {
167			cfg = <133 5 1 2>;
168			src = <MUX_CFG(MUX_MUXSEL1, MUXSEL_HSE)>;
169		};
170	};
171
172	pll6: st,pll-6 {
173		st,pll = <&pll6_cfg_500Mhz>;
174
175		pll6_cfg_500Mhz: pll6-cfg-500Mhz {
176			cfg = <25 1 1 2>;
177			src = <MUX_CFG(MUX_MUXSEL2, MUXSEL_HSE)>;
178		};
179	};
180
181	pll7: st,pll-7 {
182		st,pll = <&pll7_cfg_835_51172Mhz>;
183
184		pll7_cfg_835_51172Mhz: pll7-cfg-835-51172Mhz {
185			cfg = <167 4 1 2>;
186			src = <MUX_CFG(MUX_MUXSEL3, MUXSEL_HSE)>;
187			frac = < 0x1A3337 >;
188		};
189	};
190
191	pll8: st,pll-8 {
192		st,pll = <&pll8_cfg_594Mhz>;
193
194		pll8_cfg_594Mhz: pll8-cfg-594Mhz {
195			cfg = <297 5 1 4>;
196			src = <MUX_CFG(MUX_MUXSEL4, MUXSEL_HSE)>;
197		};
198	};
199};
200