xref: /optee_os/core/arch/arm/dts/stm32mp251.dtsi (revision fc9ea0db8ddf8150754aac716691616c7e3f404a) 
1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
5 */
6
7#include <dt-bindings/clock/st,stm32mp25-rcc.h>
8#include <dt-bindings/firewall/stm32mp25-rif.h>
9#include <dt-bindings/firewall/stm32mp25-rifsc.h>
10#include <dt-bindings/firewall/stm32mp25-risaf.h>
11#include <dt-bindings/firewall/stm32mp25-risab.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/reset/st,stm32mp25-rcc.h>
14
15/ {
16	#address-cells = <2>;
17	#size-cells = <2>;
18
19	cpus {
20		#address-cells = <1>;
21		#size-cells = <0>;
22
23		cpu0: cpu@0 {
24			compatible = "arm,cortex-a35";
25			device_type = "cpu";
26			reg = <0>;
27			enable-method = "psci";
28		};
29	};
30
31	psci {
32		compatible = "arm,psci-1.0";
33		method = "smc";
34	};
35
36	intc: interrupt-controller@4ac00000 {
37		compatible = "arm,cortex-a7-gic";
38		#interrupt-cells = <3>;
39		interrupt-controller;
40		reg = <0x0 0x4ac10000 0x0 0x1000>,
41		      <0x0 0x4ac20000 0x0 0x2000>,
42		      <0x0 0x4ac40000 0x0 0x2000>,
43		      <0x0 0x4ac60000 0x0 0x2000>;
44		#address-cells = <1>;
45	};
46
47	clocks {
48		clk_hse: clk-hse {
49			#clock-cells = <0>;
50			compatible = "fixed-clock";
51			clock-frequency = <24000000>;
52		};
53
54		clk_hsi: clk-hsi {
55			#clock-cells = <0>;
56			compatible = "fixed-clock";
57			clock-frequency = <64000000>;
58		};
59
60		clk_lse: clk-lse {
61			#clock-cells = <0>;
62			compatible = "fixed-clock";
63			clock-frequency = <32768>;
64		};
65
66		clk_lsi: clk-lsi {
67			#clock-cells = <0>;
68			compatible = "fixed-clock";
69			clock-frequency = <32000>;
70		};
71
72		clk_msi: clk-msi {
73			#clock-cells = <0>;
74			compatible = "fixed-clock";
75			clock-frequency = <4000000>;
76		};
77
78		clk_i2sin: clk-i2sin {
79			#clock-cells = <0>;
80			compatible = "fixed-clock";
81			clock-frequency = <0>;
82		};
83
84		clk_rcbsec: clk-rcbsec {
85			#clock-cells = <0>;
86			compatible = "fixed-clock";
87			clock-frequency = <64000000>;
88		};
89	};
90
91	soc@0 {
92		compatible = "simple-bus";
93		#address-cells = <1>;
94		#size-cells = <1>;
95		interrupt-parent = <&intc>;
96		ranges = <0x0 0x0 0x0 0x80000000>;
97
98		hpdma1: dma-controller@40400000 {
99			compatible = "st,stm32-dma3";
100			reg = <0x40400000 0x1000>;
101			#dma-cells = <4>;
102			status = "disabled";
103		};
104
105		hpdma2: dma-controller@40410000 {
106			compatible = "st,stm32-dma3";
107			reg = <0x40410000 0x1000>;
108			#dma-cells = <4>;
109			status = "disabled";
110		};
111
112		hpdma3: dma-controller@40420000 {
113			compatible = "st,stm32-dma3";
114			reg = <0x40420000 0x1000>;
115			#dma-cells = <4>;
116			status = "disabled";
117		};
118
119		ipcc1: mailbox@40490000 {
120			compatible = "st,stm32mp25-ipcc";
121			reg = <0x40490000 0x400>;
122			status = "disabled";
123		};
124
125		rifsc: rifsc@42080000 {
126			compatible = "st,stm32mp25-rifsc", "simple-bus";
127			reg = <0x42080000 0x1000>;
128			#address-cells = <1>;
129			#size-cells = <1>;
130			#access-controller-cells = <1>;
131
132			usart2: serial@400e0000 {
133				compatible = "st,stm32h7-uart";
134				reg = <0x400e0000 0x400>;
135				interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
136				clocks = <&rcc CK_KER_USART2>;
137				access-controllers = <&rifsc STM32MP25_RIFSC_USART2_ID>;
138				status = "disabled";
139			};
140
141			rng: rng@42020000 {
142				compatible = "st,stm32mp25-rng";
143				reg = <0x42020000 0x400>;
144				clocks = <&clk_rcbsec>, <&rcc CK_BUS_RNG>;
145				clock-names = "rng_clk", "rng_hclk";
146				resets = <&rcc RNG_R>;
147				access-controllers = <&rifsc STM32MP25_RIFSC_RNG_ID>;
148			};
149		};
150
151		iac: iac@42090000 {
152			compatible = "st,stm32mp25-iac";
153			reg = <0x42090000 0x400>;
154			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
155		};
156
157		risaf1: risaf@420a0000 {
158			compatible = "st,stm32mp25-risaf";
159			reg = <0x420a0000 0x1000>;
160			clocks = <&rcc CK_BUS_BKPSRAM>;
161			st,mem-map = <0x0 0x42000000 0x0 0x2000>;
162		};
163
164		risaf2: risaf@420b0000 {
165			compatible = "st,stm32mp25-risaf";
166			reg = <0x420b0000 0x1000>;
167			clocks = <&rcc CK_KER_OSPI1>;
168			st,mem-map = <0x0 0x60000000 0x0 0x10000000>;
169			status = "disabled";
170		};
171
172		risaf4: risaf@420d0000 {
173			compatible = "st,stm32mp25-risaf-enc";
174			reg = <0x420d0000 0x1000>;
175			clocks = <&rcc CK_BUS_RISAF4>;
176			st,mem-map = <0x0 0x80000000 0x1 0x00000000>;
177		};
178
179		risaf5: risaf@420e0000 {
180			compatible = "st,stm32mp25-risaf";
181			reg = <0x420e0000 0x1000>;
182			clocks = <&rcc CK_BUS_PCIE>;
183			st,mem-map = <0x0 0x10000000 0x0 0x10000000>;
184			status = "disabled";
185		};
186
187		risab1: risab@420f0000 {
188			compatible = "st,stm32mp25-risab";
189			reg = <0x420f0000 0x1000>;
190			clocks = <&rcc CK_ICN_LS_MCU>;
191			st,mem-map = <0xa000000 0x20000>;
192			#access-controller-cells = <1>;
193		};
194
195		risab2: risab@42100000 {
196			compatible = "st,stm32mp25-risab";
197			reg = <0x42100000 0x1000>;
198			clocks = <&rcc CK_ICN_LS_MCU>;
199			st,mem-map = <0xa020000 0x20000>;
200			#access-controller-cells = <1>;
201		};
202
203		risab3: risab@42110000 {
204			compatible = "st,stm32mp25-risab";
205			reg = <0x42110000 0x1000>;
206			clocks = <&rcc CK_ICN_LS_MCU>;
207			st,mem-map = <0xa040000 0x20000>;
208			#access-controller-cells = <1>;
209		};
210
211		risab4: risab@42120000 {
212			compatible = "st,stm32mp25-risab";
213			reg = <0x42120000 0x1000>;
214			clocks = <&rcc CK_ICN_LS_MCU>;
215			st,mem-map = <0xa060000 0x20000>;
216			#access-controller-cells = <1>;
217		};
218
219		risab5: risab@42130000 {
220			compatible = "st,stm32mp25-risab";
221			reg = <0x42130000 0x1000>;
222			clocks = <&rcc CK_ICN_LS_MCU>;
223			st,mem-map = <0xa080000 0x20000>;
224			#access-controller-cells = <1>;
225		};
226
227		risab6: risab@42140000 {
228			compatible = "st,stm32mp25-risab";
229			reg = <0x42140000 0x1000>;
230			clocks = <&rcc CK_ICN_LS_MCU>;
231			st,mem-map = <0xa0a0000 0x20000>;
232			#access-controller-cells = <1>;
233			status = "disabled";
234		};
235
236		serc: serc@44080000 {
237			compatible = "st,stm32mp25-serc";
238			reg = <0x44080000 0x1000>;
239			interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
240			clocks = <&rcc CK_BUS_SERC>;
241		};
242
243		rcc: rcc@44200000 {
244			compatible = "st,stm32mp25-rcc", "syscon";
245			reg = <0x44200000 0x10000>;
246			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
247
248			#clock-cells = <1>;
249			#reset-cells = <1>;
250			clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>,
251				 <&clk_lsi>, <&clk_msi>, <&clk_i2sin>;
252			clock-names = "clk-hse", "clk-hsi", "clk-lse",
253				      "clk-lsi", "clk-msi", "clk-i2sin";
254
255			hsi_calibration: hsi-calibration {
256				compatible = "st,hsi-cal";
257				st,cal_hsi_dev = <31>;
258				st,cal_hsi_ref = <1953>;
259				status = "disabled";
260			};
261
262			msi_calibration: msi-calibration {
263				compatible = "st,msi-cal";
264				status = "disabled";
265			};
266		};
267
268		pinctrl: pinctrl@44240000 {
269			#address-cells = <1>;
270			#size-cells = <1>;
271			compatible = "st,stm32mp257-pinctrl";
272			ranges = <0 0x44240000 0xa0400>;
273			pins-are-numbered;
274
275			gpioa: gpio@44240000 {
276				gpio-controller;
277				#gpio-cells = <2>;
278				interrupt-controller;
279				#interrupt-cells = <2>;
280				reg = <0x0 0x400>;
281				clocks = <&rcc CK_BUS_GPIOA>;
282				st,bank-name = "GPIOA";
283				status = "disabled";
284			};
285
286			gpiob: gpio@44250000 {
287				gpio-controller;
288				#gpio-cells = <2>;
289				interrupt-controller;
290				#interrupt-cells = <2>;
291				reg = <0x10000 0x400>;
292				clocks = <&rcc CK_BUS_GPIOB>;
293				st,bank-name = "GPIOB";
294				status = "disabled";
295			};
296
297			gpioc: gpio@44260000 {
298				gpio-controller;
299				#gpio-cells = <2>;
300				interrupt-controller;
301				#interrupt-cells = <2>;
302				reg = <0x20000 0x400>;
303				clocks = <&rcc CK_BUS_GPIOC>;
304				st,bank-name = "GPIOC";
305				status = "disabled";
306			};
307
308			gpiod: gpio@44270000 {
309				gpio-controller;
310				#gpio-cells = <2>;
311				interrupt-controller;
312				#interrupt-cells = <2>;
313				reg = <0x30000 0x400>;
314				clocks = <&rcc CK_BUS_GPIOD>;
315				st,bank-name = "GPIOD";
316				status = "disabled";
317			};
318
319			gpioe: gpio@44280000 {
320				gpio-controller;
321				#gpio-cells = <2>;
322				interrupt-controller;
323				#interrupt-cells = <2>;
324				reg = <0x40000 0x400>;
325				clocks = <&rcc CK_BUS_GPIOE>;
326				st,bank-name = "GPIOE";
327				status = "disabled";
328			};
329
330			gpiof: gpio@44290000 {
331				gpio-controller;
332				#gpio-cells = <2>;
333				interrupt-controller;
334				#interrupt-cells = <2>;
335				reg = <0x50000 0x400>;
336				clocks = <&rcc CK_BUS_GPIOF>;
337				st,bank-name = "GPIOF";
338				status = "disabled";
339			};
340
341			gpiog: gpio@442a0000 {
342				gpio-controller;
343				#gpio-cells = <2>;
344				interrupt-controller;
345				#interrupt-cells = <2>;
346				reg = <0x60000 0x400>;
347				clocks = <&rcc CK_BUS_GPIOG>;
348				st,bank-name = "GPIOG";
349				status = "disabled";
350			};
351
352			gpioh: gpio@442b0000 {
353				gpio-controller;
354				#gpio-cells = <2>;
355				interrupt-controller;
356				#interrupt-cells = <2>;
357				reg = <0x70000 0x400>;
358				clocks = <&rcc CK_BUS_GPIOH>;
359				st,bank-name = "GPIOH";
360				status = "disabled";
361			};
362
363			gpioi: gpio@442c0000 {
364				gpio-controller;
365				#gpio-cells = <2>;
366				interrupt-controller;
367				#interrupt-cells = <2>;
368				reg = <0x80000 0x400>;
369				clocks = <&rcc CK_BUS_GPIOI>;
370				st,bank-name = "GPIOI";
371				status = "disabled";
372			};
373
374			gpioj: gpio@442d0000 {
375				gpio-controller;
376				#gpio-cells = <2>;
377				interrupt-controller;
378				#interrupt-cells = <2>;
379				reg = <0x90000 0x400>;
380				clocks = <&rcc CK_BUS_GPIOJ>;
381				st,bank-name = "GPIOJ";
382				status = "disabled";
383			};
384
385			gpiok: gpio@442e0000 {
386				gpio-controller;
387				#gpio-cells = <2>;
388				interrupt-controller;
389				#interrupt-cells = <2>;
390				reg = <0xa0000 0x400>;
391				clocks = <&rcc CK_BUS_GPIOK>;
392				st,bank-name = "GPIOK";
393				status = "disabled";
394			};
395		};
396
397		pinctrl_z: pinctrl-z@46200000 {
398			#address-cells = <1>;
399			#size-cells = <1>;
400			compatible = "st,stm32mp257-z-pinctrl";
401			ranges = <0 0x46200000 0x400>;
402			pins-are-numbered;
403
404			gpioz: gpio@46200000 {
405				gpio-controller;
406				#gpio-cells = <2>;
407				interrupt-controller;
408				#interrupt-cells = <2>;
409				reg = <0 0x400>;
410				clocks = <&rcc CK_BUS_GPIOZ>;
411				st,bank-name = "GPIOZ";
412				st,bank-ioport = <11>;
413				status = "disabled";
414			};
415		};
416
417		hsem: hwspinlock@46240000 {
418			compatible = "st,stm32mp25-hsem";
419			reg = <0x46240000 0x400>;
420			interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
421			status = "disabled";
422		};
423
424		ipcc2: mailbox@46250000 {
425			compatible = "st,stm32mp25-ipcc";
426			reg = <0x46250000 0x400>;
427			status = "disabled";
428		};
429
430		fmc: memory-controller@48200000 {
431			#address-cells = <2>;
432			#size-cells = <1>;
433			compatible = "st,stm32mp25-fmc2-ebi";
434			reg = <0x48200000 0x400>;
435			status = "disabled";
436
437			ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
438				 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
439				 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
440				 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
441				 <4 0 0x80000000 0x10000000>; /* NAND */
442		};
443	};
444};
445