1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/clock/st,stm32mp25-rcc.h> 8#include <dt-bindings/firewall/stm32mp25-rif.h> 9#include <dt-bindings/firewall/stm32mp25-rifsc.h> 10#include <dt-bindings/firewall/stm32mp25-risaf.h> 11#include <dt-bindings/firewall/stm32mp25-risab.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/st,stm32mp25-rcc.h> 14 15/ { 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@0 { 24 compatible = "arm,cortex-a35"; 25 device_type = "cpu"; 26 reg = <0>; 27 enable-method = "psci"; 28 }; 29 }; 30 31 psci { 32 compatible = "arm,psci-1.0"; 33 method = "smc"; 34 }; 35 36 intc: interrupt-controller@4ac00000 { 37 compatible = "arm,cortex-a7-gic"; 38 #interrupt-cells = <3>; 39 interrupt-controller; 40 reg = <0x0 0x4ac10000 0x0 0x1000>, 41 <0x0 0x4ac20000 0x0 0x2000>, 42 <0x0 0x4ac40000 0x0 0x2000>, 43 <0x0 0x4ac60000 0x0 0x2000>; 44 #address-cells = <1>; 45 }; 46 47 clocks { 48 clk_hse: clk-hse { 49 #clock-cells = <0>; 50 compatible = "fixed-clock"; 51 clock-frequency = <24000000>; 52 }; 53 54 clk_hsi: clk-hsi { 55 #clock-cells = <0>; 56 compatible = "fixed-clock"; 57 clock-frequency = <64000000>; 58 }; 59 60 clk_lse: clk-lse { 61 #clock-cells = <0>; 62 compatible = "fixed-clock"; 63 clock-frequency = <32768>; 64 }; 65 66 clk_lsi: clk-lsi { 67 #clock-cells = <0>; 68 compatible = "fixed-clock"; 69 clock-frequency = <32000>; 70 }; 71 72 clk_msi: clk-msi { 73 #clock-cells = <0>; 74 compatible = "fixed-clock"; 75 clock-frequency = <4000000>; 76 }; 77 78 clk_i2sin: clk-i2sin { 79 #clock-cells = <0>; 80 compatible = "fixed-clock"; 81 clock-frequency = <0>; 82 }; 83 84 clk_rcbsec: clk-rcbsec { 85 #clock-cells = <0>; 86 compatible = "fixed-clock"; 87 clock-frequency = <64000000>; 88 }; 89 }; 90 91 soc@0 { 92 compatible = "simple-bus"; 93 #address-cells = <1>; 94 #size-cells = <1>; 95 interrupt-parent = <&intc>; 96 ranges = <0x0 0x0 0x0 0x80000000>; 97 98 hpdma1: dma-controller@40400000 { 99 compatible = "st,stm32-dma3"; 100 reg = <0x40400000 0x1000>; 101 clocks = <&rcc CK_BUS_HPDMA1>; 102 resets = <&rcc HPDMA1_R>; 103 #dma-cells = <4>; 104 status = "disabled"; 105 }; 106 107 hpdma2: dma-controller@40410000 { 108 compatible = "st,stm32-dma3"; 109 reg = <0x40410000 0x1000>; 110 clocks = <&rcc CK_BUS_HPDMA2>; 111 resets = <&rcc HPDMA2_R>; 112 #dma-cells = <4>; 113 status = "disabled"; 114 }; 115 116 hpdma3: dma-controller@40420000 { 117 compatible = "st,stm32-dma3"; 118 reg = <0x40420000 0x1000>; 119 clocks = <&rcc CK_BUS_HPDMA3>; 120 resets = <&rcc HPDMA3_R>; 121 #dma-cells = <4>; 122 status = "disabled"; 123 }; 124 125 ipcc1: mailbox@40490000 { 126 compatible = "st,stm32mp25-ipcc"; 127 reg = <0x40490000 0x400>; 128 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 129 interrupt-names = "rx"; 130 clocks = <&rcc CK_BUS_IPCC1>; 131 status = "disabled"; 132 }; 133 134 rifsc: rifsc@42080000 { 135 compatible = "st,stm32mp25-rifsc", "simple-bus"; 136 reg = <0x42080000 0x1000>; 137 #address-cells = <1>; 138 #size-cells = <1>; 139 #access-controller-cells = <1>; 140 141 usart2: serial@400e0000 { 142 compatible = "st,stm32h7-uart"; 143 reg = <0x400e0000 0x400>; 144 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 145 clocks = <&rcc CK_KER_USART2>; 146 access-controllers = <&rifsc STM32MP25_RIFSC_USART2_ID>; 147 status = "disabled"; 148 }; 149 150 rng: rng@42020000 { 151 compatible = "st,stm32mp25-rng"; 152 reg = <0x42020000 0x400>; 153 clocks = <&clk_rcbsec>, <&rcc CK_BUS_RNG>; 154 clock-names = "rng_clk", "rng_hclk"; 155 resets = <&rcc RNG_R>; 156 access-controllers = <&rifsc STM32MP25_RIFSC_RNG_ID>; 157 }; 158 }; 159 160 iac: iac@42090000 { 161 compatible = "st,stm32mp25-iac"; 162 reg = <0x42090000 0x400>; 163 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 164 }; 165 166 risaf1: risaf@420a0000 { 167 compatible = "st,stm32mp25-risaf"; 168 reg = <0x420a0000 0x1000>; 169 clocks = <&rcc CK_BUS_BKPSRAM>; 170 st,mem-map = <0x0 0x42000000 0x0 0x2000>; 171 }; 172 173 risaf2: risaf@420b0000 { 174 compatible = "st,stm32mp25-risaf"; 175 reg = <0x420b0000 0x1000>; 176 clocks = <&rcc CK_KER_OSPI1>; 177 st,mem-map = <0x0 0x60000000 0x0 0x10000000>; 178 status = "disabled"; 179 }; 180 181 risaf4: risaf@420d0000 { 182 compatible = "st,stm32mp25-risaf-enc"; 183 reg = <0x420d0000 0x1000>; 184 clocks = <&rcc CK_BUS_RISAF4>; 185 st,mem-map = <0x0 0x80000000 0x1 0x00000000>; 186 }; 187 188 risaf5: risaf@420e0000 { 189 compatible = "st,stm32mp25-risaf"; 190 reg = <0x420e0000 0x1000>; 191 clocks = <&rcc CK_BUS_PCIE>; 192 st,mem-map = <0x0 0x10000000 0x0 0x10000000>; 193 status = "disabled"; 194 }; 195 196 risab1: risab@420f0000 { 197 compatible = "st,stm32mp25-risab"; 198 reg = <0x420f0000 0x1000>; 199 clocks = <&rcc CK_ICN_LS_MCU>; 200 st,mem-map = <0xa000000 0x20000>; 201 #access-controller-cells = <1>; 202 }; 203 204 risab2: risab@42100000 { 205 compatible = "st,stm32mp25-risab"; 206 reg = <0x42100000 0x1000>; 207 clocks = <&rcc CK_ICN_LS_MCU>; 208 st,mem-map = <0xa020000 0x20000>; 209 #access-controller-cells = <1>; 210 }; 211 212 risab3: risab@42110000 { 213 compatible = "st,stm32mp25-risab"; 214 reg = <0x42110000 0x1000>; 215 clocks = <&rcc CK_ICN_LS_MCU>; 216 st,mem-map = <0xa040000 0x20000>; 217 #access-controller-cells = <1>; 218 }; 219 220 risab4: risab@42120000 { 221 compatible = "st,stm32mp25-risab"; 222 reg = <0x42120000 0x1000>; 223 clocks = <&rcc CK_ICN_LS_MCU>; 224 st,mem-map = <0xa060000 0x20000>; 225 #access-controller-cells = <1>; 226 }; 227 228 risab5: risab@42130000 { 229 compatible = "st,stm32mp25-risab"; 230 reg = <0x42130000 0x1000>; 231 clocks = <&rcc CK_ICN_LS_MCU>; 232 st,mem-map = <0xa080000 0x20000>; 233 #access-controller-cells = <1>; 234 }; 235 236 risab6: risab@42140000 { 237 compatible = "st,stm32mp25-risab"; 238 reg = <0x42140000 0x1000>; 239 clocks = <&rcc CK_ICN_LS_MCU>; 240 st,mem-map = <0xa0a0000 0x20000>; 241 #access-controller-cells = <1>; 242 status = "disabled"; 243 }; 244 245 serc: serc@44080000 { 246 compatible = "st,stm32mp25-serc"; 247 reg = <0x44080000 0x1000>; 248 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 249 clocks = <&rcc CK_BUS_SERC>; 250 }; 251 252 rcc: rcc@44200000 { 253 compatible = "st,stm32mp25-rcc", "syscon"; 254 reg = <0x44200000 0x10000>; 255 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 256 257 #clock-cells = <1>; 258 #reset-cells = <1>; 259 clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>, 260 <&clk_lsi>, <&clk_msi>, <&clk_i2sin>; 261 clock-names = "clk-hse", "clk-hsi", "clk-lse", 262 "clk-lsi", "clk-msi", "clk-i2sin"; 263 264 hsi_calibration: hsi-calibration { 265 compatible = "st,hsi-cal"; 266 st,cal_hsi_dev = <31>; 267 st,cal_hsi_ref = <1953>; 268 status = "disabled"; 269 }; 270 271 msi_calibration: msi-calibration { 272 compatible = "st,msi-cal"; 273 status = "disabled"; 274 }; 275 }; 276 277 pinctrl: pinctrl@44240000 { 278 #address-cells = <1>; 279 #size-cells = <1>; 280 compatible = "st,stm32mp257-pinctrl"; 281 ranges = <0 0x44240000 0xa0400>; 282 pins-are-numbered; 283 284 gpioa: gpio@44240000 { 285 gpio-controller; 286 #gpio-cells = <2>; 287 interrupt-controller; 288 #interrupt-cells = <2>; 289 #access-controller-cells = <1>; 290 reg = <0x0 0x400>; 291 clocks = <&rcc CK_BUS_GPIOA>; 292 st,bank-name = "GPIOA"; 293 status = "disabled"; 294 }; 295 296 gpiob: gpio@44250000 { 297 gpio-controller; 298 #gpio-cells = <2>; 299 interrupt-controller; 300 #interrupt-cells = <2>; 301 #access-controller-cells = <1>; 302 reg = <0x10000 0x400>; 303 clocks = <&rcc CK_BUS_GPIOB>; 304 st,bank-name = "GPIOB"; 305 status = "disabled"; 306 }; 307 308 gpioc: gpio@44260000 { 309 gpio-controller; 310 #gpio-cells = <2>; 311 interrupt-controller; 312 #interrupt-cells = <2>; 313 #access-controller-cells = <1>; 314 reg = <0x20000 0x400>; 315 clocks = <&rcc CK_BUS_GPIOC>; 316 st,bank-name = "GPIOC"; 317 status = "disabled"; 318 }; 319 320 gpiod: gpio@44270000 { 321 gpio-controller; 322 #gpio-cells = <2>; 323 interrupt-controller; 324 #interrupt-cells = <2>; 325 #access-controller-cells = <1>; 326 reg = <0x30000 0x400>; 327 clocks = <&rcc CK_BUS_GPIOD>; 328 st,bank-name = "GPIOD"; 329 status = "disabled"; 330 }; 331 332 gpioe: gpio@44280000 { 333 gpio-controller; 334 #gpio-cells = <2>; 335 interrupt-controller; 336 #interrupt-cells = <2>; 337 #access-controller-cells = <1>; 338 reg = <0x40000 0x400>; 339 clocks = <&rcc CK_BUS_GPIOE>; 340 st,bank-name = "GPIOE"; 341 status = "disabled"; 342 }; 343 344 gpiof: gpio@44290000 { 345 gpio-controller; 346 #gpio-cells = <2>; 347 interrupt-controller; 348 #interrupt-cells = <2>; 349 #access-controller-cells = <1>; 350 reg = <0x50000 0x400>; 351 clocks = <&rcc CK_BUS_GPIOF>; 352 st,bank-name = "GPIOF"; 353 status = "disabled"; 354 }; 355 356 gpiog: gpio@442a0000 { 357 gpio-controller; 358 #gpio-cells = <2>; 359 interrupt-controller; 360 #interrupt-cells = <2>; 361 #access-controller-cells = <1>; 362 reg = <0x60000 0x400>; 363 clocks = <&rcc CK_BUS_GPIOG>; 364 st,bank-name = "GPIOG"; 365 status = "disabled"; 366 }; 367 368 gpioh: gpio@442b0000 { 369 gpio-controller; 370 #gpio-cells = <2>; 371 interrupt-controller; 372 #interrupt-cells = <2>; 373 #access-controller-cells = <1>; 374 reg = <0x70000 0x400>; 375 clocks = <&rcc CK_BUS_GPIOH>; 376 st,bank-name = "GPIOH"; 377 status = "disabled"; 378 }; 379 380 gpioi: gpio@442c0000 { 381 gpio-controller; 382 #gpio-cells = <2>; 383 interrupt-controller; 384 #interrupt-cells = <2>; 385 #access-controller-cells = <1>; 386 reg = <0x80000 0x400>; 387 clocks = <&rcc CK_BUS_GPIOI>; 388 st,bank-name = "GPIOI"; 389 status = "disabled"; 390 }; 391 392 gpioj: gpio@442d0000 { 393 gpio-controller; 394 #gpio-cells = <2>; 395 interrupt-controller; 396 #interrupt-cells = <2>; 397 #access-controller-cells = <1>; 398 reg = <0x90000 0x400>; 399 clocks = <&rcc CK_BUS_GPIOJ>; 400 st,bank-name = "GPIOJ"; 401 status = "disabled"; 402 }; 403 404 gpiok: gpio@442e0000 { 405 gpio-controller; 406 #gpio-cells = <2>; 407 interrupt-controller; 408 #interrupt-cells = <2>; 409 #access-controller-cells = <1>; 410 reg = <0xa0000 0x400>; 411 clocks = <&rcc CK_BUS_GPIOK>; 412 st,bank-name = "GPIOK"; 413 status = "disabled"; 414 }; 415 }; 416 417 tamp: tamp@46010000 { 418 compatible = "st,stm32mp25-tamp"; 419 reg = <0x46010000 0x400>; 420 clocks = <&rcc CK_BUS_RTC>; 421 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 422 #address-cells = <1>; 423 #size-cells = <1>; 424 ranges; 425 st,backup-zones = <24 24 24 24 12 12 8>; 426 }; 427 428 pinctrl_z: pinctrl-z@46200000 { 429 #address-cells = <1>; 430 #size-cells = <1>; 431 compatible = "st,stm32mp257-z-pinctrl"; 432 ranges = <0 0x46200000 0x400>; 433 pins-are-numbered; 434 435 gpioz: gpio@46200000 { 436 gpio-controller; 437 #gpio-cells = <2>; 438 interrupt-controller; 439 #interrupt-cells = <2>; 440 #access-controller-cells = <1>; 441 reg = <0 0x400>; 442 clocks = <&rcc CK_BUS_GPIOZ>; 443 st,bank-name = "GPIOZ"; 444 st,bank-ioport = <11>; 445 status = "disabled"; 446 }; 447 }; 448 449 hsem: hwspinlock@46240000 { 450 compatible = "st,stm32mp25-hsem"; 451 reg = <0x46240000 0x400>; 452 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 453 clocks = <&rcc CK_BUS_HSEM>; 454 status = "disabled"; 455 }; 456 457 ipcc2: mailbox@46250000 { 458 compatible = "st,stm32mp25-ipcc"; 459 reg = <0x46250000 0x400>; 460 clocks = <&rcc CK_BUS_IPCC2>; 461 status = "disabled"; 462 }; 463 464 fmc: memory-controller@48200000 { 465 #address-cells = <2>; 466 #size-cells = <1>; 467 compatible = "st,stm32mp25-fmc2-ebi"; 468 reg = <0x48200000 0x400>; 469 clocks = <&rcc CK_KER_FMC>; 470 resets = <&rcc FMC_R>; 471 status = "disabled"; 472 473 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 474 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 475 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 476 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 477 <4 0 0x80000000 0x10000000>; /* NAND */ 478 }; 479 }; 480}; 481