1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2023-2025 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/clock/st,stm32mp25-rcc.h> 8#include <dt-bindings/firewall/stm32mp25-rif.h> 9#include <dt-bindings/firewall/stm32mp25-rifsc.h> 10#include <dt-bindings/firewall/stm32mp25-risaf.h> 11#include <dt-bindings/firewall/stm32mp25-risab.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/st,stm32mp25-rcc.h> 14 15/ { 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@0 { 24 compatible = "arm,cortex-a35"; 25 device_type = "cpu"; 26 reg = <0>; 27 enable-method = "psci"; 28 }; 29 }; 30 31 psci { 32 compatible = "arm,psci-1.0"; 33 method = "smc"; 34 }; 35 36 intc: interrupt-controller@4ac00000 { 37 compatible = "arm,cortex-a7-gic"; 38 #interrupt-cells = <3>; 39 interrupt-controller; 40 reg = <0x0 0x4ac10000 0x0 0x1000>, 41 <0x0 0x4ac20000 0x0 0x2000>, 42 <0x0 0x4ac40000 0x0 0x2000>, 43 <0x0 0x4ac60000 0x0 0x2000>; 44 #address-cells = <1>; 45 }; 46 47 clocks { 48 clk_hse: clk-hse { 49 #clock-cells = <0>; 50 compatible = "fixed-clock"; 51 clock-frequency = <24000000>; 52 }; 53 54 clk_hsi: clk-hsi { 55 #clock-cells = <0>; 56 compatible = "fixed-clock"; 57 clock-frequency = <64000000>; 58 }; 59 60 clk_lse: clk-lse { 61 #clock-cells = <0>; 62 compatible = "fixed-clock"; 63 clock-frequency = <32768>; 64 }; 65 66 clk_lsi: clk-lsi { 67 #clock-cells = <0>; 68 compatible = "fixed-clock"; 69 clock-frequency = <32000>; 70 }; 71 72 clk_msi: clk-msi { 73 #clock-cells = <0>; 74 compatible = "fixed-clock"; 75 clock-frequency = <4000000>; 76 }; 77 78 clk_i2sin: clk-i2sin { 79 #clock-cells = <0>; 80 compatible = "fixed-clock"; 81 clock-frequency = <0>; 82 }; 83 84 clk_rcbsec: clk-rcbsec { 85 #clock-cells = <0>; 86 compatible = "fixed-clock"; 87 clock-frequency = <64000000>; 88 }; 89 }; 90 91 soc@0 { 92 compatible = "simple-bus"; 93 #address-cells = <1>; 94 #size-cells = <1>; 95 interrupt-parent = <&intc>; 96 ranges = <0x0 0x0 0x0 0x80000000>; 97 98 hpdma1: dma-controller@40400000 { 99 compatible = "st,stm32-dma3"; 100 reg = <0x40400000 0x1000>; 101 clocks = <&rcc CK_BUS_HPDMA1>; 102 resets = <&rcc HPDMA1_R>; 103 #dma-cells = <4>; 104 status = "disabled"; 105 }; 106 107 hpdma2: dma-controller@40410000 { 108 compatible = "st,stm32-dma3"; 109 reg = <0x40410000 0x1000>; 110 clocks = <&rcc CK_BUS_HPDMA2>; 111 resets = <&rcc HPDMA2_R>; 112 #dma-cells = <4>; 113 status = "disabled"; 114 }; 115 116 hpdma3: dma-controller@40420000 { 117 compatible = "st,stm32-dma3"; 118 reg = <0x40420000 0x1000>; 119 clocks = <&rcc CK_BUS_HPDMA3>; 120 resets = <&rcc HPDMA3_R>; 121 #dma-cells = <4>; 122 status = "disabled"; 123 }; 124 125 ipcc1: mailbox@40490000 { 126 compatible = "st,stm32mp25-ipcc"; 127 reg = <0x40490000 0x400>; 128 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 129 interrupt-names = "rx"; 130 clocks = <&rcc CK_BUS_IPCC1>; 131 status = "disabled"; 132 }; 133 134 ommanager: ommanager@40500000 { 135 compatible = "st,stm32mp25-omm"; 136 reg = <0x40500000 0x400>, <0x60000000 0x10000000>; 137 reg-names = "regs", "memory_map"; 138 ranges = <0 0 0x40430000 0x400>, 139 <1 0 0x40440000 0x400>; 140 clocks = <&rcc CK_BUS_OSPIIOM>; 141 resets = <&rcc OSPIIOM_R>; 142 #address-cells = <2>; 143 #size-cells = <1>; 144 st,syscfg-amcr = <&syscfg 0x2c00 0x7>; 145 status = "disabled"; 146 147 ospi1: spi@0 { 148 compatible = "st,stm32mp25-ospi"; 149 reg = <0 0 0x400>; 150 clocks = <&rcc CK_KER_OSPI1>; 151 resets = <&rcc OSPI1_R>, <&rcc OSPI1DLL_R>; 152 status = "disabled"; 153 }; 154 155 ospi2: spi@1 { 156 compatible = "st,stm32mp25-ospi"; 157 reg = <1 0 0x400>; 158 clocks = <&rcc CK_KER_OSPI2>; 159 resets = <&rcc OSPI2_R>, <&rcc OSPI2DLL_R>; 160 status = "disabled"; 161 }; 162 }; 163 164 rifsc: rifsc@42080000 { 165 compatible = "st,stm32mp25-rifsc", "simple-bus"; 166 reg = <0x42080000 0x1000>; 167 #address-cells = <1>; 168 #size-cells = <1>; 169 #access-controller-cells = <1>; 170 171 usart2: serial@400e0000 { 172 compatible = "st,stm32h7-uart"; 173 reg = <0x400e0000 0x400>; 174 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 175 clocks = <&rcc CK_KER_USART2>; 176 access-controllers = <&rifsc STM32MP25_RIFSC_USART2_ID>; 177 status = "disabled"; 178 }; 179 180 rng: rng@42020000 { 181 compatible = "st,stm32mp25-rng"; 182 reg = <0x42020000 0x400>; 183 clocks = <&clk_rcbsec>, <&rcc CK_BUS_RNG>; 184 clock-names = "rng_clk", "rng_hclk"; 185 resets = <&rcc RNG_R>; 186 access-controllers = <&rifsc STM32MP25_RIFSC_RNG_ID>; 187 }; 188 }; 189 190 iac: iac@42090000 { 191 compatible = "st,stm32mp25-iac"; 192 reg = <0x42090000 0x400>; 193 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 194 }; 195 196 risaf1: risaf@420a0000 { 197 compatible = "st,stm32mp25-risaf"; 198 reg = <0x420a0000 0x1000>; 199 clocks = <&rcc CK_BUS_BKPSRAM>; 200 st,mem-map = <0x0 0x42000000 0x0 0x2000>; 201 #access-controller-cells = <1>; 202 }; 203 204 risaf2: risaf@420b0000 { 205 compatible = "st,stm32mp25-risaf"; 206 reg = <0x420b0000 0x1000>; 207 clocks = <&rcc CK_KER_OSPI1>; 208 st,mem-map = <0x0 0x60000000 0x0 0x10000000>; 209 #access-controller-cells = <1>; 210 status = "disabled"; 211 }; 212 213 risaf4: risaf@420d0000 { 214 compatible = "st,stm32mp25-risaf-enc"; 215 reg = <0x420d0000 0x1000>; 216 clocks = <&rcc CK_BUS_RISAF4>; 217 st,mem-map = <0x0 0x80000000 0x1 0x00000000>; 218 #access-controller-cells = <1>; 219 }; 220 221 risaf5: risaf@420e0000 { 222 compatible = "st,stm32mp25-risaf"; 223 reg = <0x420e0000 0x1000>; 224 clocks = <&rcc CK_BUS_PCIE>; 225 st,mem-map = <0x0 0x10000000 0x0 0x10000000>; 226 #access-controller-cells = <1>; 227 status = "disabled"; 228 }; 229 230 risab1: risab@420f0000 { 231 compatible = "st,stm32mp25-risab"; 232 reg = <0x420f0000 0x1000>; 233 clocks = <&rcc CK_ICN_LS_MCU>; 234 st,mem-map = <0xa000000 0x20000>; 235 #access-controller-cells = <1>; 236 }; 237 238 risab2: risab@42100000 { 239 compatible = "st,stm32mp25-risab"; 240 reg = <0x42100000 0x1000>; 241 clocks = <&rcc CK_ICN_LS_MCU>; 242 st,mem-map = <0xa020000 0x20000>; 243 #access-controller-cells = <1>; 244 }; 245 246 risab3: risab@42110000 { 247 compatible = "st,stm32mp25-risab"; 248 reg = <0x42110000 0x1000>; 249 clocks = <&rcc CK_ICN_LS_MCU>; 250 st,mem-map = <0xa040000 0x20000>; 251 #access-controller-cells = <1>; 252 }; 253 254 risab4: risab@42120000 { 255 compatible = "st,stm32mp25-risab"; 256 reg = <0x42120000 0x1000>; 257 clocks = <&rcc CK_ICN_LS_MCU>; 258 st,mem-map = <0xa060000 0x20000>; 259 #access-controller-cells = <1>; 260 }; 261 262 risab5: risab@42130000 { 263 compatible = "st,stm32mp25-risab"; 264 reg = <0x42130000 0x1000>; 265 clocks = <&rcc CK_ICN_LS_MCU>; 266 st,mem-map = <0xa080000 0x20000>; 267 #access-controller-cells = <1>; 268 }; 269 270 risab6: risab@42140000 { 271 compatible = "st,stm32mp25-risab"; 272 reg = <0x42140000 0x1000>; 273 clocks = <&rcc CK_ICN_LS_MCU>; 274 st,mem-map = <0xa0a0000 0x20000>; 275 #access-controller-cells = <1>; 276 status = "disabled"; 277 }; 278 279 serc: serc@44080000 { 280 compatible = "st,stm32mp25-serc"; 281 reg = <0x44080000 0x1000>; 282 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 283 clocks = <&rcc CK_BUS_SERC>; 284 }; 285 286 rcc: rcc@44200000 { 287 compatible = "st,stm32mp25-rcc", "syscon"; 288 reg = <0x44200000 0x10000>; 289 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 290 291 #clock-cells = <1>; 292 #reset-cells = <1>; 293 clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>, 294 <&clk_lsi>, <&clk_msi>, <&clk_i2sin>; 295 clock-names = "clk-hse", "clk-hsi", "clk-lse", 296 "clk-lsi", "clk-msi", "clk-i2sin"; 297 298 hsi_calibration: hsi-calibration { 299 compatible = "st,hsi-cal"; 300 st,cal_hsi_dev = <31>; 301 st,cal_hsi_ref = <1953>; 302 status = "disabled"; 303 }; 304 305 msi_calibration: msi-calibration { 306 compatible = "st,msi-cal"; 307 status = "disabled"; 308 }; 309 }; 310 311 exti1: interrupt-controller@44220000 { 312 compatible = "st,stm32mp1-exti"; 313 interrupt-controller; 314 #interrupt-cells = <2>; 315 reg = <0x44220000 0x400>; 316 interrupts-extended = 317 <&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 318 <&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 319 <&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 320 <&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 321 <&intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 322 <&intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 323 <&intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 324 <&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 325 <&intc GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 326 <&intc GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 327 <&intc GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 328 <&intc GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 329 <&intc GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 330 <&intc GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 331 <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 332 <&intc GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 333 <&intc GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 334 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 335 <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 336 <&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 337 <0>, /* EXTI_20 */ 338 <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 339 <&intc GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 340 <&intc GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 341 <&intc GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 342 <&intc GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 343 <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 344 <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 345 <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 346 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 347 <&intc GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 348 <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 349 <&intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 350 <&intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 351 <&intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 352 <0>, 353 <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 354 <&intc GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 355 <&intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 356 <&intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 357 <&intc GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ 358 <&intc GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 359 <&intc GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 360 <&intc GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 361 <&intc GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 362 <&intc GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 363 <&intc GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 364 <&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 365 <&intc GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 366 <&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 367 <&intc GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 368 <0>, 369 <0>, 370 <0>, 371 <0>, 372 <0>, 373 <0>, 374 <0>, 375 <0>, 376 <&intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 377 <0>, /* EXTI_60 */ 378 <&intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 379 <0>, 380 <0>, 381 <&intc GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 382 <0>, 383 <0>, 384 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 385 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 386 <0>, 387 <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ 388 <0>, 389 <&intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 390 <&intc GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 391 <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 392 <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 393 <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 394 <&intc GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 395 <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 396 <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 397 <0>, /* EXTI_80 */ 398 <0>, 399 <0>, 400 <&intc GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 401 <&intc GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 402 }; 403 404 syscfg: syscon@44230000 { 405 reg = <0x44230000 0x10000>; 406 status = "disabled"; 407 }; 408 409 pinctrl: pinctrl@44240000 { 410 #address-cells = <1>; 411 #size-cells = <1>; 412 compatible = "st,stm32mp257-pinctrl"; 413 ranges = <0 0x44240000 0xa0400>; 414 pins-are-numbered; 415 416 gpioa: gpio@44240000 { 417 gpio-controller; 418 #gpio-cells = <2>; 419 interrupt-controller; 420 #interrupt-cells = <2>; 421 #access-controller-cells = <1>; 422 reg = <0x0 0x400>; 423 clocks = <&rcc CK_BUS_GPIOA>; 424 st,bank-name = "GPIOA"; 425 status = "disabled"; 426 }; 427 428 gpiob: gpio@44250000 { 429 gpio-controller; 430 #gpio-cells = <2>; 431 interrupt-controller; 432 #interrupt-cells = <2>; 433 #access-controller-cells = <1>; 434 reg = <0x10000 0x400>; 435 clocks = <&rcc CK_BUS_GPIOB>; 436 st,bank-name = "GPIOB"; 437 status = "disabled"; 438 }; 439 440 gpioc: gpio@44260000 { 441 gpio-controller; 442 #gpio-cells = <2>; 443 interrupt-controller; 444 #interrupt-cells = <2>; 445 #access-controller-cells = <1>; 446 reg = <0x20000 0x400>; 447 clocks = <&rcc CK_BUS_GPIOC>; 448 st,bank-name = "GPIOC"; 449 status = "disabled"; 450 }; 451 452 gpiod: gpio@44270000 { 453 gpio-controller; 454 #gpio-cells = <2>; 455 interrupt-controller; 456 #interrupt-cells = <2>; 457 #access-controller-cells = <1>; 458 reg = <0x30000 0x400>; 459 clocks = <&rcc CK_BUS_GPIOD>; 460 st,bank-name = "GPIOD"; 461 status = "disabled"; 462 }; 463 464 gpioe: gpio@44280000 { 465 gpio-controller; 466 #gpio-cells = <2>; 467 interrupt-controller; 468 #interrupt-cells = <2>; 469 #access-controller-cells = <1>; 470 reg = <0x40000 0x400>; 471 clocks = <&rcc CK_BUS_GPIOE>; 472 st,bank-name = "GPIOE"; 473 status = "disabled"; 474 }; 475 476 gpiof: gpio@44290000 { 477 gpio-controller; 478 #gpio-cells = <2>; 479 interrupt-controller; 480 #interrupt-cells = <2>; 481 #access-controller-cells = <1>; 482 reg = <0x50000 0x400>; 483 clocks = <&rcc CK_BUS_GPIOF>; 484 st,bank-name = "GPIOF"; 485 status = "disabled"; 486 }; 487 488 gpiog: gpio@442a0000 { 489 gpio-controller; 490 #gpio-cells = <2>; 491 interrupt-controller; 492 #interrupt-cells = <2>; 493 #access-controller-cells = <1>; 494 reg = <0x60000 0x400>; 495 clocks = <&rcc CK_BUS_GPIOG>; 496 st,bank-name = "GPIOG"; 497 status = "disabled"; 498 }; 499 500 gpioh: gpio@442b0000 { 501 gpio-controller; 502 #gpio-cells = <2>; 503 interrupt-controller; 504 #interrupt-cells = <2>; 505 #access-controller-cells = <1>; 506 reg = <0x70000 0x400>; 507 clocks = <&rcc CK_BUS_GPIOH>; 508 st,bank-name = "GPIOH"; 509 status = "disabled"; 510 }; 511 512 gpioi: gpio@442c0000 { 513 gpio-controller; 514 #gpio-cells = <2>; 515 interrupt-controller; 516 #interrupt-cells = <2>; 517 #access-controller-cells = <1>; 518 reg = <0x80000 0x400>; 519 clocks = <&rcc CK_BUS_GPIOI>; 520 st,bank-name = "GPIOI"; 521 status = "disabled"; 522 }; 523 524 gpioj: gpio@442d0000 { 525 gpio-controller; 526 #gpio-cells = <2>; 527 interrupt-controller; 528 #interrupt-cells = <2>; 529 #access-controller-cells = <1>; 530 reg = <0x90000 0x400>; 531 clocks = <&rcc CK_BUS_GPIOJ>; 532 st,bank-name = "GPIOJ"; 533 status = "disabled"; 534 }; 535 536 gpiok: gpio@442e0000 { 537 gpio-controller; 538 #gpio-cells = <2>; 539 interrupt-controller; 540 #interrupt-cells = <2>; 541 #access-controller-cells = <1>; 542 reg = <0xa0000 0x400>; 543 clocks = <&rcc CK_BUS_GPIOK>; 544 st,bank-name = "GPIOK"; 545 status = "disabled"; 546 }; 547 }; 548 549 rtc: rtc@46000000 { 550 compatible = "st,stm32mp25-rtc"; 551 reg = <0x46000000 0x400>; 552 clocks = <&rcc CK_BUS_RTC>, <&rcc RTC_CK>; 553 clock-names = "pclk", "rtc_ck"; 554 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 555 }; 556 557 tamp: tamp@46010000 { 558 compatible = "st,stm32mp25-tamp"; 559 reg = <0x46010000 0x400>; 560 clocks = <&rcc CK_BUS_RTC>; 561 interrupts-extended = <&exti2 21 IRQ_TYPE_EDGE_RISING>; 562 #address-cells = <1>; 563 #size-cells = <1>; 564 ranges; 565 st,backup-zones = <24 24 24 24 12 12 8>; 566 }; 567 568 pinctrl_z: pinctrl-z@46200000 { 569 #address-cells = <1>; 570 #size-cells = <1>; 571 compatible = "st,stm32mp257-z-pinctrl"; 572 ranges = <0 0x46200000 0x400>; 573 pins-are-numbered; 574 575 gpioz: gpio@46200000 { 576 gpio-controller; 577 #gpio-cells = <2>; 578 interrupt-controller; 579 #interrupt-cells = <2>; 580 #access-controller-cells = <1>; 581 reg = <0 0x400>; 582 clocks = <&rcc CK_BUS_GPIOZ>; 583 st,bank-name = "GPIOZ"; 584 st,bank-ioport = <11>; 585 status = "disabled"; 586 }; 587 }; 588 589 exti2: interrupt-controller@46230000 { 590 compatible = "st,stm32mp1-exti"; 591 interrupt-controller; 592 #interrupt-cells = <2>; 593 reg = <0x46230000 0x400>; 594 interrupts-extended = 595 <&intc GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 596 <&intc GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 597 <&intc GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 598 <&intc GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 599 <&intc GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 600 <&intc GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 601 <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 602 <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 603 <&intc GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 604 <&intc GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 605 <&intc GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 606 <&intc GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 607 <&intc GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 608 <&intc GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 609 <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 610 <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 611 <&intc GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 612 <&intc GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 613 <0>, 614 <0>, 615 <0>, /* EXTI_20 */ 616 <&intc GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 617 <&intc GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 618 <0>, 619 <0>, 620 <&intc GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 621 <&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 622 <&intc GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 623 <0>, 624 <&intc GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 625 <&intc GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 626 <&intc GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 627 <0>, 628 <&intc GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 629 <&intc GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 630 <0>, 631 <0>, 632 <&intc GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 633 <0>, 634 <0>, 635 <&intc GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ 636 <0>, 637 <0>, 638 <&intc GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 639 <0>, 640 <0>, 641 <&intc GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 642 <0>, 643 <&intc GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 644 <&intc GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 645 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 646 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 647 <&intc GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 648 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 649 <0>, 650 <0>, 651 <0>, 652 <0>, 653 <0>, 654 <0>, 655 <0>, /* EXTI_60 */ 656 <&intc GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 657 <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 658 <0>, 659 <&intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 660 <&intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 661 <&intc GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 662 <&intc GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 663 <0>, 664 <0>, 665 <&intc GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ 666 }; 667 668 hsem: hwspinlock@46240000 { 669 compatible = "st,stm32mp25-hsem"; 670 reg = <0x46240000 0x400>; 671 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 672 clocks = <&rcc CK_BUS_HSEM>; 673 status = "disabled"; 674 }; 675 676 ipcc2: mailbox@46250000 { 677 compatible = "st,stm32mp25-ipcc"; 678 reg = <0x46250000 0x400>; 679 clocks = <&rcc CK_BUS_IPCC2>; 680 status = "disabled"; 681 }; 682 683 stgenc: stgen@48080000 { 684 compatible = "st,stm32mp25-stgen"; 685 reg = <0x48080000 0x1000>; 686 clocks = <&rcc CK_BUS_STGEN>, <&rcc CK_KER_STGEN>; 687 clock-names = "bus", "stgen_clk"; 688 }; 689 690 fmc: memory-controller@48200000 { 691 #address-cells = <2>; 692 #size-cells = <1>; 693 compatible = "st,stm32mp25-fmc2-ebi"; 694 reg = <0x48200000 0x400>; 695 clocks = <&rcc CK_KER_FMC>; 696 resets = <&rcc FMC_R>; 697 status = "disabled"; 698 699 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 700 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 701 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 702 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 703 <4 0 0x80000000 0x10000000>; /* NAND */ 704 }; 705 }; 706}; 707