1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8 9/ { 10 #address-cells = <2>; 11 #size-cells = <2>; 12 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu0: cpu@0 { 18 compatible = "arm,cortex-a35"; 19 device_type = "cpu"; 20 reg = <0>; 21 enable-method = "psci"; 22 }; 23 }; 24 25 psci { 26 compatible = "arm,psci-1.0"; 27 method = "smc"; 28 }; 29 30 intc: interrupt-controller@4ac00000 { 31 compatible = "arm,cortex-a7-gic"; 32 #interrupt-cells = <3>; 33 interrupt-controller; 34 reg = <0x0 0x4ac10000 0x0 0x1000>, 35 <0x0 0x4ac20000 0x0 0x2000>, 36 <0x0 0x4ac40000 0x0 0x2000>, 37 <0x0 0x4ac60000 0x0 0x2000>; 38 #address-cells = <1>; 39 }; 40 41 clocks { 42 clk_hse: clk-hse { 43 #clock-cells = <0>; 44 compatible = "fixed-clock"; 45 clock-frequency = <24000000>; 46 }; 47 48 clk_hsi: clk-hsi { 49 #clock-cells = <0>; 50 compatible = "fixed-clock"; 51 clock-frequency = <64000000>; 52 }; 53 54 clk_lse: clk-lse { 55 #clock-cells = <0>; 56 compatible = "fixed-clock"; 57 clock-frequency = <32768>; 58 }; 59 60 clk_lsi: clk-lsi { 61 #clock-cells = <0>; 62 compatible = "fixed-clock"; 63 clock-frequency = <32000>; 64 }; 65 66 clk_msi: clk-msi { 67 #clock-cells = <0>; 68 compatible = "fixed-clock"; 69 clock-frequency = <4000000>; 70 }; 71 72 clk_i2sin: clk-i2sin { 73 #clock-cells = <0>; 74 compatible = "fixed-clock"; 75 clock-frequency = <0>; 76 }; 77 78 clocks { 79 clk_rcbsec: clk-rcbsec { 80 #clock-cells = <0>; 81 compatible = "fixed-clock"; 82 clock-frequency = <64000000>; 83 }; 84 }; 85 }; 86 87 soc@0 { 88 compatible = "simple-bus"; 89 #address-cells = <1>; 90 #size-cells = <1>; 91 interrupt-parent = <&intc>; 92 ranges = <0x0 0x0 0x0 0x80000000>; 93 94 hpdma1: dma-controller@40400000 { 95 compatible = "st,stm32-dma3"; 96 reg = <0x40400000 0x1000>; 97 #dma-cells = <4>; 98 status = "disabled"; 99 }; 100 101 hpdma2: dma-controller@40410000 { 102 compatible = "st,stm32-dma3"; 103 reg = <0x40410000 0x1000>; 104 #dma-cells = <4>; 105 status = "disabled"; 106 }; 107 108 hpdma3: dma-controller@40420000 { 109 compatible = "st,stm32-dma3"; 110 reg = <0x40420000 0x1000>; 111 #dma-cells = <4>; 112 status = "disabled"; 113 }; 114 115 ipcc1: mailbox@40490000 { 116 compatible = "st,stm32mp25-ipcc"; 117 reg = <0x40490000 0x400>; 118 status = "disabled"; 119 }; 120 121 rifsc: rifsc@42080000 { 122 compatible = "st,stm32mp25-rifsc"; 123 reg = <0x42080000 0x1000>; 124 #address-cells = <1>; 125 #size-cells = <1>; 126 127 usart2: serial@400e0000 { 128 reg = <0x400e0000 0x400>; 129 status = "disabled"; 130 }; 131 }; 132 133 pinctrl: pinctrl@44240000 { 134 #address-cells = <1>; 135 #size-cells = <1>; 136 compatible = "st,stm32mp257-pinctrl"; 137 ranges = <0 0x44240000 0xa0400>; 138 pins-are-numbered; 139 140 gpioa: gpio@44240000 { 141 gpio-controller; 142 #gpio-cells = <2>; 143 interrupt-controller; 144 #interrupt-cells = <2>; 145 reg = <0x0 0x400>; 146 st,bank-name = "GPIOA"; 147 status = "disabled"; 148 }; 149 150 gpiob: gpio@44250000 { 151 gpio-controller; 152 #gpio-cells = <2>; 153 interrupt-controller; 154 #interrupt-cells = <2>; 155 reg = <0x10000 0x400>; 156 st,bank-name = "GPIOB"; 157 status = "disabled"; 158 }; 159 160 gpioc: gpio@44260000 { 161 gpio-controller; 162 #gpio-cells = <2>; 163 interrupt-controller; 164 #interrupt-cells = <2>; 165 reg = <0x20000 0x400>; 166 st,bank-name = "GPIOC"; 167 status = "disabled"; 168 }; 169 170 gpiod: gpio@44270000 { 171 gpio-controller; 172 #gpio-cells = <2>; 173 interrupt-controller; 174 #interrupt-cells = <2>; 175 reg = <0x30000 0x400>; 176 st,bank-name = "GPIOD"; 177 status = "disabled"; 178 }; 179 180 gpioe: gpio@44280000 { 181 gpio-controller; 182 #gpio-cells = <2>; 183 interrupt-controller; 184 #interrupt-cells = <2>; 185 reg = <0x40000 0x400>; 186 st,bank-name = "GPIOE"; 187 status = "disabled"; 188 }; 189 190 gpiof: gpio@44290000 { 191 gpio-controller; 192 #gpio-cells = <2>; 193 interrupt-controller; 194 #interrupt-cells = <2>; 195 reg = <0x50000 0x400>; 196 st,bank-name = "GPIOF"; 197 status = "disabled"; 198 }; 199 200 gpiog: gpio@442a0000 { 201 gpio-controller; 202 #gpio-cells = <2>; 203 interrupt-controller; 204 #interrupt-cells = <2>; 205 reg = <0x60000 0x400>; 206 st,bank-name = "GPIOG"; 207 status = "disabled"; 208 }; 209 210 gpioh: gpio@442b0000 { 211 gpio-controller; 212 #gpio-cells = <2>; 213 interrupt-controller; 214 #interrupt-cells = <2>; 215 reg = <0x70000 0x400>; 216 st,bank-name = "GPIOH"; 217 status = "disabled"; 218 }; 219 220 gpioi: gpio@442c0000 { 221 gpio-controller; 222 #gpio-cells = <2>; 223 interrupt-controller; 224 #interrupt-cells = <2>; 225 reg = <0x80000 0x400>; 226 st,bank-name = "GPIOI"; 227 status = "disabled"; 228 }; 229 230 gpioj: gpio@442d0000 { 231 gpio-controller; 232 #gpio-cells = <2>; 233 interrupt-controller; 234 #interrupt-cells = <2>; 235 reg = <0x90000 0x400>; 236 st,bank-name = "GPIOJ"; 237 status = "disabled"; 238 }; 239 240 gpiok: gpio@442e0000 { 241 gpio-controller; 242 #gpio-cells = <2>; 243 interrupt-controller; 244 #interrupt-cells = <2>; 245 reg = <0xa0000 0x400>; 246 st,bank-name = "GPIOK"; 247 status = "disabled"; 248 }; 249 }; 250 251 pinctrl_z: pinctrl-z@46200000 { 252 #address-cells = <1>; 253 #size-cells = <1>; 254 compatible = "st,stm32mp257-z-pinctrl"; 255 ranges = <0 0x46200000 0x400>; 256 pins-are-numbered; 257 258 gpioz: gpio@46200000 { 259 gpio-controller; 260 #gpio-cells = <2>; 261 interrupt-controller; 262 #interrupt-cells = <2>; 263 reg = <0 0x400>; 264 st,bank-name = "GPIOZ"; 265 st,bank-ioport = <11>; 266 status = "disabled"; 267 }; 268 }; 269 270 hsem: hwspinlock@46240000 { 271 compatible = "st,stm32mp25-hsem"; 272 reg = <0x46240000 0x400>; 273 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 274 status = "disabled"; 275 }; 276 277 ipcc2: mailbox@46250000 { 278 compatible = "st,stm32mp25-ipcc"; 279 reg = <0x46250000 0x400>; 280 status = "disabled"; 281 }; 282 283 fmc: memory-controller@48200000 { 284 #address-cells = <2>; 285 #size-cells = <1>; 286 compatible = "st,stm32mp25-fmc2-ebi"; 287 reg = <0x48200000 0x400>; 288 status = "disabled"; 289 290 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 291 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 292 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 293 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 294 <4 0 0x80000000 0x10000000>; /* NAND */ 295 }; 296 }; 297}; 298