1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/clock/st,stm32mp25-rcc.h> 8#include <dt-bindings/firewall/stm32mp25-rifsc.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/reset/st,stm32mp25-rcc.h> 11 12/ { 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu0: cpu@0 { 21 compatible = "arm,cortex-a35"; 22 device_type = "cpu"; 23 reg = <0>; 24 enable-method = "psci"; 25 }; 26 }; 27 28 psci { 29 compatible = "arm,psci-1.0"; 30 method = "smc"; 31 }; 32 33 intc: interrupt-controller@4ac00000 { 34 compatible = "arm,cortex-a7-gic"; 35 #interrupt-cells = <3>; 36 interrupt-controller; 37 reg = <0x0 0x4ac10000 0x0 0x1000>, 38 <0x0 0x4ac20000 0x0 0x2000>, 39 <0x0 0x4ac40000 0x0 0x2000>, 40 <0x0 0x4ac60000 0x0 0x2000>; 41 #address-cells = <1>; 42 }; 43 44 clocks { 45 clk_hse: clk-hse { 46 #clock-cells = <0>; 47 compatible = "fixed-clock"; 48 clock-frequency = <24000000>; 49 }; 50 51 clk_hsi: clk-hsi { 52 #clock-cells = <0>; 53 compatible = "fixed-clock"; 54 clock-frequency = <64000000>; 55 }; 56 57 clk_lse: clk-lse { 58 #clock-cells = <0>; 59 compatible = "fixed-clock"; 60 clock-frequency = <32768>; 61 }; 62 63 clk_lsi: clk-lsi { 64 #clock-cells = <0>; 65 compatible = "fixed-clock"; 66 clock-frequency = <32000>; 67 }; 68 69 clk_msi: clk-msi { 70 #clock-cells = <0>; 71 compatible = "fixed-clock"; 72 clock-frequency = <4000000>; 73 }; 74 75 clk_i2sin: clk-i2sin { 76 #clock-cells = <0>; 77 compatible = "fixed-clock"; 78 clock-frequency = <0>; 79 }; 80 81 clk_rcbsec: clk-rcbsec { 82 #clock-cells = <0>; 83 compatible = "fixed-clock"; 84 clock-frequency = <64000000>; 85 }; 86 }; 87 88 soc@0 { 89 compatible = "simple-bus"; 90 #address-cells = <1>; 91 #size-cells = <1>; 92 interrupt-parent = <&intc>; 93 ranges = <0x0 0x0 0x0 0x80000000>; 94 95 hpdma1: dma-controller@40400000 { 96 compatible = "st,stm32-dma3"; 97 reg = <0x40400000 0x1000>; 98 #dma-cells = <4>; 99 status = "disabled"; 100 }; 101 102 hpdma2: dma-controller@40410000 { 103 compatible = "st,stm32-dma3"; 104 reg = <0x40410000 0x1000>; 105 #dma-cells = <4>; 106 status = "disabled"; 107 }; 108 109 hpdma3: dma-controller@40420000 { 110 compatible = "st,stm32-dma3"; 111 reg = <0x40420000 0x1000>; 112 #dma-cells = <4>; 113 status = "disabled"; 114 }; 115 116 ipcc1: mailbox@40490000 { 117 compatible = "st,stm32mp25-ipcc"; 118 reg = <0x40490000 0x400>; 119 status = "disabled"; 120 }; 121 122 rifsc: rifsc@42080000 { 123 compatible = "st,stm32mp25-rifsc", "simple-bus"; 124 reg = <0x42080000 0x1000>; 125 #address-cells = <1>; 126 #size-cells = <1>; 127 #access-controller-cells = <1>; 128 129 usart2: serial@400e0000 { 130 compatible = "st,stm32h7-uart"; 131 reg = <0x400e0000 0x400>; 132 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 133 clocks = <&rcc CK_KER_USART2>; 134 access-controllers = <&rifsc STM32MP25_RIFSC_USART2_ID>; 135 status = "disabled"; 136 }; 137 138 rng: rng@42020000 { 139 compatible = "st,stm32mp25-rng"; 140 reg = <0x42020000 0x400>; 141 clocks = <&clk_rcbsec>, <&rcc CK_BUS_RNG>; 142 clock-names = "rng_clk", "rng_hclk"; 143 resets = <&rcc RNG_R>; 144 access-controllers = <&rifsc STM32MP25_RIFSC_RNG_ID>; 145 }; 146 }; 147 148 iac: iac@42090000 { 149 compatible = "st,stm32mp25-iac"; 150 reg = <0x42090000 0x400>; 151 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 152 }; 153 154 risaf1: risaf@420a0000 { 155 compatible = "st,stm32mp25-risaf"; 156 reg = <0x420a0000 0x1000>; 157 clocks = <&rcc CK_BUS_BKPSRAM>; 158 st,mem-map = <0x0 0x42000000 0x0 0x2000>; 159 }; 160 161 risaf2: risaf@420b0000 { 162 compatible = "st,stm32mp25-risaf"; 163 reg = <0x420b0000 0x1000>; 164 clocks = <&rcc CK_KER_OSPI1>; 165 st,mem-map = <0x0 0x60000000 0x0 0x10000000>; 166 status = "disabled"; 167 }; 168 169 risaf4: risaf@420d0000 { 170 compatible = "st,stm32mp25-risaf-enc"; 171 reg = <0x420d0000 0x1000>; 172 clocks = <&rcc CK_BUS_RISAF4>; 173 st,mem-map = <0x0 0x80000000 0x1 0x00000000>; 174 }; 175 176 risaf5: risaf@420e0000 { 177 compatible = "st,stm32mp25-risaf"; 178 reg = <0x420e0000 0x1000>; 179 clocks = <&rcc CK_BUS_PCIE>; 180 st,mem-map = <0x0 0x10000000 0x0 0x10000000>; 181 status = "disabled"; 182 }; 183 184 serc: serc@44080000 { 185 compatible = "st,stm32mp25-serc"; 186 reg = <0x44080000 0x1000>; 187 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 188 clocks = <&rcc CK_BUS_SERC>; 189 }; 190 191 rcc: rcc@44200000 { 192 compatible = "st,stm32mp25-rcc", "syscon"; 193 reg = <0x44200000 0x10000>; 194 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 195 196 #clock-cells = <1>; 197 #reset-cells = <1>; 198 clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>, 199 <&clk_lsi>, <&clk_msi>, <&clk_i2sin>; 200 clock-names = "clk-hse", "clk-hsi", "clk-lse", 201 "clk-lsi", "clk-msi", "clk-i2sin"; 202 203 hsi_calibration: hsi-calibration { 204 compatible = "st,hsi-cal"; 205 st,cal_hsi_dev = <31>; 206 st,cal_hsi_ref = <1953>; 207 status = "disabled"; 208 }; 209 210 msi_calibration: msi-calibration { 211 compatible = "st,msi-cal"; 212 status = "disabled"; 213 }; 214 }; 215 216 pinctrl: pinctrl@44240000 { 217 #address-cells = <1>; 218 #size-cells = <1>; 219 compatible = "st,stm32mp257-pinctrl"; 220 ranges = <0 0x44240000 0xa0400>; 221 pins-are-numbered; 222 223 gpioa: gpio@44240000 { 224 gpio-controller; 225 #gpio-cells = <2>; 226 interrupt-controller; 227 #interrupt-cells = <2>; 228 reg = <0x0 0x400>; 229 clocks = <&rcc CK_BUS_GPIOA>; 230 st,bank-name = "GPIOA"; 231 status = "disabled"; 232 }; 233 234 gpiob: gpio@44250000 { 235 gpio-controller; 236 #gpio-cells = <2>; 237 interrupt-controller; 238 #interrupt-cells = <2>; 239 reg = <0x10000 0x400>; 240 clocks = <&rcc CK_BUS_GPIOB>; 241 st,bank-name = "GPIOB"; 242 status = "disabled"; 243 }; 244 245 gpioc: gpio@44260000 { 246 gpio-controller; 247 #gpio-cells = <2>; 248 interrupt-controller; 249 #interrupt-cells = <2>; 250 reg = <0x20000 0x400>; 251 clocks = <&rcc CK_BUS_GPIOC>; 252 st,bank-name = "GPIOC"; 253 status = "disabled"; 254 }; 255 256 gpiod: gpio@44270000 { 257 gpio-controller; 258 #gpio-cells = <2>; 259 interrupt-controller; 260 #interrupt-cells = <2>; 261 reg = <0x30000 0x400>; 262 clocks = <&rcc CK_BUS_GPIOD>; 263 st,bank-name = "GPIOD"; 264 status = "disabled"; 265 }; 266 267 gpioe: gpio@44280000 { 268 gpio-controller; 269 #gpio-cells = <2>; 270 interrupt-controller; 271 #interrupt-cells = <2>; 272 reg = <0x40000 0x400>; 273 clocks = <&rcc CK_BUS_GPIOE>; 274 st,bank-name = "GPIOE"; 275 status = "disabled"; 276 }; 277 278 gpiof: gpio@44290000 { 279 gpio-controller; 280 #gpio-cells = <2>; 281 interrupt-controller; 282 #interrupt-cells = <2>; 283 reg = <0x50000 0x400>; 284 clocks = <&rcc CK_BUS_GPIOF>; 285 st,bank-name = "GPIOF"; 286 status = "disabled"; 287 }; 288 289 gpiog: gpio@442a0000 { 290 gpio-controller; 291 #gpio-cells = <2>; 292 interrupt-controller; 293 #interrupt-cells = <2>; 294 reg = <0x60000 0x400>; 295 clocks = <&rcc CK_BUS_GPIOG>; 296 st,bank-name = "GPIOG"; 297 status = "disabled"; 298 }; 299 300 gpioh: gpio@442b0000 { 301 gpio-controller; 302 #gpio-cells = <2>; 303 interrupt-controller; 304 #interrupt-cells = <2>; 305 reg = <0x70000 0x400>; 306 clocks = <&rcc CK_BUS_GPIOH>; 307 st,bank-name = "GPIOH"; 308 status = "disabled"; 309 }; 310 311 gpioi: gpio@442c0000 { 312 gpio-controller; 313 #gpio-cells = <2>; 314 interrupt-controller; 315 #interrupt-cells = <2>; 316 reg = <0x80000 0x400>; 317 clocks = <&rcc CK_BUS_GPIOI>; 318 st,bank-name = "GPIOI"; 319 status = "disabled"; 320 }; 321 322 gpioj: gpio@442d0000 { 323 gpio-controller; 324 #gpio-cells = <2>; 325 interrupt-controller; 326 #interrupt-cells = <2>; 327 reg = <0x90000 0x400>; 328 clocks = <&rcc CK_BUS_GPIOJ>; 329 st,bank-name = "GPIOJ"; 330 status = "disabled"; 331 }; 332 333 gpiok: gpio@442e0000 { 334 gpio-controller; 335 #gpio-cells = <2>; 336 interrupt-controller; 337 #interrupt-cells = <2>; 338 reg = <0xa0000 0x400>; 339 clocks = <&rcc CK_BUS_GPIOK>; 340 st,bank-name = "GPIOK"; 341 status = "disabled"; 342 }; 343 }; 344 345 pinctrl_z: pinctrl-z@46200000 { 346 #address-cells = <1>; 347 #size-cells = <1>; 348 compatible = "st,stm32mp257-z-pinctrl"; 349 ranges = <0 0x46200000 0x400>; 350 pins-are-numbered; 351 352 gpioz: gpio@46200000 { 353 gpio-controller; 354 #gpio-cells = <2>; 355 interrupt-controller; 356 #interrupt-cells = <2>; 357 reg = <0 0x400>; 358 clocks = <&rcc CK_BUS_GPIOZ>; 359 st,bank-name = "GPIOZ"; 360 st,bank-ioport = <11>; 361 status = "disabled"; 362 }; 363 }; 364 365 hsem: hwspinlock@46240000 { 366 compatible = "st,stm32mp25-hsem"; 367 reg = <0x46240000 0x400>; 368 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 369 status = "disabled"; 370 }; 371 372 ipcc2: mailbox@46250000 { 373 compatible = "st,stm32mp25-ipcc"; 374 reg = <0x46250000 0x400>; 375 status = "disabled"; 376 }; 377 378 fmc: memory-controller@48200000 { 379 #address-cells = <2>; 380 #size-cells = <1>; 381 compatible = "st,stm32mp25-fmc2-ebi"; 382 reg = <0x48200000 0x400>; 383 status = "disabled"; 384 385 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 386 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 387 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 388 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 389 <4 0 0x80000000 0x10000000>; /* NAND */ 390 }; 391 }; 392}; 393