1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8 9/ { 10 #address-cells = <2>; 11 #size-cells = <2>; 12 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu0: cpu@0 { 18 compatible = "arm,cortex-a35"; 19 device_type = "cpu"; 20 reg = <0>; 21 enable-method = "psci"; 22 }; 23 }; 24 25 psci { 26 compatible = "arm,psci-1.0"; 27 method = "smc"; 28 }; 29 30 intc: interrupt-controller@4ac00000 { 31 compatible = "arm,cortex-a7-gic"; 32 #interrupt-cells = <3>; 33 interrupt-controller; 34 reg = <0x0 0x4ac10000 0x0 0x1000>, 35 <0x0 0x4ac20000 0x0 0x2000>, 36 <0x0 0x4ac40000 0x0 0x2000>, 37 <0x0 0x4ac60000 0x0 0x2000>; 38 #address-cells = <1>; 39 }; 40 41 clocks { 42 clk_hse: clk-hse { 43 #clock-cells = <0>; 44 compatible = "fixed-clock"; 45 clock-frequency = <24000000>; 46 }; 47 48 clk_hsi: clk-hsi { 49 #clock-cells = <0>; 50 compatible = "fixed-clock"; 51 clock-frequency = <64000000>; 52 }; 53 54 clk_lse: clk-lse { 55 #clock-cells = <0>; 56 compatible = "fixed-clock"; 57 clock-frequency = <32768>; 58 }; 59 60 clk_lsi: clk-lsi { 61 #clock-cells = <0>; 62 compatible = "fixed-clock"; 63 clock-frequency = <32000>; 64 }; 65 66 clk_msi: clk-msi { 67 #clock-cells = <0>; 68 compatible = "fixed-clock"; 69 clock-frequency = <4000000>; 70 }; 71 72 clk_i2sin: clk-i2sin { 73 #clock-cells = <0>; 74 compatible = "fixed-clock"; 75 clock-frequency = <0>; 76 }; 77 78 clocks { 79 clk_rcbsec: clk-rcbsec { 80 #clock-cells = <0>; 81 compatible = "fixed-clock"; 82 clock-frequency = <64000000>; 83 }; 84 }; 85 }; 86 87 soc@0 { 88 compatible = "simple-bus"; 89 #address-cells = <1>; 90 #size-cells = <1>; 91 interrupt-parent = <&intc>; 92 ranges = <0x0 0x0 0x0 0x80000000>; 93 94 rifsc: rifsc@42080000 { 95 reg = <0x42080000 0x1000>; 96 #address-cells = <1>; 97 #size-cells = <1>; 98 99 usart2: serial@400e0000 { 100 reg = <0x400e0000 0x400>; 101 status = "disabled"; 102 }; 103 }; 104 105 pinctrl: pinctrl@44240000 { 106 #address-cells = <1>; 107 #size-cells = <1>; 108 compatible = "st,stm32mp257-pinctrl"; 109 ranges = <0 0x44240000 0xa0400>; 110 pins-are-numbered; 111 112 gpioa: gpio@44240000 { 113 gpio-controller; 114 #gpio-cells = <2>; 115 interrupt-controller; 116 #interrupt-cells = <2>; 117 reg = <0x0 0x400>; 118 st,bank-name = "GPIOA"; 119 status = "disabled"; 120 }; 121 122 gpiob: gpio@44250000 { 123 gpio-controller; 124 #gpio-cells = <2>; 125 interrupt-controller; 126 #interrupt-cells = <2>; 127 reg = <0x10000 0x400>; 128 st,bank-name = "GPIOB"; 129 status = "disabled"; 130 }; 131 132 gpioc: gpio@44260000 { 133 gpio-controller; 134 #gpio-cells = <2>; 135 interrupt-controller; 136 #interrupt-cells = <2>; 137 reg = <0x20000 0x400>; 138 st,bank-name = "GPIOC"; 139 status = "disabled"; 140 }; 141 142 gpiod: gpio@44270000 { 143 gpio-controller; 144 #gpio-cells = <2>; 145 interrupt-controller; 146 #interrupt-cells = <2>; 147 reg = <0x30000 0x400>; 148 st,bank-name = "GPIOD"; 149 status = "disabled"; 150 }; 151 152 gpioe: gpio@44280000 { 153 gpio-controller; 154 #gpio-cells = <2>; 155 interrupt-controller; 156 #interrupt-cells = <2>; 157 reg = <0x40000 0x400>; 158 st,bank-name = "GPIOE"; 159 status = "disabled"; 160 }; 161 162 gpiof: gpio@44290000 { 163 gpio-controller; 164 #gpio-cells = <2>; 165 interrupt-controller; 166 #interrupt-cells = <2>; 167 reg = <0x50000 0x400>; 168 st,bank-name = "GPIOF"; 169 status = "disabled"; 170 }; 171 172 gpiog: gpio@442a0000 { 173 gpio-controller; 174 #gpio-cells = <2>; 175 interrupt-controller; 176 #interrupt-cells = <2>; 177 reg = <0x60000 0x400>; 178 st,bank-name = "GPIOG"; 179 status = "disabled"; 180 }; 181 182 gpioh: gpio@442b0000 { 183 gpio-controller; 184 #gpio-cells = <2>; 185 interrupt-controller; 186 #interrupt-cells = <2>; 187 reg = <0x70000 0x400>; 188 st,bank-name = "GPIOH"; 189 status = "disabled"; 190 }; 191 192 gpioi: gpio@442c0000 { 193 gpio-controller; 194 #gpio-cells = <2>; 195 interrupt-controller; 196 #interrupt-cells = <2>; 197 reg = <0x80000 0x400>; 198 st,bank-name = "GPIOI"; 199 status = "disabled"; 200 }; 201 202 gpioj: gpio@442d0000 { 203 gpio-controller; 204 #gpio-cells = <2>; 205 interrupt-controller; 206 #interrupt-cells = <2>; 207 reg = <0x90000 0x400>; 208 st,bank-name = "GPIOJ"; 209 status = "disabled"; 210 }; 211 212 gpiok: gpio@442e0000 { 213 gpio-controller; 214 #gpio-cells = <2>; 215 interrupt-controller; 216 #interrupt-cells = <2>; 217 reg = <0xa0000 0x400>; 218 st,bank-name = "GPIOK"; 219 status = "disabled"; 220 }; 221 }; 222 223 pinctrl_z: pinctrl-z@46200000 { 224 #address-cells = <1>; 225 #size-cells = <1>; 226 compatible = "st,stm32mp257-z-pinctrl"; 227 ranges = <0 0x46200000 0x400>; 228 pins-are-numbered; 229 230 gpioz: gpio@46200000 { 231 gpio-controller; 232 #gpio-cells = <2>; 233 interrupt-controller; 234 #interrupt-cells = <2>; 235 reg = <0 0x400>; 236 st,bank-name = "GPIOZ"; 237 st,bank-ioport = <11>; 238 status = "disabled"; 239 }; 240 }; 241 }; 242}; 243