1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2023-2025 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/clock/st,stm32mp25-rcc.h> 8#include <dt-bindings/firewall/stm32mp25-rif.h> 9#include <dt-bindings/firewall/stm32mp25-rifsc.h> 10#include <dt-bindings/firewall/stm32mp25-risaf.h> 11#include <dt-bindings/firewall/stm32mp25-risab.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/st,stm32mp25-rcc.h> 14 15/ { 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@0 { 24 compatible = "arm,cortex-a35"; 25 device_type = "cpu"; 26 reg = <0>; 27 enable-method = "psci"; 28 }; 29 }; 30 31 psci { 32 compatible = "arm,psci-1.0"; 33 method = "smc"; 34 }; 35 36 intc: interrupt-controller@4ac00000 { 37 compatible = "arm,cortex-a7-gic"; 38 #interrupt-cells = <3>; 39 interrupt-controller; 40 reg = <0x0 0x4ac10000 0x0 0x1000>, 41 <0x0 0x4ac20000 0x0 0x2000>, 42 <0x0 0x4ac40000 0x0 0x2000>, 43 <0x0 0x4ac60000 0x0 0x2000>; 44 #address-cells = <1>; 45 }; 46 47 clocks { 48 clk_hse: clk-hse { 49 #clock-cells = <0>; 50 compatible = "fixed-clock"; 51 clock-frequency = <24000000>; 52 }; 53 54 clk_hsi: clk-hsi { 55 #clock-cells = <0>; 56 compatible = "fixed-clock"; 57 clock-frequency = <64000000>; 58 }; 59 60 clk_lse: clk-lse { 61 #clock-cells = <0>; 62 compatible = "fixed-clock"; 63 clock-frequency = <32768>; 64 }; 65 66 clk_lsi: clk-lsi { 67 #clock-cells = <0>; 68 compatible = "fixed-clock"; 69 clock-frequency = <32000>; 70 }; 71 72 clk_msi: clk-msi { 73 #clock-cells = <0>; 74 compatible = "fixed-clock"; 75 clock-frequency = <4000000>; 76 }; 77 78 clk_i2sin: clk-i2sin { 79 #clock-cells = <0>; 80 compatible = "fixed-clock"; 81 clock-frequency = <0>; 82 }; 83 84 clk_rcbsec: clk-rcbsec { 85 #clock-cells = <0>; 86 compatible = "fixed-clock"; 87 clock-frequency = <64000000>; 88 }; 89 }; 90 91 soc@0 { 92 compatible = "simple-bus"; 93 #address-cells = <1>; 94 #size-cells = <1>; 95 interrupt-parent = <&intc>; 96 ranges = <0x0 0x0 0x0 0x80000000>; 97 98 hpdma1: dma-controller@40400000 { 99 compatible = "st,stm32-dma3"; 100 reg = <0x40400000 0x1000>; 101 clocks = <&rcc CK_BUS_HPDMA1>; 102 resets = <&rcc HPDMA1_R>; 103 #dma-cells = <4>; 104 status = "disabled"; 105 }; 106 107 hpdma2: dma-controller@40410000 { 108 compatible = "st,stm32-dma3"; 109 reg = <0x40410000 0x1000>; 110 clocks = <&rcc CK_BUS_HPDMA2>; 111 resets = <&rcc HPDMA2_R>; 112 #dma-cells = <4>; 113 status = "disabled"; 114 }; 115 116 hpdma3: dma-controller@40420000 { 117 compatible = "st,stm32-dma3"; 118 reg = <0x40420000 0x1000>; 119 clocks = <&rcc CK_BUS_HPDMA3>; 120 resets = <&rcc HPDMA3_R>; 121 #dma-cells = <4>; 122 status = "disabled"; 123 }; 124 125 ipcc1: mailbox@40490000 { 126 compatible = "st,stm32mp25-ipcc"; 127 reg = <0x40490000 0x400>; 128 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 129 interrupt-names = "rx"; 130 clocks = <&rcc CK_BUS_IPCC1>; 131 status = "disabled"; 132 }; 133 134 ommanager: ommanager@40500000 { 135 compatible = "st,stm32mp25-omm"; 136 reg = <0x40500000 0x400>, <0x60000000 0x10000000>; 137 reg-names = "regs", "memory_map"; 138 ranges = <0 0 0x40430000 0x400>, 139 <1 0 0x40440000 0x400>; 140 clocks = <&rcc CK_BUS_OSPIIOM>; 141 resets = <&rcc OSPIIOM_R>; 142 #address-cells = <2>; 143 #size-cells = <1>; 144 st,syscfg-amcr = <&syscfg 0x2c00 0x7>; 145 status = "disabled"; 146 147 ospi1: spi@0 { 148 compatible = "st,stm32mp25-ospi"; 149 reg = <0 0 0x400>; 150 clocks = <&rcc CK_KER_OSPI1>; 151 resets = <&rcc OSPI1_R>, <&rcc OSPI1DLL_R>; 152 status = "disabled"; 153 }; 154 155 ospi2: spi@1 { 156 compatible = "st,stm32mp25-ospi"; 157 reg = <1 0 0x400>; 158 clocks = <&rcc CK_KER_OSPI2>; 159 resets = <&rcc OSPI2_R>, <&rcc OSPI2DLL_R>; 160 status = "disabled"; 161 }; 162 }; 163 164 rifsc: rifsc@42080000 { 165 compatible = "st,stm32mp25-rifsc", "simple-bus"; 166 reg = <0x42080000 0x1000>; 167 #address-cells = <1>; 168 #size-cells = <1>; 169 #access-controller-cells = <1>; 170 171 usart2: serial@400e0000 { 172 compatible = "st,stm32h7-uart"; 173 reg = <0x400e0000 0x400>; 174 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 175 clocks = <&rcc CK_KER_USART2>; 176 access-controllers = <&rifsc STM32MP25_RIFSC_USART2_ID>; 177 status = "disabled"; 178 }; 179 180 rng: rng@42020000 { 181 compatible = "st,stm32mp25-rng"; 182 reg = <0x42020000 0x400>; 183 clocks = <&clk_rcbsec>, <&rcc CK_BUS_RNG>; 184 clock-names = "rng_clk", "rng_hclk"; 185 resets = <&rcc RNG_R>; 186 access-controllers = <&rifsc STM32MP25_RIFSC_RNG_ID>; 187 }; 188 189 iwdg1: watchdog@44010000 { 190 compatible = "st,stm32mp1-iwdg"; 191 reg = <0x44010000 0x400>; 192 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 193 clocks = <&rcc CK_BUS_IWDG1>, <&rcc LSI_CK>; 194 clock-names = "pclk", "lsi"; 195 access-controllers = <&rifsc STM32MP25_RIFSC_IWDG1_ID>; 196 status = "disabled"; 197 }; 198 199 iwdg2: watchdog@44020000 { 200 compatible = "st,stm32mp1-iwdg"; 201 reg = <0x44020000 0x400>; 202 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 203 clocks = <&rcc CK_BUS_IWDG2>, <&rcc LSI_CK>; 204 clock-names = "pclk", "lsi"; 205 resets = <&rcc IWDG2_SYS_R>; 206 access-controllers = <&rifsc STM32MP25_RIFSC_IWDG2_ID>; 207 status = "disabled"; 208 }; 209 }; 210 211 iac: iac@42090000 { 212 compatible = "st,stm32mp25-iac"; 213 reg = <0x42090000 0x400>; 214 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 215 }; 216 217 risaf1: risaf@420a0000 { 218 compatible = "st,stm32mp25-risaf"; 219 reg = <0x420a0000 0x1000>; 220 clocks = <&rcc CK_BUS_BKPSRAM>; 221 st,mem-map = <0x0 0x42000000 0x0 0x2000>; 222 #access-controller-cells = <1>; 223 }; 224 225 risaf2: risaf@420b0000 { 226 compatible = "st,stm32mp25-risaf"; 227 reg = <0x420b0000 0x1000>; 228 clocks = <&rcc CK_KER_OSPI1>; 229 st,mem-map = <0x0 0x60000000 0x0 0x10000000>; 230 #access-controller-cells = <1>; 231 status = "disabled"; 232 }; 233 234 risaf4: risaf@420d0000 { 235 compatible = "st,stm32mp25-risaf-enc"; 236 reg = <0x420d0000 0x1000>; 237 clocks = <&rcc CK_BUS_RISAF4>; 238 st,mem-map = <0x0 0x80000000 0x1 0x00000000>; 239 #access-controller-cells = <1>; 240 }; 241 242 risaf5: risaf@420e0000 { 243 compatible = "st,stm32mp25-risaf"; 244 reg = <0x420e0000 0x1000>; 245 clocks = <&rcc CK_BUS_PCIE>; 246 st,mem-map = <0x0 0x10000000 0x0 0x10000000>; 247 #access-controller-cells = <1>; 248 status = "disabled"; 249 }; 250 251 risab1: risab@420f0000 { 252 compatible = "st,stm32mp25-risab"; 253 reg = <0x420f0000 0x1000>; 254 clocks = <&rcc CK_ICN_LS_MCU>; 255 st,mem-map = <0xa000000 0x20000>; 256 #access-controller-cells = <1>; 257 }; 258 259 risab2: risab@42100000 { 260 compatible = "st,stm32mp25-risab"; 261 reg = <0x42100000 0x1000>; 262 clocks = <&rcc CK_ICN_LS_MCU>; 263 st,mem-map = <0xa020000 0x20000>; 264 #access-controller-cells = <1>; 265 }; 266 267 risab3: risab@42110000 { 268 compatible = "st,stm32mp25-risab"; 269 reg = <0x42110000 0x1000>; 270 clocks = <&rcc CK_ICN_LS_MCU>; 271 st,mem-map = <0xa040000 0x20000>; 272 #access-controller-cells = <1>; 273 }; 274 275 risab4: risab@42120000 { 276 compatible = "st,stm32mp25-risab"; 277 reg = <0x42120000 0x1000>; 278 clocks = <&rcc CK_ICN_LS_MCU>; 279 st,mem-map = <0xa060000 0x20000>; 280 #access-controller-cells = <1>; 281 }; 282 283 risab5: risab@42130000 { 284 compatible = "st,stm32mp25-risab"; 285 reg = <0x42130000 0x1000>; 286 clocks = <&rcc CK_ICN_LS_MCU>; 287 st,mem-map = <0xa080000 0x20000>; 288 #access-controller-cells = <1>; 289 }; 290 291 risab6: risab@42140000 { 292 compatible = "st,stm32mp25-risab"; 293 reg = <0x42140000 0x1000>; 294 clocks = <&rcc CK_ICN_LS_MCU>; 295 st,mem-map = <0xa0a0000 0x20000>; 296 #access-controller-cells = <1>; 297 status = "disabled"; 298 }; 299 300 serc: serc@44080000 { 301 compatible = "st,stm32mp25-serc"; 302 reg = <0x44080000 0x1000>; 303 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&rcc CK_BUS_SERC>; 305 }; 306 307 rcc: rcc@44200000 { 308 compatible = "st,stm32mp25-rcc", "syscon"; 309 reg = <0x44200000 0x10000>; 310 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 311 312 #clock-cells = <1>; 313 #reset-cells = <1>; 314 clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>, 315 <&clk_lsi>, <&clk_msi>, <&clk_i2sin>; 316 clock-names = "clk-hse", "clk-hsi", "clk-lse", 317 "clk-lsi", "clk-msi", "clk-i2sin"; 318 319 hsi_calibration: hsi-calibration { 320 compatible = "st,hsi-cal"; 321 st,cal_hsi_dev = <31>; 322 st,cal_hsi_ref = <1953>; 323 status = "disabled"; 324 }; 325 326 msi_calibration: msi-calibration { 327 compatible = "st,msi-cal"; 328 status = "disabled"; 329 }; 330 }; 331 332 exti1: interrupt-controller@44220000 { 333 compatible = "st,stm32mp1-exti"; 334 interrupt-controller; 335 #interrupt-cells = <2>; 336 reg = <0x44220000 0x400>; 337 interrupts-extended = 338 <&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 339 <&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 340 <&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 341 <&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 342 <&intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 343 <&intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 344 <&intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 345 <&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 346 <&intc GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 347 <&intc GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 348 <&intc GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 349 <&intc GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 350 <&intc GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 351 <&intc GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 352 <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 353 <&intc GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 354 <&intc GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 355 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 356 <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 357 <&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 358 <0>, /* EXTI_20 */ 359 <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 360 <&intc GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 361 <&intc GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 362 <&intc GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 363 <&intc GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 364 <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 365 <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 366 <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 367 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 368 <&intc GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 369 <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 370 <&intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 371 <&intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 372 <&intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 373 <0>, 374 <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 375 <&intc GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 376 <&intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 377 <&intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 378 <&intc GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ 379 <&intc GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 380 <&intc GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 381 <&intc GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 382 <&intc GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 383 <&intc GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 384 <&intc GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 385 <&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 386 <&intc GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 387 <&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 388 <&intc GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 389 <0>, 390 <0>, 391 <0>, 392 <0>, 393 <0>, 394 <0>, 395 <0>, 396 <0>, 397 <&intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 398 <0>, /* EXTI_60 */ 399 <&intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 400 <0>, 401 <0>, 402 <&intc GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 403 <0>, 404 <0>, 405 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 406 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 407 <0>, 408 <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ 409 <0>, 410 <&intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 411 <&intc GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 412 <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 413 <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 414 <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 415 <&intc GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 416 <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 417 <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 418 <0>, /* EXTI_80 */ 419 <0>, 420 <0>, 421 <&intc GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 422 <&intc GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 423 }; 424 425 syscfg: syscon@44230000 { 426 reg = <0x44230000 0x10000>; 427 status = "disabled"; 428 }; 429 430 pinctrl: pinctrl@44240000 { 431 #address-cells = <1>; 432 #size-cells = <1>; 433 compatible = "st,stm32mp257-pinctrl"; 434 ranges = <0 0x44240000 0xa0400>; 435 436 gpioa: gpio@44240000 { 437 gpio-controller; 438 #gpio-cells = <2>; 439 interrupt-controller; 440 #interrupt-cells = <2>; 441 #access-controller-cells = <1>; 442 reg = <0x0 0x400>; 443 clocks = <&rcc CK_BUS_GPIOA>; 444 st,bank-name = "GPIOA"; 445 status = "disabled"; 446 }; 447 448 gpiob: gpio@44250000 { 449 gpio-controller; 450 #gpio-cells = <2>; 451 interrupt-controller; 452 #interrupt-cells = <2>; 453 #access-controller-cells = <1>; 454 reg = <0x10000 0x400>; 455 clocks = <&rcc CK_BUS_GPIOB>; 456 st,bank-name = "GPIOB"; 457 status = "disabled"; 458 }; 459 460 gpioc: gpio@44260000 { 461 gpio-controller; 462 #gpio-cells = <2>; 463 interrupt-controller; 464 #interrupt-cells = <2>; 465 #access-controller-cells = <1>; 466 reg = <0x20000 0x400>; 467 clocks = <&rcc CK_BUS_GPIOC>; 468 st,bank-name = "GPIOC"; 469 status = "disabled"; 470 }; 471 472 gpiod: gpio@44270000 { 473 gpio-controller; 474 #gpio-cells = <2>; 475 interrupt-controller; 476 #interrupt-cells = <2>; 477 #access-controller-cells = <1>; 478 reg = <0x30000 0x400>; 479 clocks = <&rcc CK_BUS_GPIOD>; 480 st,bank-name = "GPIOD"; 481 status = "disabled"; 482 }; 483 484 gpioe: gpio@44280000 { 485 gpio-controller; 486 #gpio-cells = <2>; 487 interrupt-controller; 488 #interrupt-cells = <2>; 489 #access-controller-cells = <1>; 490 reg = <0x40000 0x400>; 491 clocks = <&rcc CK_BUS_GPIOE>; 492 st,bank-name = "GPIOE"; 493 status = "disabled"; 494 }; 495 496 gpiof: gpio@44290000 { 497 gpio-controller; 498 #gpio-cells = <2>; 499 interrupt-controller; 500 #interrupt-cells = <2>; 501 #access-controller-cells = <1>; 502 reg = <0x50000 0x400>; 503 clocks = <&rcc CK_BUS_GPIOF>; 504 st,bank-name = "GPIOF"; 505 status = "disabled"; 506 }; 507 508 gpiog: gpio@442a0000 { 509 gpio-controller; 510 #gpio-cells = <2>; 511 interrupt-controller; 512 #interrupt-cells = <2>; 513 #access-controller-cells = <1>; 514 reg = <0x60000 0x400>; 515 clocks = <&rcc CK_BUS_GPIOG>; 516 st,bank-name = "GPIOG"; 517 status = "disabled"; 518 }; 519 520 gpioh: gpio@442b0000 { 521 gpio-controller; 522 #gpio-cells = <2>; 523 interrupt-controller; 524 #interrupt-cells = <2>; 525 #access-controller-cells = <1>; 526 reg = <0x70000 0x400>; 527 clocks = <&rcc CK_BUS_GPIOH>; 528 st,bank-name = "GPIOH"; 529 status = "disabled"; 530 }; 531 532 gpioi: gpio@442c0000 { 533 gpio-controller; 534 #gpio-cells = <2>; 535 interrupt-controller; 536 #interrupt-cells = <2>; 537 #access-controller-cells = <1>; 538 reg = <0x80000 0x400>; 539 clocks = <&rcc CK_BUS_GPIOI>; 540 st,bank-name = "GPIOI"; 541 status = "disabled"; 542 }; 543 544 gpioj: gpio@442d0000 { 545 gpio-controller; 546 #gpio-cells = <2>; 547 interrupt-controller; 548 #interrupt-cells = <2>; 549 #access-controller-cells = <1>; 550 reg = <0x90000 0x400>; 551 clocks = <&rcc CK_BUS_GPIOJ>; 552 st,bank-name = "GPIOJ"; 553 status = "disabled"; 554 }; 555 556 gpiok: gpio@442e0000 { 557 gpio-controller; 558 #gpio-cells = <2>; 559 interrupt-controller; 560 #interrupt-cells = <2>; 561 #access-controller-cells = <1>; 562 reg = <0xa0000 0x400>; 563 clocks = <&rcc CK_BUS_GPIOK>; 564 st,bank-name = "GPIOK"; 565 status = "disabled"; 566 }; 567 }; 568 569 rtc: rtc@46000000 { 570 compatible = "st,stm32mp25-rtc"; 571 reg = <0x46000000 0x400>; 572 clocks = <&rcc CK_BUS_RTC>, <&rcc RTC_CK>; 573 clock-names = "pclk", "rtc_ck"; 574 wakeup-source; 575 interrupts-extended = <&exti2 22 IRQ_TYPE_EDGE_RISING>; 576 }; 577 578 tamp: tamp@46010000 { 579 compatible = "st,stm32mp25-tamp"; 580 reg = <0x46010000 0x400>; 581 clocks = <&rcc CK_BUS_RTC>; 582 interrupts-extended = <&exti2 21 IRQ_TYPE_EDGE_RISING>; 583 #address-cells = <1>; 584 #size-cells = <1>; 585 ranges; 586 st,backup-zones = <24 24 24 24 12 12 8>; 587 }; 588 589 pinctrl_z: pinctrl-z@46200000 { 590 #address-cells = <1>; 591 #size-cells = <1>; 592 compatible = "st,stm32mp257-z-pinctrl"; 593 ranges = <0 0x46200000 0x400>; 594 595 gpioz: gpio@46200000 { 596 gpio-controller; 597 #gpio-cells = <2>; 598 interrupt-controller; 599 #interrupt-cells = <2>; 600 #access-controller-cells = <1>; 601 reg = <0 0x400>; 602 clocks = <&rcc CK_BUS_GPIOZ>; 603 st,bank-name = "GPIOZ"; 604 st,bank-ioport = <11>; 605 status = "disabled"; 606 }; 607 }; 608 609 exti2: interrupt-controller@46230000 { 610 compatible = "st,stm32mp1-exti"; 611 interrupt-controller; 612 #interrupt-cells = <2>; 613 reg = <0x46230000 0x400>; 614 interrupts-extended = 615 <&intc GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 616 <&intc GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 617 <&intc GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 618 <&intc GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 619 <&intc GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 620 <&intc GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 621 <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 622 <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 623 <&intc GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 624 <&intc GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 625 <&intc GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 626 <&intc GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 627 <&intc GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 628 <&intc GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 629 <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 630 <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 631 <&intc GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 632 <&intc GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 633 <0>, 634 <0>, 635 <0>, /* EXTI_20 */ 636 <&intc GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 637 <&intc GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 638 <0>, 639 <0>, 640 <&intc GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 641 <&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 642 <&intc GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 643 <0>, 644 <&intc GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 645 <&intc GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 646 <&intc GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 647 <0>, 648 <&intc GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 649 <&intc GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 650 <0>, 651 <0>, 652 <&intc GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 653 <0>, 654 <0>, 655 <&intc GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ 656 <0>, 657 <0>, 658 <&intc GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 659 <0>, 660 <0>, 661 <&intc GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 662 <0>, 663 <&intc GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 664 <&intc GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 665 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 666 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 667 <&intc GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 668 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 669 <0>, 670 <0>, 671 <0>, 672 <0>, 673 <0>, 674 <0>, 675 <0>, /* EXTI_60 */ 676 <&intc GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 677 <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 678 <0>, 679 <&intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 680 <&intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 681 <&intc GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 682 <&intc GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 683 <0>, 684 <0>, 685 <&intc GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ 686 }; 687 688 hsem: hwspinlock@46240000 { 689 compatible = "st,stm32mp25-hsem"; 690 reg = <0x46240000 0x400>; 691 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 692 clocks = <&rcc CK_BUS_HSEM>; 693 status = "disabled"; 694 }; 695 696 ipcc2: mailbox@46250000 { 697 compatible = "st,stm32mp25-ipcc"; 698 reg = <0x46250000 0x400>; 699 clocks = <&rcc CK_BUS_IPCC2>; 700 status = "disabled"; 701 }; 702 703 stgenc: stgen@48080000 { 704 compatible = "st,stm32mp25-stgen"; 705 reg = <0x48080000 0x1000>; 706 clocks = <&rcc CK_BUS_STGEN>, <&rcc CK_KER_STGEN>; 707 clock-names = "bus", "stgen_clk"; 708 }; 709 710 fmc: memory-controller@48200000 { 711 compatible = "st,stm32mp25-fmc2-ebi"; 712 reg = <0x48200000 0x400>; 713 ranges = <0 0 0x70000000 0x04000000>, /* EBI CS 1 */ 714 <1 0 0x74000000 0x04000000>, /* EBI CS 2 */ 715 <2 0 0x78000000 0x04000000>, /* EBI CS 3 */ 716 <3 0 0x7c000000 0x04000000>, /* EBI CS 4 */ 717 <4 0 0x48810000 0x00001000>; /* NAND */ 718 #address-cells = <2>; 719 #size-cells = <1>; 720 clocks = <&rcc CK_KER_FMC>; 721 resets = <&rcc FMC_R>; 722 status = "disabled"; 723 }; 724 }; 725}; 726