xref: /optee_os/core/arch/arm/dts/stm32mp235f-dk-ca35tdcid-rcc.dtsi (revision 0960b6765c51598643bdb226a3bfaeab1b0e608f) 
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
4 */
5
6&clk_hse {
7	clock-frequency = <40000000>;
8};
9
10&clk_hsi {
11	clock-frequency = <64000000>;
12};
13
14&clk_lse {
15	clock-frequency = <32768>;
16};
17
18&clk_lsi {
19	clock-frequency = <32000>;
20};
21
22&clk_msi {
23	clock-frequency = <16000000>;
24};
25
26&rcc {
27	st,busclk = <
28		DIV_CFG(DIV_LSMCU, 1)
29		DIV_CFG(DIV_APB1, 0)
30		DIV_CFG(DIV_APB2, 0)
31		DIV_CFG(DIV_APB3, 0)
32		DIV_CFG(DIV_APB4, 0)
33		DIV_CFG(DIV_APBDBG, 0)
34	>;
35
36	st,flexgen = <
37		FLEXGEN_CFG(0, XBAR_SRC_PLL4, 0, 2)
38		FLEXGEN_CFG(1, XBAR_SRC_PLL4, 0, 5)
39		FLEXGEN_CFG(2, XBAR_SRC_PLL4, 0, 1)
40		FLEXGEN_CFG(3, XBAR_SRC_PLL4, 0, 2)
41		FLEXGEN_CFG(4, XBAR_SRC_PLL4, 0, 3)
42		FLEXGEN_CFG(5, XBAR_SRC_PLL4, 0, 2)
43		FLEXGEN_CFG(6, XBAR_SRC_PLL4, 0, 1)
44		FLEXGEN_CFG(7, XBAR_SRC_PLL4, 0, 11)
45		FLEXGEN_CFG(8, XBAR_SRC_HSI_KER, 0, 0)
46		FLEXGEN_CFG(9, XBAR_SRC_HSI_KER, 0, 0)
47		FLEXGEN_CFG(10, XBAR_SRC_PLL7, 0, 16)
48		FLEXGEN_CFG(11, XBAR_SRC_PLL4, 0, 5)
49		FLEXGEN_CFG(12, XBAR_SRC_PLL4, 0, 11)
50		FLEXGEN_CFG(15, XBAR_SRC_PLL4, 0, 11)
51		FLEXGEN_CFG(16, XBAR_SRC_PLL4, 0, 23)
52		FLEXGEN_CFG(17, XBAR_SRC_PLL5, 0, 3)
53		FLEXGEN_CFG(18, XBAR_SRC_PLL5, 0, 3)
54		FLEXGEN_CFG(19, XBAR_SRC_HSI_KER, 0, 0)
55		FLEXGEN_CFG(20, XBAR_SRC_HSI_KER, 0, 0)
56		FLEXGEN_CFG(21, XBAR_SRC_HSI_KER, 0, 0)
57		FLEXGEN_CFG(23, XBAR_SRC_PLL7, 0, 16)
58		FLEXGEN_CFG(24, XBAR_SRC_PLL7, 0, 16)
59		FLEXGEN_CFG(25, XBAR_SRC_PLL7, 0, 16)
60		FLEXGEN_CFG(26, XBAR_SRC_PLL4, 0, 11)
61		FLEXGEN_CFG(27, XBAR_SRC_PLL8, 0, 3)
62		FLEXGEN_CFG(28, XBAR_SRC_PLL8, 0, 21)
63		FLEXGEN_CFG(29, XBAR_SRC_PLL5, 0, 1)
64		FLEXGEN_CFG(30, XBAR_SRC_HSE_KER, 0, 1)
65		FLEXGEN_CFG(31, XBAR_SRC_PLL5, 0, 19)
66		FLEXGEN_CFG(32, XBAR_SRC_PLL5, 0, 19)
67		FLEXGEN_CFG(33, XBAR_SRC_HSE_KER, 0, 0)
68		FLEXGEN_CFG(34, XBAR_SRC_PLL4, 0, 59)
69		FLEXGEN_CFG(35, XBAR_SRC_HSI_KER, 0, 3)
70		FLEXGEN_CFG(36, XBAR_SRC_PLL5, 0, 3)
71		FLEXGEN_CFG(37, XBAR_SRC_PLL5, 0, 3)
72		FLEXGEN_CFG(38, XBAR_SRC_PLL5, 0, 3)
73		FLEXGEN_CFG(39, XBAR_SRC_MSI_KER, 0, 0)
74		FLEXGEN_CFG(40, XBAR_SRC_LSE, 0, 0)
75		FLEXGEN_CFG(41, XBAR_SRC_PLL4, 0, 11)
76		FLEXGEN_CFG(43, XBAR_SRC_PLL4, 0, 23)
77		FLEXGEN_CFG(44, XBAR_SRC_PLL4, 0, 5)
78		FLEXGEN_CFG(45, XBAR_SRC_PLL4, 0, 2)
79		FLEXGEN_CFG(46, XBAR_SRC_PLL5, 0, 3)
80		FLEXGEN_CFG(47, XBAR_SRC_PLL5, 0, 3)
81		FLEXGEN_CFG(51, XBAR_SRC_PLL4, 0, 5)
82		FLEXGEN_CFG(52, XBAR_SRC_PLL4, 0, 5)
83		FLEXGEN_CFG(53, XBAR_SRC_PLL4, 0, 5)
84		FLEXGEN_CFG(54, XBAR_SRC_PLL6, 0, 3)
85		FLEXGEN_CFG(55, XBAR_SRC_PLL6, 0, 3)
86		FLEXGEN_CFG(56, XBAR_SRC_PLL4, 0, 5)
87		FLEXGEN_CFG(57, XBAR_SRC_HSE_KER, 0, 1)
88		FLEXGEN_CFG(58, XBAR_SRC_HSE_KER, 0, 1)
89		FLEXGEN_CFG(59, XBAR_SRC_PLL4, 0, 1)
90		FLEXGEN_CFG(61, XBAR_SRC_PLL4, 0, 7)
91		FLEXGEN_CFG(62, XBAR_SRC_PLL4, 0, 7)
92		FLEXGEN_CFG(63, XBAR_SRC_PLL4, 0, 2)
93	>;
94
95	st,kerclk = <
96		MUX_CFG(MUX_ADC12, MUX_ADC12_FLEX46)
97		MUX_CFG(MUX_USB2PHY1, MUX_USB2PHY1_FLEX57)
98		MUX_CFG(MUX_USB2PHY2, MUX_USB2PHY2_FLEX58)
99		MUX_CFG(MUX_USB3PCIEPHY, MUX_USB3PCIEPHY_HSE)
100		MUX_CFG(MUX_DSIPHY, MUX_DSIPHY_FLEX28)
101		MUX_CFG(MUX_DSIBLANE, MUX_DSIBLANE_DSIPHY)
102		MUX_CFG(MUX_LVDSPHY, MUX_LVDSPHY_FLEX32)
103		MUX_CFG(MUX_DTS, MUX_DTS_HSE)
104		MUX_CFG(MUX_RTC, MUX_RTC_LSE)
105		MUX_CFG(MUX_D3PER, MUX_D3PER_MSI)
106		MCO_CFG(MCO1, MUX_MCO1_FLEX61, MCO_OFF)
107		MCO_CFG(MCO2, MUX_MCO2_FLEX62, MCO_OFF)
108	>;
109
110	pll1: st,pll-1 {
111		st,pll = <&pll1_cfg_1200Mhz>;
112
113		pll1_cfg_1200Mhz: pll1-cfg-1200Mhz {
114			cfg = <30 1 1 1>;
115			src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>;
116		};
117
118		pll1_cfg_1500Mhz: pll1-cfg-1500Mhz {
119			cfg = <75 2 1 1>;
120			src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>;
121		};
122	};
123
124	pll2: st,pll-2 {
125		st,pll = <&pll2_cfg_600Mhz>;
126
127		pll2_cfg_600Mhz: pll2-cfg-600Mhz {
128			cfg = <30 1 1 2>;
129			src = <MUX_CFG(MUX_MUXSEL6, MUXSEL_HSE)>;
130		};
131	};
132
133	pll3: st,pll-3 {
134		st,pll = <&pll3_cfg_400Mhz>;
135
136		pll3_cfg_400Mhz: pll3-cfg-400Mhz {
137			cfg = <20 1 1 2>;
138			src = <MUX_CFG(MUX_MUXSEL7, MUXSEL_HSE)>;
139		};
140	};
141
142	pll4: st,pll-4 {
143		st,pll = <&pll4_cfg_1200Mhz>;
144
145		pll4_cfg_1200Mhz: pll4-cfg-1200Mhz {
146			cfg = <30 1 1 1>;
147			src = <MUX_CFG(MUX_MUXSEL0, MUXSEL_HSE)>;
148		};
149	};
150
151	pll5: st,pll-5 {
152		st,pll = <&pll5_cfg_532Mhz>;
153
154		pll5_cfg_532Mhz: pll5-cfg-532Mhz {
155			cfg = <133 5 1 2>;
156			src = <MUX_CFG(MUX_MUXSEL1, MUXSEL_HSE)>;
157		};
158	};
159
160	pll6: st,pll-6 {
161		st,pll = <&pll6_cfg_500Mhz>;
162
163		pll6_cfg_500Mhz: pll6-cfg-500Mhz {
164			cfg = <25 1 1 2>;
165			src = <MUX_CFG(MUX_MUXSEL2, MUXSEL_HSE)>;
166		};
167	};
168
169	pll7: st,pll-7 {
170		st,pll = <&pll7_cfg_835_51172Mhz>;
171
172		pll7_cfg_835_51172Mhz: pll7-cfg-835-51172Mhz {
173			cfg = <167 4 1 2>;
174			src = <MUX_CFG(MUX_MUXSEL3, MUXSEL_HSE)>;
175			frac = < 0x1A3337 >;
176		};
177	};
178
179	pll8: st,pll-8 {
180		st,pll = <&pll8_cfg_594Mhz>;
181
182		pll8_cfg_594Mhz: pll8-cfg-594Mhz {
183			cfg = <297 5 1 4>;
184			src = <MUX_CFG(MUX_MUXSEL4, MUXSEL_HSE)>;
185		};
186	};
187};
188
189