1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2/* 3 * Copyright (C) 2025, STMicroelectronics - All Rights Reserved 4 */ 5 6/* 7 * STM32MP21 Clock tree device tree configuration 8 */ 9 10&clk_hse { 11 clock-frequency = <40000000>; 12}; 13 14&clk_hsi { 15 clock-frequency = <64000000>; 16}; 17 18&clk_lse { 19 clock-frequency = <32768>; 20}; 21 22&clk_lsi { 23 clock-frequency = <32000>; 24}; 25 26&clk_msi { 27 clock-frequency = <16000000>; 28}; 29 30&rcc { 31 st,busclk = < 32 DIV_CFG(DIV_LSMCU, 1) 33 DIV_CFG(DIV_APB1, 0) 34 DIV_CFG(DIV_APB2, 0) 35 DIV_CFG(DIV_APB3, 0) 36 DIV_CFG(DIV_APB4, 0) 37 DIV_CFG(DIV_APB5, 0) 38 DIV_CFG(DIV_APBDBG, 0) 39 >; 40 41 st,flexgen = < 42 FLEXGEN_CFG(0, XBAR_SRC_PLL4, 0, 3) 43 FLEXGEN_CFG(1, XBAR_SRC_PLL4, 0, 5) 44 FLEXGEN_CFG(2, XBAR_SRC_PLL4, 0, 1) 45 FLEXGEN_CFG(3, XBAR_SRC_PLL4, 0, 2) 46 FLEXGEN_CFG(4, XBAR_SRC_PLL4, 0, 3) 47 FLEXGEN_CFG(5, XBAR_SRC_PLL4, 0, 2) 48 FLEXGEN_CFG(6, XBAR_SRC_PLL4, 0, 1) 49 FLEXGEN_CFG(7, XBAR_SRC_PLL4, 0, 11) 50 FLEXGEN_CFG(8, XBAR_SRC_HSI_KER, 0, 0) 51 FLEXGEN_CFG(9, XBAR_SRC_HSI_KER, 0, 0) 52 FLEXGEN_CFG(10, XBAR_SRC_PLL7, 0, 16) 53 FLEXGEN_CFG(11, XBAR_SRC_PLL7, 0, 16) 54 FLEXGEN_CFG(12, XBAR_SRC_PLL4, 0, 5) 55 FLEXGEN_CFG(13, XBAR_SRC_PLL4, 0, 11) 56 FLEXGEN_CFG(14, XBAR_SRC_PLL4, 0, 11) 57 FLEXGEN_CFG(16, XBAR_SRC_PLL7, 0, 16) 58 FLEXGEN_CFG(17, XBAR_SRC_PLL5, 0, 3) 59 FLEXGEN_CFG(18, XBAR_SRC_HSI_KER, 0, 0) 60 FLEXGEN_CFG(19, XBAR_SRC_HSI_KER, 0, 0) 61 FLEXGEN_CFG(20, XBAR_SRC_HSI_KER, 0, 0) 62 FLEXGEN_CFG(21, XBAR_SRC_PLL7, 0, 16) 63 FLEXGEN_CFG(22, XBAR_SRC_PLL7, 0, 16) 64 FLEXGEN_CFG(23, XBAR_SRC_PLL7, 0, 16) 65 FLEXGEN_CFG(24, XBAR_SRC_PLL7, 0, 16) 66 FLEXGEN_CFG(25, XBAR_SRC_PLL7, 0, 16) 67 FLEXGEN_CFG(26, XBAR_SRC_PLL4, 0, 11) 68 FLEXGEN_CFG(27, XBAR_SRC_PLL8, 0, 3) 69 FLEXGEN_CFG(29, XBAR_SRC_PLL5, 0, 1) 70 FLEXGEN_CFG(30, XBAR_SRC_HSE_KER, 0, 1) 71 FLEXGEN_CFG(31, XBAR_SRC_PLL5, 0, 19) 72 FLEXGEN_CFG(33, XBAR_SRC_HSE_KER, 0, 0) 73 FLEXGEN_CFG(36, XBAR_SRC_PLL4, 0, 11) 74 FLEXGEN_CFG(37, XBAR_SRC_PLL5, 0, 3) 75 FLEXGEN_CFG(38, XBAR_SRC_PLL4, 0, 11) 76 FLEXGEN_CFG(39, XBAR_SRC_MSI_KER, 0, 0) 77 FLEXGEN_CFG(40, XBAR_SRC_LSE, 0, 0) 78 FLEXGEN_CFG(41, XBAR_SRC_PLL4, 0, 11) 79 FLEXGEN_CFG(42, XBAR_SRC_PLL4, 0, 11) 80 FLEXGEN_CFG(43, XBAR_SRC_PLL4, 0, 23) 81 FLEXGEN_CFG(44, XBAR_SRC_PLL4, 0, 5) 82 FLEXGEN_CFG(45, XBAR_SRC_PLL4, 0, 2) 83 FLEXGEN_CFG(46, XBAR_SRC_PLL5, 0, 3) 84 FLEXGEN_CFG(47, XBAR_SRC_PLL5, 0, 3) 85 FLEXGEN_CFG(48, XBAR_SRC_PLL5, 0, 3) 86 FLEXGEN_CFG(51, XBAR_SRC_PLL4, 0, 5) 87 FLEXGEN_CFG(52, XBAR_SRC_PLL4, 0, 5) 88 FLEXGEN_CFG(53, XBAR_SRC_PLL4, 0, 5) 89 FLEXGEN_CFG(54, XBAR_SRC_PLL6, 0, 9) 90 FLEXGEN_CFG(55, XBAR_SRC_PLL6, 0, 3) 91 FLEXGEN_CFG(56, XBAR_SRC_PLL4, 0, 5) 92 FLEXGEN_CFG(57, XBAR_SRC_HSE_KER, 0, 1) 93 FLEXGEN_CFG(58, XBAR_SRC_HSE_KER, 0, 1) 94 FLEXGEN_CFG(61, XBAR_SRC_PLL4, 0, 7) 95 FLEXGEN_CFG(62, XBAR_SRC_PLL4, 0, 7) 96 FLEXGEN_CFG(63, XBAR_SRC_PLL4, 0, 2) 97 >; 98 99 st,kerclk = < 100 MUX_CFG(MUX_ADC1, MUX_ADC1_FLEX46) 101 MUX_CFG(MUX_ADC2, MUX_ADC2_FLEX47) 102 MUX_CFG(MUX_USB2PHY1, MUX_USB2PHY1_FLEX57) 103 MUX_CFG(MUX_USB2PHY2, MUX_USB2PHY2_FLEX58) 104 MUX_CFG(MUX_DTS, MUX_DTS_HSE) 105 MUX_CFG(MUX_RTC, MUX_RTC_LSE) 106 MCO_CFG(MCO1, MUX_MCO1_FLEX61, MCO_OFF) 107 MCO_CFG(MCO2, MUX_MCO2_FLEX62, MCO_OFF) 108 >; 109 110 pll1: st,pll-1 { 111 st,pll = <&pll1_cfg_1200MHz>; 112 113 pll1_cfg_1200MHz: pll1-cfg-1200MHz { 114 cfg = <30 1 1 1>; 115 src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>; 116 }; 117 118 pll1_cfg_1500MHz: pll1-cfg-1500MHz { 119 cfg = <75 2 1 1>; 120 src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>; 121 }; 122 }; 123 124 pll2: st,pll-2 { 125 st,pll = <&pll2_cfg_400MHz>; 126 127 pll2_cfg_400MHz: pll2-cfg-400MHz { 128 cfg = <20 1 1 2>; 129 src = <MUX_CFG(MUX_MUXSEL6, MUXSEL_HSE)>; 130 }; 131 }; 132 133 pll4: st,pll-4 { 134 st,pll = <&pll4_cfg_1200MHz>; 135 136 pll4_cfg_1200MHz: pll4-cfg-1200MHz { 137 cfg = <30 1 1 1>; 138 src = <MUX_CFG(MUX_MUXSEL0, MUXSEL_HSE)>; 139 }; 140 }; 141 142 pll5: st,pll-5 { 143 st,pll = <&pll5_cfg_532MHz>; 144 145 pll5_cfg_532MHz: pll5-cfg-532MHz { 146 cfg = <133 5 1 2>; 147 src = <MUX_CFG(MUX_MUXSEL1, MUXSEL_HSE)>; 148 }; 149 }; 150 151 pll6: st,pll-6 { 152 st,pll = <&pll6_cfg_500MHz>; 153 154 pll6_cfg_500MHz: pll6-cfg-500MHz { 155 cfg = <25 1 1 2>; 156 src = <MUX_CFG(MUX_MUXSEL2, MUXSEL_HSE)>; 157 }; 158 }; 159 160 pll7: st,pll-7 { 161 st,pll = <&pll7_cfg_835_51172MHz>; 162 163 pll7_cfg_835_51172MHz: pll7-cfg-835-51172MHz { 164 cfg = <167 4 1 2>; 165 src = <MUX_CFG(MUX_MUXSEL3, MUXSEL_HSE)>; 166 frac = < 0x1A3337 >; 167 }; 168 }; 169 170 pll8: st,pll-8 { 171 st,pll = <&pll8_cfg_594MHz>; 172 173 pll8_cfg_594MHz: pll8-cfg-594MHz { 174 cfg = <297 5 1 4>; 175 src = <MUX_CFG(MUX_MUXSEL4, MUXSEL_HSE)>; 176 }; 177 }; 178}; 179