1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2/* 3 * Copyright (C) 2025, STMicroelectronics - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/firewall/stm32mp21-rifsc.h> 9#include <dt-bindings/firewall/stm32mp25-rif.h> 10#include <dt-bindings/firewall/stm32mp25-risab.h> 11#include <dt-bindings/firewall/stm32mp25-risaf.h> 12 13/ { 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu0: cpu@0 { 22 compatible = "arm,cortex-a35"; 23 device_type = "cpu"; 24 reg = <0>; 25 enable-method = "psci"; 26 }; 27 }; 28 29 psci { 30 compatible = "arm,psci-1.0"; 31 method = "smc"; 32 }; 33 34 intc: interrupt-controller@4ac00000 { 35 compatible = "arm,cortex-a7-gic"; 36 #interrupt-cells = <3>; 37 interrupt-controller; 38 reg = <0x0 0x4ac10000 0x0 0x1000>, 39 <0x0 0x4ac20000 0x0 0x2000>, 40 <0x0 0x4ac40000 0x0 0x2000>, 41 <0x0 0x4ac60000 0x0 0x2000>; 42 #address-cells = <1>; 43 }; 44 45 clocks { 46 clk_hse: clk-hse { 47 #clock-cells = <0>; 48 compatible = "fixed-clock"; 49 clock-frequency = <48000000>; 50 }; 51 52 clk_hsi: clk-hsi { 53 #clock-cells = <0>; 54 compatible = "fixed-clock"; 55 clock-frequency = <64000000>; 56 }; 57 58 clk_lse: clk-lse { 59 #clock-cells = <0>; 60 compatible = "fixed-clock"; 61 clock-frequency = <32768>; 62 }; 63 64 clk_lsi: clk-lsi { 65 #clock-cells = <0>; 66 compatible = "fixed-clock"; 67 clock-frequency = <32000>; 68 }; 69 70 clk_msi: clk-msi { 71 #clock-cells = <0>; 72 compatible = "fixed-clock"; 73 clock-frequency = <16000000>; 74 }; 75 76 clk_i2sin: clk-i2sin { 77 #clock-cells = <0>; 78 compatible = "fixed-clock"; 79 clock-frequency = <0>; 80 }; 81 82 clk_rcbsec: clk-rcbsec { 83 #clock-cells = <0>; 84 compatible = "fixed-clock"; 85 clock-frequency = <64000000>; 86 }; 87 }; 88 89 soc@0 { 90 compatible = "simple-bus"; 91 #address-cells = <1>; 92 #size-cells = <1>; 93 interrupt-parent = <&intc>; 94 ranges = <0x0 0x0 0x0 0x80000000>; 95 96 rifsc: bus@42080000 { 97 compatible = "st,stm32mp25-rifsc", "simple-bus"; 98 reg = <0x42080000 0x1000>; 99 #address-cells = <1>; 100 #size-cells = <1>; 101 #access-controller-cells = <1>; 102 }; 103 104 iac: iac@42090000 { 105 compatible = "st,stm32mp25-iac"; 106 reg = <0x42090000 0x400>; 107 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 108 }; 109 110 syscfg: syscon@44230000 { 111 reg = <0x44230000 0x10000>; 112 status = "disabled"; 113 }; 114 }; 115}; 116