xref: /optee_os/core/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi (revision 9f34db38245c9b3a4e6e7e63eb78a75e23ab2da3) 
1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2/*
3 * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
4 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
5 * Copyright (C) 2020 Marek Vasut <marex@denx.de>
6 * Copyright (C) 2022 DH electronics GmbH
7 */
8
9#include "stm32mp15-pinctrl.dtsi"
10#include "stm32mp15xxac-pinctrl.dtsi"
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/mfd/st,stpmic1.h>
13
14/ {
15	aliases {
16		spi0 = &qspi;
17	};
18
19	memory@c0000000 {
20		device_type = "memory";
21		reg = <0xc0000000 0x40000000>;
22	};
23
24	reserved-memory {
25		#address-cells = <1>;
26		#size-cells = <1>;
27		ranges;
28
29		mcuram2: mcuram2@10000000 {
30			compatible = "shared-dma-pool";
31			reg = <0x10000000 0x40000>;
32			no-map;
33		};
34
35		vdev0vring0: vdev0vring0@10040000 {
36			compatible = "shared-dma-pool";
37			reg = <0x10040000 0x1000>;
38			no-map;
39		};
40
41		vdev0vring1: vdev0vring1@10041000 {
42			compatible = "shared-dma-pool";
43			reg = <0x10041000 0x1000>;
44			no-map;
45		};
46
47		vdev0buffer: vdev0buffer@10042000 {
48			compatible = "shared-dma-pool";
49			reg = <0x10042000 0x4000>;
50			no-map;
51		};
52
53		mcuram: mcuram@30000000 {
54			compatible = "shared-dma-pool";
55			reg = <0x30000000 0x40000>;
56			no-map;
57		};
58
59		retram: retram@38000000 {
60			compatible = "shared-dma-pool";
61			reg = <0x38000000 0x10000>;
62			no-map;
63		};
64	};
65};
66
67&crc1 {
68	status = "okay";
69};
70
71&dts {
72	status = "okay";
73};
74
75&etzpc {
76	st,decprot =
77		<DECPROT(STM32MP1_ETZPC_USART1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>,
78		<DECPROT(STM32MP1_ETZPC_SPI6_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>,
79		<DECPROT(STM32MP1_ETZPC_I2C4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>,
80		<DECPROT(STM32MP1_ETZPC_I2C6_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>,
81		<DECPROT(STM32MP1_ETZPC_RNG1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>,
82		<DECPROT(STM32MP1_ETZPC_HASH1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>,
83		<DECPROT(STM32MP1_ETZPC_CRYP1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>,
84		<DECPROT(STM32MP1_ETZPC_DDRCTRL_ID, DECPROT_NS_R_S_W, DECPROT_LOCK)>,
85		<DECPROT(STM32MP1_ETZPC_DDRPHYC_ID, DECPROT_NS_R_S_W, DECPROT_LOCK)>,
86		<DECPROT(STM32MP1_ETZPC_STGENC_ID, DECPROT_S_RW, DECPROT_LOCK)>,
87		<DECPROT(STM32MP1_ETZPC_BKPSRAM_ID, DECPROT_S_RW, DECPROT_LOCK)>,
88		<DECPROT(STM32MP1_ETZPC_IWDG1_ID, DECPROT_NS_RW, DECPROT_LOCK)>;
89};
90
91&i2c4 {
92	pinctrl-names = "default";
93	pinctrl-0 = <&i2c4_pins_a>;
94	i2c-scl-rising-time-ns = <185>;
95	i2c-scl-falling-time-ns = <20>;
96	status = "okay";
97	/delete-property/dmas;
98	/delete-property/dma-names;
99
100	pmic: stpmic@33 {
101		compatible = "st,stpmic1";
102		reg = <0x33>;
103		interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
104		interrupt-controller;
105		#interrupt-cells = <2>;
106		status = "okay";
107
108		regulators {
109			compatible = "st,stpmic1-regulators";
110
111			ldo1-supply = <&v3v3>;
112			ldo2-supply = <&v3v3>;
113			ldo3-supply = <&vdd_ddr>;
114			ldo5-supply = <&v3v3>;
115			ldo6-supply = <&v3v3>;
116			pwr_sw1-supply = <&bst_out>;
117			pwr_sw2-supply = <&bst_out>;
118
119			vddcore: buck1 {
120				regulator-name = "vddcore";
121				regulator-min-microvolt = <1200000>;
122				regulator-max-microvolt = <1350000>;
123				regulator-always-on;
124				regulator-initial-mode = <0>;
125				regulator-over-current-protection;
126			};
127
128			vdd_ddr: buck2 {
129				regulator-name = "vdd_ddr";
130				regulator-min-microvolt = <1350000>;
131				regulator-max-microvolt = <1350000>;
132				regulator-always-on;
133				regulator-initial-mode = <0>;
134				regulator-over-current-protection;
135			};
136
137			vdd: buck3 {
138				regulator-name = "vdd";
139				regulator-min-microvolt = <2900000>;
140				regulator-max-microvolt = <2900000>;
141				regulator-always-on;
142				regulator-initial-mode = <0>;
143				regulator-over-current-protection;
144			};
145
146			v3v3: buck4 {
147				regulator-name = "v3v3";
148				regulator-min-microvolt = <3300000>;
149				regulator-max-microvolt = <3300000>;
150				regulator-always-on;
151				regulator-over-current-protection;
152				regulator-initial-mode = <0>;
153			};
154
155			vdda: ldo1 {
156				regulator-name = "vdda";
157				regulator-min-microvolt = <2900000>;
158				regulator-max-microvolt = <2900000>;
159				interrupts = <IT_CURLIM_LDO1 0>;
160			};
161
162			v2v8: ldo2 {
163				regulator-name = "v2v8";
164				regulator-min-microvolt = <2800000>;
165				regulator-max-microvolt = <2800000>;
166				interrupts = <IT_CURLIM_LDO2 0>;
167			};
168
169			vtt_ddr: ldo3 {
170				regulator-name = "vtt_ddr";
171				regulator-min-microvolt = <500000>;
172				regulator-max-microvolt = <750000>;
173				regulator-always-on;
174				regulator-over-current-protection;
175			};
176
177			vdd_usb: ldo4 {
178				regulator-name = "vdd_usb";
179				interrupts = <IT_CURLIM_LDO4 0>;
180			};
181
182			vdd_sd: ldo5 {
183				regulator-name = "vdd_sd";
184				regulator-min-microvolt = <2900000>;
185				regulator-max-microvolt = <2900000>;
186				interrupts = <IT_CURLIM_LDO5 0>;
187				regulator-boot-on;
188			};
189
190			v1v8: ldo6 {
191				regulator-name = "v1v8";
192				regulator-min-microvolt = <1800000>;
193				regulator-max-microvolt = <1800000>;
194				interrupts = <IT_CURLIM_LDO6 0>;
195				regulator-enable-ramp-delay = <300000>;
196			};
197
198			vref_ddr: vref_ddr {
199				regulator-name = "vref_ddr";
200				regulator-always-on;
201			};
202
203			bst_out: boost {
204				regulator-name = "bst_out";
205				interrupts = <IT_OCP_BOOST 0>;
206			};
207
208			vbus_otg: pwr_sw1 {
209				regulator-name = "vbus_otg";
210				interrupts = <IT_OCP_OTG 0>;
211				regulator-active-discharge = <1>;
212			};
213
214			vbus_sw: pwr_sw2 {
215				regulator-name = "vbus_sw";
216				interrupts = <IT_OCP_SWOUT 0>;
217				regulator-active-discharge = <1>;
218			};
219		};
220
221		onkey {
222			compatible = "st,stpmic1-onkey";
223			interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>;
224			interrupt-names = "onkey-falling", "onkey-rising";
225			status = "okay";
226		};
227
228		watchdog {
229			compatible = "st,stpmic1-wdt";
230			status = "disabled";
231		};
232	};
233
234	eeprom@53 {
235		compatible = "atmel,24c02";
236		reg = <0x53>;
237		pagesize = <16>;
238	};
239};
240
241&ipcc {
242	status = "okay";
243};
244
245&iwdg2 {
246	timeout-sec = <32>;
247	status = "okay";
248	secure-status = "disabled";
249};
250
251&m4_rproc {
252	memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
253			<&vdev0vring1>, <&vdev0buffer>;
254	mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
255	mbox-names = "vq0", "vq1", "shutdown";
256	interrupt-parent = <&exti>;
257	interrupts = <68 1>;
258	status = "okay";
259};
260
261&pwr_regulators {
262	vdd-supply = <&vdd>;
263	vdd_3v3_usbfs-supply = <&vdd_usb>;
264};
265
266&qspi {
267	pinctrl-names = "default", "sleep";
268	pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
269	pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
270	reg = <0x58003000 0x1000>, <0x70000000 0x200000>;
271	#address-cells = <1>;
272	#size-cells = <0>;
273	status = "okay";
274
275	flash0: flash@0 {
276		compatible = "jedec,spi-nor";
277		reg = <0>;
278		spi-rx-bus-width = <4>;
279		spi-max-frequency = <50000000>;
280		#address-cells = <1>;
281		#size-cells = <1>;
282	};
283};
284
285&rcc {
286	status = "okay";
287};
288
289&rng1 {
290	status = "okay";
291};
292
293&rtc {
294	status = "okay";
295};
296