1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) 2019-2020 Marek Vasut <marex@denx.de> 4 * Copyright (C) 2022 DH electronics GmbH 5 */ 6 7#include "stm32mp15-pinctrl.dtsi" 8#include "stm32mp15xxaa-pinctrl.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/mfd/st,stpmic1.h> 11 12/ { 13 aliases { 14 ethernet0 = ðernet0; 15 ethernet1 = &ksz8851; 16 rtc0 = &hwrtc; 17 rtc1 = &rtc; 18 }; 19 20 memory@c0000000 { 21 device_type = "memory"; 22 reg = <0xC0000000 0x40000000>; 23 }; 24 25 reserved-memory { 26 #address-cells = <1>; 27 #size-cells = <1>; 28 ranges; 29 30 mcuram2: mcuram2@10000000 { 31 compatible = "shared-dma-pool"; 32 reg = <0x10000000 0x40000>; 33 no-map; 34 }; 35 36 vdev0vring0: vdev0vring0@10040000 { 37 compatible = "shared-dma-pool"; 38 reg = <0x10040000 0x1000>; 39 no-map; 40 }; 41 42 vdev0vring1: vdev0vring1@10041000 { 43 compatible = "shared-dma-pool"; 44 reg = <0x10041000 0x1000>; 45 no-map; 46 }; 47 48 vdev0buffer: vdev0buffer@10042000 { 49 compatible = "shared-dma-pool"; 50 reg = <0x10042000 0x4000>; 51 no-map; 52 }; 53 54 mcuram: mcuram@30000000 { 55 compatible = "shared-dma-pool"; 56 reg = <0x30000000 0x40000>; 57 no-map; 58 }; 59 60 retram: retram@38000000 { 61 compatible = "shared-dma-pool"; 62 reg = <0x38000000 0x10000>; 63 no-map; 64 }; 65 }; 66 67 ethernet_vio: vioregulator { 68 compatible = "regulator-fixed"; 69 regulator-name = "vio"; 70 regulator-min-microvolt = <3300000>; 71 regulator-max-microvolt = <3300000>; 72 gpio = <&gpiog 3 GPIO_ACTIVE_LOW>; 73 regulator-always-on; 74 regulator-boot-on; 75 vin-supply = <&vdd>; 76 }; 77}; 78 79&adc { 80 vdd-supply = <&vdd>; 81 vdda-supply = <&vdda>; 82 vref-supply = <&vdda>; 83 status = "okay"; 84 85 adc1: adc@0 { 86 st,min-sample-time-nsecs = <5000>; 87 st,adc-channels = <0>; 88 status = "okay"; 89 }; 90 91 adc2: adc@100 { 92 st,adc-channels = <1>; 93 st,min-sample-time-nsecs = <5000>; 94 status = "okay"; 95 }; 96}; 97 98&crc1 { 99 status = "okay"; 100}; 101 102&dac { 103 pinctrl-names = "default"; 104 pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; 105 vref-supply = <&vdda>; 106 status = "okay"; 107 108 dac1: dac@1 { 109 status = "okay"; 110 }; 111 dac2: dac@2 { 112 status = "okay"; 113 }; 114}; 115 116&dts { 117 status = "okay"; 118}; 119 120ðernet0 { 121 status = "okay"; 122 pinctrl-0 = <ðernet0_rmii_pins_c &mco2_pins_a>; 123 pinctrl-1 = <ðernet0_rmii_sleep_pins_c &mco2_sleep_pins_a>; 124 pinctrl-names = "default", "sleep"; 125 phy-mode = "rmii"; 126 max-speed = <100>; 127 phy-handle = <&phy0>; 128 129 mdio0 { 130 #address-cells = <1>; 131 #size-cells = <0>; 132 compatible = "snps,dwmac-mdio"; 133 134 phy0: ethernet-phy@1 { 135 reg = <1>; 136 /* LAN8710Ai */ 137 compatible = "ethernet-phy-id0007.c0f0", 138 "ethernet-phy-ieee802.3-c22"; 139 clocks = <&rcc CK_MCO2>; 140 reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; 141 reset-assert-us = <500>; 142 reset-deassert-us = <500>; 143 smsc,disable-energy-detect; 144 interrupt-parent = <&gpioi>; 145 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 146 }; 147 }; 148}; 149 150&etzpc { 151 st,decprot = 152 <DECPROT(STM32MP1_ETZPC_USART1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 153 <DECPROT(STM32MP1_ETZPC_SPI6_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 154 <DECPROT(STM32MP1_ETZPC_I2C4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 155 <DECPROT(STM32MP1_ETZPC_I2C6_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 156 <DECPROT(STM32MP1_ETZPC_RNG1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 157 <DECPROT(STM32MP1_ETZPC_HASH1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 158 <DECPROT(STM32MP1_ETZPC_CRYP1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 159 <DECPROT(STM32MP1_ETZPC_DDRCTRL_ID, DECPROT_NS_R_S_W, DECPROT_LOCK)>, 160 <DECPROT(STM32MP1_ETZPC_DDRPHYC_ID, DECPROT_NS_R_S_W, DECPROT_LOCK)>, 161 <DECPROT(STM32MP1_ETZPC_STGENC_ID, DECPROT_S_RW, DECPROT_LOCK)>, 162 <DECPROT(STM32MP1_ETZPC_BKPSRAM_ID, DECPROT_S_RW, DECPROT_LOCK)>, 163 <DECPROT(STM32MP1_ETZPC_IWDG1_ID, DECPROT_NS_RW, DECPROT_LOCK)>; 164}; 165 166&fmc { 167 pinctrl-names = "default", "sleep"; 168 pinctrl-0 = <&fmc_pins_b>; 169 pinctrl-1 = <&fmc_sleep_pins_b>; 170 status = "okay"; 171 172 ksz8851: ethernet@1,0 { 173 compatible = "micrel,ks8851-mll"; 174 reg = <1 0x0 0x2>, <1 0x2 0x20000>; 175 interrupt-parent = <&gpioc>; 176 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 177 bank-width = <2>; 178 179 /* Timing values are in nS */ 180 st,fmc2-ebi-cs-mux-enable; 181 st,fmc2-ebi-cs-transaction-type = <4>; 182 st,fmc2-ebi-cs-buswidth = <16>; 183 st,fmc2-ebi-cs-address-setup-ns = <5>; 184 st,fmc2-ebi-cs-address-hold-ns = <5>; 185 st,fmc2-ebi-cs-bus-turnaround-ns = <5>; 186 st,fmc2-ebi-cs-data-setup-ns = <45>; 187 st,fmc2-ebi-cs-data-hold-ns = <1>; 188 st,fmc2-ebi-cs-write-address-setup-ns = <5>; 189 st,fmc2-ebi-cs-write-address-hold-ns = <5>; 190 st,fmc2-ebi-cs-write-bus-turnaround-ns = <5>; 191 st,fmc2-ebi-cs-write-data-setup-ns = <45>; 192 st,fmc2-ebi-cs-write-data-hold-ns = <1>; 193 }; 194}; 195 196&gpioa { 197 gpio-line-names = "", "", "", "", 198 "", "", "DHCOM-K", "", 199 "", "", "", "", 200 "", "", "", ""; 201}; 202 203&gpiob { 204 gpio-line-names = "", "", "", "", 205 "", "", "", "", 206 "DHCOM-Q", "", "", "", 207 "", "", "", ""; 208}; 209 210&gpioc { 211 gpio-line-names = "", "", "", "", 212 "", "", "DHCOM-E", "", 213 "", "", "", "", 214 "", "", "", ""; 215}; 216 217&gpiod { 218 gpio-line-names = "", "", "", "", 219 "", "", "DHCOM-B", "", 220 "", "", "", "DHCOM-F", 221 "DHCOM-D", "", "", ""; 222}; 223 224&gpioe { 225 gpio-line-names = "", "", "", "", 226 "", "", "DHCOM-P", "", 227 "", "", "", "", 228 "", "", "", ""; 229}; 230 231&gpiof { 232 gpio-line-names = "", "", "", "DHCOM-A", 233 "", "", "", "", 234 "", "", "", "", 235 "", "", "", ""; 236}; 237 238&gpiog { 239 gpio-line-names = "DHCOM-C", "", "", "", 240 "", "", "", "", 241 "DHCOM-L", "", "", "", 242 "", "", "", ""; 243}; 244 245&gpioh { 246 gpio-line-names = "", "", "", "", 247 "", "", "", "DHCOM-N", 248 "DHCOM-J", "DHCOM-W", "DHCOM-V", "DHCOM-U", 249 "DHCOM-T", "", "DHCOM-S", ""; 250}; 251 252&gpioi { 253 gpio-line-names = "DHCOM-G", "DHCOM-O", "DHCOM-H", "DHCOM-I", 254 "DHCOM-R", "DHCOM-M", "", "", 255 "", "", "", "", 256 "", "", "", ""; 257}; 258 259&i2c4 { 260 pinctrl-names = "default"; 261 pinctrl-0 = <&i2c4_pins_a>; 262 i2c-scl-rising-time-ns = <185>; 263 i2c-scl-falling-time-ns = <20>; 264 status = "okay"; 265 /* spare dmas for other usage */ 266 /delete-property/dmas; 267 /delete-property/dma-names; 268 269 hwrtc: rtc@32 { 270 compatible = "microcrystal,rv8803"; 271 reg = <0x32>; 272 }; 273 274 pmic: stpmic@33 { 275 compatible = "st,stpmic1"; 276 reg = <0x33>; 277 interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; 278 interrupt-controller; 279 #interrupt-cells = <2>; 280 status = "okay"; 281 282 regulators { 283 compatible = "st,stpmic1-regulators"; 284 ldo1-supply = <&v3v3>; 285 ldo2-supply = <&v3v3>; 286 ldo3-supply = <&vdd_ddr>; 287 ldo5-supply = <&v3v3>; 288 ldo6-supply = <&v3v3>; 289 pwr_sw1-supply = <&bst_out>; 290 pwr_sw2-supply = <&bst_out>; 291 292 vddcore: buck1 { 293 regulator-name = "vddcore"; 294 regulator-min-microvolt = <800000>; 295 regulator-max-microvolt = <1350000>; 296 regulator-always-on; 297 regulator-initial-mode = <0>; 298 regulator-over-current-protection; 299 }; 300 301 vdd_ddr: buck2 { 302 regulator-name = "vdd_ddr"; 303 regulator-min-microvolt = <1350000>; 304 regulator-max-microvolt = <1350000>; 305 regulator-always-on; 306 regulator-initial-mode = <0>; 307 regulator-over-current-protection; 308 }; 309 310 vdd: buck3 { 311 regulator-name = "vdd"; 312 regulator-min-microvolt = <3300000>; 313 regulator-max-microvolt = <3300000>; 314 regulator-always-on; 315 st,mask-reset; 316 regulator-initial-mode = <0>; 317 regulator-over-current-protection; 318 }; 319 320 v3v3: buck4 { 321 regulator-name = "v3v3"; 322 regulator-min-microvolt = <3300000>; 323 regulator-max-microvolt = <3300000>; 324 regulator-always-on; 325 regulator-over-current-protection; 326 regulator-initial-mode = <0>; 327 }; 328 329 vdda: ldo1 { 330 regulator-name = "vdda"; 331 regulator-always-on; 332 regulator-min-microvolt = <2900000>; 333 regulator-max-microvolt = <2900000>; 334 interrupts = <IT_CURLIM_LDO1 0>; 335 }; 336 337 v2v8: ldo2 { 338 regulator-name = "v2v8"; 339 regulator-min-microvolt = <2800000>; 340 regulator-max-microvolt = <2800000>; 341 interrupts = <IT_CURLIM_LDO2 0>; 342 }; 343 344 vtt_ddr: ldo3 { 345 regulator-name = "vtt_ddr"; 346 regulator-min-microvolt = <500000>; 347 regulator-max-microvolt = <750000>; 348 regulator-always-on; 349 regulator-over-current-protection; 350 }; 351 352 vdd_usb: ldo4 { 353 regulator-name = "vdd_usb"; 354 interrupts = <IT_CURLIM_LDO4 0>; 355 }; 356 357 vdd_sd: ldo5 { 358 regulator-name = "vdd_sd"; 359 regulator-min-microvolt = <2900000>; 360 regulator-max-microvolt = <2900000>; 361 interrupts = <IT_CURLIM_LDO5 0>; 362 regulator-boot-on; 363 }; 364 365 v1v8: ldo6 { 366 regulator-name = "v1v8"; 367 regulator-min-microvolt = <1800000>; 368 regulator-max-microvolt = <1800000>; 369 interrupts = <IT_CURLIM_LDO6 0>; 370 }; 371 372 vref_ddr: vref_ddr { 373 regulator-name = "vref_ddr"; 374 regulator-always-on; 375 }; 376 377 bst_out: boost { 378 regulator-name = "bst_out"; 379 interrupts = <IT_OCP_BOOST 0>; 380 }; 381 382 vbus_otg: pwr_sw1 { 383 regulator-name = "vbus_otg"; 384 interrupts = <IT_OCP_OTG 0>; 385 }; 386 387 vbus_sw: pwr_sw2 { 388 regulator-name = "vbus_sw"; 389 interrupts = <IT_OCP_SWOUT 0>; 390 regulator-active-discharge = <1>; 391 }; 392 }; 393 394 onkey { 395 compatible = "st,stpmic1-onkey"; 396 interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>; 397 interrupt-names = "onkey-falling", "onkey-rising"; 398 power-off-time-sec = <10>; 399 status = "okay"; 400 }; 401 402 watchdog { 403 compatible = "st,stpmic1-wdt"; 404 status = "disabled"; 405 }; 406 }; 407 408 touchscreen@49 { 409 compatible = "ti,tsc2004"; 410 reg = <0x49>; 411 vio-supply = <&v3v3>; 412 interrupts-extended = <&gpioh 15 IRQ_TYPE_EDGE_FALLING>; 413 }; 414 415 eeprom@50 { 416 compatible = "atmel,24c02"; 417 reg = <0x50>; 418 pagesize = <16>; 419 }; 420}; 421 422&ipcc { 423 status = "okay"; 424}; 425 426&iwdg2 { 427 timeout-sec = <32>; 428 status = "okay"; 429 secure-status = "disabled"; 430}; 431 432&m4_rproc { 433 memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, 434 <&vdev0vring1>, <&vdev0buffer>; 435 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; 436 mbox-names = "vq0", "vq1", "shutdown"; 437 interrupt-parent = <&exti>; 438 interrupts = <68 1>; 439 status = "okay"; 440}; 441 442&pwr_regulators { 443 vdd-supply = <&vdd>; 444 vdd_3v3_usbfs-supply = <&vdd_usb>; 445}; 446 447&qspi { 448 pinctrl-names = "default", "sleep"; 449 pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; 450 pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; 451 reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 status = "okay"; 455 456 flash0: flash@0 { 457 compatible = "jedec,spi-nor"; 458 reg = <0>; 459 spi-rx-bus-width = <4>; 460 spi-max-frequency = <108000000>; 461 #address-cells = <1>; 462 #size-cells = <1>; 463 }; 464}; 465 466&rcc { 467 /* Connect MCO2 output to ETH_RX_CLK input via pad-pad connection */ 468 /* clocks = <&rcc CK_MCO2>; Not supported in OP-TEE OS */ 469 /* clock-names = "ETH_RX_CLK/ETH_REF_CLK"; Not supported */ 470 471 /* 472 * Set PLL4P output to 100 MHz to supply SDMMC with faster clock, 473 * set MCO2 output to 50 MHz to supply ETHRX clock with PLL4P/2, 474 * so that MCO2 behaves as a divider for the ETHRX clock here. 475 */ 476 /* assigned-clocks = <&rcc CK_MCO2>, <&rcc PLL4_P>; Not supported */ 477 /* assigned-clock-parents = <&rcc PLL4_P>; Not supported */ 478 /* assigned-clock-rates = <50000000>, <100000000>; Not supported */ 479 480 status = "okay"; 481}; 482 483&rng1 { 484 status = "okay"; 485}; 486 487&rtc { 488 status = "okay"; 489}; 490 491&sdmmc1 { 492 pinctrl-names = "default", "opendrain", "sleep", "init"; 493 pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; 494 pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; 495 pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; 496 pinctrl-3 = <&sdmmc1_b4_init_pins_a &sdmmc1_dir_init_pins_a>; 497 cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; 498 disable-wp; 499 st,sig-dir; 500 st,neg-edge; 501 st,use-ckin; 502 st,cmd-gpios = <&gpiod 2 0>; 503 st,ck-gpios = <&gpioc 12 0>; 504 st,ckin-gpios = <&gpioe 4 0>; 505 bus-width = <4>; 506 vmmc-supply = <&vdd_sd>; 507 status = "okay"; 508}; 509 510&sdmmc1_b4_pins_a { 511 /* 512 * SD bus pull-up resistors: 513 * - optional on SoMs with SD voltage translator 514 * - mandatory on SoMs without SD voltage translator 515 */ 516 pins1 { 517 bias-pull-up; 518 }; 519 pins2 { 520 bias-pull-up; 521 }; 522}; 523 524&sdmmc2 { 525 pinctrl-names = "default", "opendrain", "sleep"; 526 pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; 527 pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; 528 pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; 529 non-removable; 530 no-sd; 531 no-sdio; 532 st,neg-edge; 533 bus-width = <8>; 534 vmmc-supply = <&v3v3>; 535 vqmmc-supply = <&v3v3>; 536 mmc-ddr-3_3v; 537 status = "okay"; 538}; 539 540&sdmmc3 { 541 pinctrl-names = "default", "opendrain", "sleep"; 542 pinctrl-0 = <&sdmmc3_b4_pins_a>; 543 pinctrl-1 = <&sdmmc3_b4_od_pins_a>; 544 pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; 545 broken-cd; 546 st,neg-edge; 547 bus-width = <4>; 548 vmmc-supply = <&v3v3>; 549 vqmmc-supply = <&v3v3>; 550 mmc-ddr-3_3v; 551 status = "okay"; 552}; 553 554&uart4 { 555 pinctrl-names = "default"; 556 pinctrl-0 = <&uart4_pins_a>; 557 /delete-property/dmas; 558 /delete-property/dma-names; 559 status = "okay"; 560}; 561