1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2017-2024 - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/stm32mp1-clks.h> 8#include <dt-bindings/reset/stm32mp1-resets.h> 9#include <dt-bindings/firewall/stm32mp15-etzpc.h> 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a7"; 21 clock-frequency = <650000000>; 22 device_type = "cpu"; 23 reg = <0>; 24 }; 25 }; 26 27 arm-pmu { 28 compatible = "arm,cortex-a7-pmu"; 29 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 30 interrupt-affinity = <&cpu0>; 31 interrupt-parent = <&intc>; 32 }; 33 34 psci { 35 compatible = "arm,psci-1.0"; 36 method = "smc"; 37 }; 38 39 intc: interrupt-controller@a0021000 { 40 compatible = "arm,cortex-a7-gic"; 41 #interrupt-cells = <3>; 42 interrupt-controller; 43 reg = <0xa0021000 0x1000>, 44 <0xa0022000 0x2000>; 45 }; 46 47 timer { 48 compatible = "arm,armv7-timer"; 49 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 50 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 51 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 52 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 53 interrupt-parent = <&intc>; 54 }; 55 56 clocks { 57 clk_hse: clk-hse { 58 #clock-cells = <0>; 59 compatible = "fixed-clock"; 60 clock-frequency = <24000000>; 61 }; 62 63 clk_hsi: clk-hsi { 64 #clock-cells = <0>; 65 compatible = "fixed-clock"; 66 clock-frequency = <64000000>; 67 }; 68 69 clk_lse: clk-lse { 70 #clock-cells = <0>; 71 compatible = "fixed-clock"; 72 clock-frequency = <32768>; 73 }; 74 75 clk_lsi: clk-lsi { 76 #clock-cells = <0>; 77 compatible = "fixed-clock"; 78 clock-frequency = <32000>; 79 }; 80 81 clk_csi: clk-csi { 82 #clock-cells = <0>; 83 compatible = "fixed-clock"; 84 clock-frequency = <4000000>; 85 }; 86 }; 87 88 thermal-zones { 89 cpu_thermal: cpu-thermal { 90 polling-delay-passive = <0>; 91 polling-delay = <0>; 92 thermal-sensors = <&dts>; 93 94 trips { 95 cpu_alert1: cpu-alert1 { 96 temperature = <85000>; 97 hysteresis = <0>; 98 type = "passive"; 99 }; 100 101 cpu-crit { 102 temperature = <120000>; 103 hysteresis = <0>; 104 type = "critical"; 105 }; 106 }; 107 108 cooling-maps { 109 }; 110 }; 111 }; 112 113 booster: regulator-booster { 114 compatible = "st,stm32mp1-booster"; 115 st,syscfg = <&syscfg>; 116 status = "disabled"; 117 }; 118 119 soc { 120 compatible = "simple-bus"; 121 #address-cells = <1>; 122 #size-cells = <1>; 123 interrupt-parent = <&intc>; 124 ranges; 125 126 ipcc: mailbox@4c001000 { 127 compatible = "st,stm32mp1-ipcc"; 128 #mbox-cells = <1>; 129 reg = <0x4c001000 0x400>; 130 st,proc-id = <0>; 131 interrupts-extended = 132 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 133 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 134 <&exti 61 1>; 135 interrupt-names = "rx", "tx", "wakeup"; 136 clocks = <&rcc IPCC>; 137 wakeup-source; 138 status = "disabled"; 139 }; 140 141 rcc: rcc@50000000 { 142 compatible = "st,stm32mp1-rcc", "syscon"; 143 reg = <0x50000000 0x1000>; 144 #clock-cells = <1>; 145 #reset-cells = <1>; 146 }; 147 148 pwr_regulators: pwr@50001000 { 149 compatible = "st,stm32mp1,pwr-reg"; 150 reg = <0x50001000 0x10>; 151 152 reg11: reg11 { 153 regulator-name = "reg11"; 154 regulator-min-microvolt = <1100000>; 155 regulator-max-microvolt = <1100000>; 156 }; 157 158 reg18: reg18 { 159 regulator-name = "reg18"; 160 regulator-min-microvolt = <1800000>; 161 regulator-max-microvolt = <1800000>; 162 }; 163 164 usb33: usb33 { 165 regulator-name = "usb33"; 166 regulator-min-microvolt = <3300000>; 167 regulator-max-microvolt = <3300000>; 168 }; 169 }; 170 171 pwr_mcu: pwr_mcu@50001014 { 172 compatible = "st,stm32mp151-pwr-mcu", "syscon"; 173 reg = <0x50001014 0x4>; 174 }; 175 176 exti: interrupt-controller@5000d000 { 177 compatible = "st,stm32mp1-exti", "syscon"; 178 interrupt-controller; 179 #interrupt-cells = <2>; 180 reg = <0x5000d000 0x400>; 181 }; 182 183 syscfg: syscon@50020000 { 184 compatible = "st,stm32mp157-syscfg", "syscon"; 185 reg = <0x50020000 0x400>; 186 clocks = <&rcc SYSCFG>; 187 }; 188 189 dts: thermal@50028000 { 190 compatible = "st,stm32-thermal"; 191 reg = <0x50028000 0x100>; 192 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 193 clocks = <&rcc TMPSENS>; 194 clock-names = "pclk"; 195 #thermal-sensor-cells = <0>; 196 status = "disabled"; 197 }; 198 199 mdma1: dma-controller@58000000 { 200 compatible = "st,stm32h7-mdma"; 201 reg = <0x58000000 0x1000>; 202 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 203 clocks = <&rcc MDMA>; 204 resets = <&rcc MDMA_R>; 205 #dma-cells = <5>; 206 dma-channels = <32>; 207 dma-requests = <48>; 208 }; 209 210 sdmmc1: mmc@58005000 { 211 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 212 arm,primecell-periphid = <0x00253180>; 213 reg = <0x58005000 0x1000>; 214 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 215 interrupt-names = "cmd_irq"; 216 clocks = <&rcc SDMMC1_K>; 217 clock-names = "apb_pclk"; 218 resets = <&rcc SDMMC1_R>; 219 cap-sd-highspeed; 220 cap-mmc-highspeed; 221 max-frequency = <120000000>; 222 status = "disabled"; 223 }; 224 225 sdmmc2: mmc@58007000 { 226 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 227 arm,primecell-periphid = <0x00253180>; 228 reg = <0x58007000 0x1000>; 229 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 230 interrupt-names = "cmd_irq"; 231 clocks = <&rcc SDMMC2_K>; 232 clock-names = "apb_pclk"; 233 resets = <&rcc SDMMC2_R>; 234 cap-sd-highspeed; 235 cap-mmc-highspeed; 236 max-frequency = <120000000>; 237 status = "disabled"; 238 }; 239 240 crc1: crc@58009000 { 241 compatible = "st,stm32f7-crc"; 242 reg = <0x58009000 0x400>; 243 clocks = <&rcc CRC1>; 244 status = "disabled"; 245 }; 246 247 usbh_ohci: usb@5800c000 { 248 compatible = "generic-ohci"; 249 reg = <0x5800c000 0x1000>; 250 clocks = <&usbphyc>, <&rcc USBH>; 251 resets = <&rcc USBH_R>; 252 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 253 status = "disabled"; 254 }; 255 256 usbh_ehci: usb@5800d000 { 257 compatible = "generic-ehci"; 258 reg = <0x5800d000 0x1000>; 259 clocks = <&usbphyc>, <&rcc USBH>; 260 resets = <&rcc USBH_R>; 261 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 262 companion = <&usbh_ohci>; 263 status = "disabled"; 264 }; 265 266 ltdc: display-controller@5a001000 { 267 compatible = "st,stm32-ltdc"; 268 reg = <0x5a001000 0x400>; 269 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 271 clocks = <&rcc LTDC_PX>; 272 clock-names = "lcd"; 273 resets = <&rcc LTDC_R>; 274 status = "disabled"; 275 276 port { 277 #address-cells = <1>; 278 #size-cells = <0>; 279 }; 280 }; 281 282 iwdg2: watchdog@5a002000 { 283 compatible = "st,stm32mp1-iwdg"; 284 reg = <0x5a002000 0x400>; 285 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&rcc IWDG2>, <&rcc CK_LSI>; 287 clock-names = "pclk", "lsi"; 288 status = "disabled"; 289 }; 290 291 usbphyc: usbphyc@5a006000 { 292 #address-cells = <1>; 293 #size-cells = <0>; 294 #clock-cells = <0>; 295 compatible = "st,stm32mp1-usbphyc"; 296 reg = <0x5a006000 0x1000>; 297 clocks = <&rcc USBPHY_K>; 298 resets = <&rcc USBPHY_R>; 299 vdda1v1-supply = <®11>; 300 vdda1v8-supply = <®18>; 301 status = "disabled"; 302 303 usbphyc_port0: usb-phy@0 { 304 #phy-cells = <0>; 305 reg = <0>; 306 }; 307 308 usbphyc_port1: usb-phy@1 { 309 #phy-cells = <1>; 310 reg = <1>; 311 }; 312 }; 313 314 rtc: rtc@5c004000 { 315 compatible = "st,stm32mp1-rtc"; 316 reg = <0x5c004000 0x400>; 317 clocks = <&rcc RTCAPB>, <&rcc RTC>; 318 clock-names = "pclk", "rtc_ck"; 319 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; 320 status = "disabled"; 321 }; 322 323 bsec: efuse@5c005000 { 324 compatible = "st,stm32mp15-bsec"; 325 reg = <0x5c005000 0x400>; 326 #address-cells = <1>; 327 #size-cells = <1>; 328 329 cfg0_otp: cfg0_otp@0 { 330 reg = <0x0 0x1>; 331 }; 332 part_number_otp: part_number_otp@4 { 333 reg = <0x4 0x1>; 334 }; 335 monotonic_otp: monotonic_otp@10 { 336 reg = <0x10 0x4>; 337 }; 338 nand_otp: nand_otp@24 { 339 reg = <0x24 0x4>; 340 }; 341 uid_otp: uid_otp@34 { 342 reg = <0x34 0xc>; 343 }; 344 package_otp: package_otp@40 { 345 reg = <0x40 0x4>; 346 }; 347 hw2_otp: hw2_otp@48 { 348 reg = <0x48 0x4>; 349 }; 350 ts_cal1: calib@5c { 351 reg = <0x5c 0x2>; 352 }; 353 ts_cal2: calib@5e { 354 reg = <0x5e 0x2>; 355 }; 356 pkh_otp: pkh_otp@60 { 357 reg = <0x60 0x20>; 358 }; 359 ethernet_mac_address: mac@e4 { 360 reg = <0xe4 0x8>; 361 st,non-secure-otp; 362 }; 363 }; 364 365 tamp: tamp@5c00a000 { 366 compatible = "st,stm32-tamp", "syscon", "simple-mfd"; 367 reg = <0x5c00a000 0x400>; 368 clocks = <&rcc RTCAPB>; 369 }; 370 371 /* 372 * Break node order to solve dependency probe issue between 373 * pinctrl and exti. 374 */ 375 pinctrl: pinctrl@50002000 { 376 #address-cells = <1>; 377 #size-cells = <1>; 378 compatible = "st,stm32mp157-pinctrl"; 379 ranges = <0 0x50002000 0xa400>; 380 interrupt-parent = <&exti>; 381 st,syscfg = <&exti 0x60 0xff>; 382 pins-are-numbered; 383 384 gpioa: gpio@50002000 { 385 gpio-controller; 386 #gpio-cells = <2>; 387 interrupt-controller; 388 #interrupt-cells = <2>; 389 reg = <0x0 0x400>; 390 clocks = <&rcc GPIOA>; 391 st,bank-name = "GPIOA"; 392 status = "disabled"; 393 }; 394 395 gpiob: gpio@50003000 { 396 gpio-controller; 397 #gpio-cells = <2>; 398 interrupt-controller; 399 #interrupt-cells = <2>; 400 reg = <0x1000 0x400>; 401 clocks = <&rcc GPIOB>; 402 st,bank-name = "GPIOB"; 403 status = "disabled"; 404 }; 405 406 gpioc: gpio@50004000 { 407 gpio-controller; 408 #gpio-cells = <2>; 409 interrupt-controller; 410 #interrupt-cells = <2>; 411 reg = <0x2000 0x400>; 412 clocks = <&rcc GPIOC>; 413 st,bank-name = "GPIOC"; 414 status = "disabled"; 415 }; 416 417 gpiod: gpio@50005000 { 418 gpio-controller; 419 #gpio-cells = <2>; 420 interrupt-controller; 421 #interrupt-cells = <2>; 422 reg = <0x3000 0x400>; 423 clocks = <&rcc GPIOD>; 424 st,bank-name = "GPIOD"; 425 status = "disabled"; 426 }; 427 428 gpioe: gpio@50006000 { 429 gpio-controller; 430 #gpio-cells = <2>; 431 interrupt-controller; 432 #interrupt-cells = <2>; 433 reg = <0x4000 0x400>; 434 clocks = <&rcc GPIOE>; 435 st,bank-name = "GPIOE"; 436 status = "disabled"; 437 }; 438 439 gpiof: gpio@50007000 { 440 gpio-controller; 441 #gpio-cells = <2>; 442 interrupt-controller; 443 #interrupt-cells = <2>; 444 reg = <0x5000 0x400>; 445 clocks = <&rcc GPIOF>; 446 st,bank-name = "GPIOF"; 447 status = "disabled"; 448 }; 449 450 gpiog: gpio@50008000 { 451 gpio-controller; 452 #gpio-cells = <2>; 453 interrupt-controller; 454 #interrupt-cells = <2>; 455 reg = <0x6000 0x400>; 456 clocks = <&rcc GPIOG>; 457 st,bank-name = "GPIOG"; 458 status = "disabled"; 459 }; 460 461 gpioh: gpio@50009000 { 462 gpio-controller; 463 #gpio-cells = <2>; 464 interrupt-controller; 465 #interrupt-cells = <2>; 466 reg = <0x7000 0x400>; 467 clocks = <&rcc GPIOH>; 468 st,bank-name = "GPIOH"; 469 status = "disabled"; 470 }; 471 472 gpioi: gpio@5000a000 { 473 gpio-controller; 474 #gpio-cells = <2>; 475 interrupt-controller; 476 #interrupt-cells = <2>; 477 reg = <0x8000 0x400>; 478 clocks = <&rcc GPIOI>; 479 st,bank-name = "GPIOI"; 480 status = "disabled"; 481 }; 482 483 gpioj: gpio@5000b000 { 484 gpio-controller; 485 #gpio-cells = <2>; 486 interrupt-controller; 487 #interrupt-cells = <2>; 488 reg = <0x9000 0x400>; 489 clocks = <&rcc GPIOJ>; 490 st,bank-name = "GPIOJ"; 491 status = "disabled"; 492 }; 493 494 gpiok: gpio@5000c000 { 495 gpio-controller; 496 #gpio-cells = <2>; 497 interrupt-controller; 498 #interrupt-cells = <2>; 499 reg = <0xa000 0x400>; 500 clocks = <&rcc GPIOK>; 501 st,bank-name = "GPIOK"; 502 status = "disabled"; 503 }; 504 }; 505 506 pinctrl_z: pinctrl@54004000 { 507 #address-cells = <1>; 508 #size-cells = <1>; 509 compatible = "st,stm32mp157-z-pinctrl"; 510 ranges = <0 0x54004000 0x400>; 511 pins-are-numbered; 512 interrupt-parent = <&exti>; 513 st,syscfg = <&exti 0x60 0xff>; 514 515 gpioz: gpio@54004000 { 516 gpio-controller; 517 #gpio-cells = <2>; 518 interrupt-controller; 519 #interrupt-cells = <2>; 520 reg = <0 0x400>; 521 clocks = <&rcc GPIOZ>; 522 st,bank-name = "GPIOZ"; 523 st,bank-ioport = <11>; 524 status = "disabled"; 525 }; 526 }; 527 528 tzc400: tzc@5c006000 { 529 compatible = "st,stm32mp1-tzc"; 530 reg = <0x5c006000 0x1000>; 531 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&rcc TZC1>, <&rcc TZC2>; 533 st,mem-map = <0xc0000000 0x40000000>; 534 }; 535 536 etzpc: etzpc@5c007000 { 537 compatible = "st,stm32-etzpc", "simple-bus"; 538 reg = <0x5C007000 0x400>; 539 clocks = <&rcc TZPC>; 540 #address-cells = <1>; 541 #size-cells = <1>; 542 #access-controller-cells = <1>; 543 544 timers2: timer@40000000 { 545 #address-cells = <1>; 546 #size-cells = <0>; 547 compatible = "st,stm32-timers"; 548 reg = <0x40000000 0x400>; 549 clocks = <&rcc TIM2_K>; 550 clock-names = "int"; 551 dmas = <&dmamux1 18 0x400 0x1>, 552 <&dmamux1 19 0x400 0x1>, 553 <&dmamux1 20 0x400 0x1>, 554 <&dmamux1 21 0x400 0x1>, 555 <&dmamux1 22 0x400 0x1>; 556 dma-names = "ch1", "ch2", "ch3", "ch4", "up"; 557 access-controllers = <&etzpc STM32MP1_ETZPC_TIM2_ID>; 558 status = "disabled"; 559 560 pwm { 561 compatible = "st,stm32-pwm"; 562 #pwm-cells = <3>; 563 status = "disabled"; 564 }; 565 566 timer@1 { 567 compatible = "st,stm32h7-timer-trigger"; 568 reg = <1>; 569 status = "disabled"; 570 }; 571 572 counter { 573 compatible = "st,stm32-timer-counter"; 574 status = "disabled"; 575 }; 576 }; 577 578 timers3: timer@40001000 { 579 #address-cells = <1>; 580 #size-cells = <0>; 581 compatible = "st,stm32-timers"; 582 reg = <0x40001000 0x400>; 583 clocks = <&rcc TIM3_K>; 584 clock-names = "int"; 585 dmas = <&dmamux1 23 0x400 0x1>, 586 <&dmamux1 24 0x400 0x1>, 587 <&dmamux1 25 0x400 0x1>, 588 <&dmamux1 26 0x400 0x1>, 589 <&dmamux1 27 0x400 0x1>, 590 <&dmamux1 28 0x400 0x1>; 591 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 592 access-controllers = <&etzpc STM32MP1_ETZPC_TIM3_ID>; 593 status = "disabled"; 594 595 pwm { 596 compatible = "st,stm32-pwm"; 597 #pwm-cells = <3>; 598 status = "disabled"; 599 }; 600 601 timer@2 { 602 compatible = "st,stm32h7-timer-trigger"; 603 reg = <2>; 604 status = "disabled"; 605 }; 606 607 counter { 608 compatible = "st,stm32-timer-counter"; 609 status = "disabled"; 610 }; 611 }; 612 613 timers4: timer@40002000 { 614 #address-cells = <1>; 615 #size-cells = <0>; 616 compatible = "st,stm32-timers"; 617 reg = <0x40002000 0x400>; 618 clocks = <&rcc TIM4_K>; 619 clock-names = "int"; 620 dmas = <&dmamux1 29 0x400 0x1>, 621 <&dmamux1 30 0x400 0x1>, 622 <&dmamux1 31 0x400 0x1>, 623 <&dmamux1 32 0x400 0x1>; 624 dma-names = "ch1", "ch2", "ch3", "ch4"; 625 access-controllers = <&etzpc STM32MP1_ETZPC_TIM4_ID>; 626 status = "disabled"; 627 628 pwm { 629 compatible = "st,stm32-pwm"; 630 #pwm-cells = <3>; 631 status = "disabled"; 632 }; 633 634 timer@3 { 635 compatible = "st,stm32h7-timer-trigger"; 636 reg = <3>; 637 status = "disabled"; 638 }; 639 640 counter { 641 compatible = "st,stm32-timer-counter"; 642 status = "disabled"; 643 }; 644 }; 645 646 timers5: timer@40003000 { 647 #address-cells = <1>; 648 #size-cells = <0>; 649 compatible = "st,stm32-timers"; 650 reg = <0x40003000 0x400>; 651 clocks = <&rcc TIM5_K>; 652 clock-names = "int"; 653 dmas = <&dmamux1 55 0x400 0x1>, 654 <&dmamux1 56 0x400 0x1>, 655 <&dmamux1 57 0x400 0x1>, 656 <&dmamux1 58 0x400 0x1>, 657 <&dmamux1 59 0x400 0x1>, 658 <&dmamux1 60 0x400 0x1>; 659 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 660 access-controllers = <&etzpc STM32MP1_ETZPC_TIM5_ID>; 661 status = "disabled"; 662 663 pwm { 664 compatible = "st,stm32-pwm"; 665 #pwm-cells = <3>; 666 status = "disabled"; 667 }; 668 669 timer@4 { 670 compatible = "st,stm32h7-timer-trigger"; 671 reg = <4>; 672 status = "disabled"; 673 }; 674 675 counter { 676 compatible = "st,stm32-timer-counter"; 677 status = "disabled"; 678 }; 679 }; 680 681 timers6: timer@40004000 { 682 #address-cells = <1>; 683 #size-cells = <0>; 684 compatible = "st,stm32-timers"; 685 reg = <0x40004000 0x400>; 686 clocks = <&rcc TIM6_K>; 687 clock-names = "int"; 688 dmas = <&dmamux1 69 0x400 0x1>; 689 dma-names = "up"; 690 access-controllers = <&etzpc STM32MP1_ETZPC_TIM6_ID>; 691 status = "disabled"; 692 693 timer@5 { 694 compatible = "st,stm32h7-timer-trigger"; 695 reg = <5>; 696 status = "disabled"; 697 }; 698 }; 699 700 timers7: timer@40005000 { 701 #address-cells = <1>; 702 #size-cells = <0>; 703 compatible = "st,stm32-timers"; 704 reg = <0x40005000 0x400>; 705 clocks = <&rcc TIM7_K>; 706 clock-names = "int"; 707 dmas = <&dmamux1 70 0x400 0x1>; 708 dma-names = "up"; 709 access-controllers = <&etzpc STM32MP1_ETZPC_TIM7_ID>; 710 status = "disabled"; 711 712 timer@6 { 713 compatible = "st,stm32h7-timer-trigger"; 714 reg = <6>; 715 status = "disabled"; 716 }; 717 }; 718 719 timers12: timer@40006000 { 720 #address-cells = <1>; 721 #size-cells = <0>; 722 compatible = "st,stm32-timers"; 723 reg = <0x40006000 0x400>; 724 clocks = <&rcc TIM12_K>; 725 clock-names = "int"; 726 access-controllers = <&etzpc STM32MP1_ETZPC_TIM12_ID>; 727 status = "disabled"; 728 729 pwm { 730 compatible = "st,stm32-pwm"; 731 #pwm-cells = <3>; 732 status = "disabled"; 733 }; 734 735 timer@11 { 736 compatible = "st,stm32h7-timer-trigger"; 737 reg = <11>; 738 status = "disabled"; 739 }; 740 }; 741 742 timers13: timer@40007000 { 743 #address-cells = <1>; 744 #size-cells = <0>; 745 compatible = "st,stm32-timers"; 746 reg = <0x40007000 0x400>; 747 clocks = <&rcc TIM13_K>; 748 clock-names = "int"; 749 access-controllers = <&etzpc STM32MP1_ETZPC_TIM13_ID>; 750 status = "disabled"; 751 752 pwm { 753 compatible = "st,stm32-pwm"; 754 #pwm-cells = <3>; 755 status = "disabled"; 756 }; 757 758 timer@12 { 759 compatible = "st,stm32h7-timer-trigger"; 760 reg = <12>; 761 status = "disabled"; 762 }; 763 }; 764 765 timers14: timer@40008000 { 766 #address-cells = <1>; 767 #size-cells = <0>; 768 compatible = "st,stm32-timers"; 769 reg = <0x40008000 0x400>; 770 clocks = <&rcc TIM14_K>; 771 clock-names = "int"; 772 access-controllers = <&etzpc STM32MP1_ETZPC_TIM14_ID>; 773 status = "disabled"; 774 775 pwm { 776 compatible = "st,stm32-pwm"; 777 #pwm-cells = <3>; 778 status = "disabled"; 779 }; 780 781 timer@13 { 782 compatible = "st,stm32h7-timer-trigger"; 783 reg = <13>; 784 status = "disabled"; 785 }; 786 }; 787 788 lptimer1: timer@40009000 { 789 #address-cells = <1>; 790 #size-cells = <0>; 791 compatible = "st,stm32-lptimer"; 792 reg = <0x40009000 0x400>; 793 interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; 794 clocks = <&rcc LPTIM1_K>; 795 clock-names = "mux"; 796 wakeup-source; 797 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM1_ID>; 798 status = "disabled"; 799 800 pwm { 801 compatible = "st,stm32-pwm-lp"; 802 #pwm-cells = <3>; 803 status = "disabled"; 804 }; 805 806 trigger@0 { 807 compatible = "st,stm32-lptimer-trigger"; 808 reg = <0>; 809 status = "disabled"; 810 }; 811 812 counter { 813 compatible = "st,stm32-lptimer-counter"; 814 status = "disabled"; 815 }; 816 }; 817 818 spi2: spi@4000b000 { 819 #address-cells = <1>; 820 #size-cells = <0>; 821 compatible = "st,stm32h7-spi"; 822 reg = <0x4000b000 0x400>; 823 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 824 clocks = <&rcc SPI2_K>; 825 resets = <&rcc SPI2_R>; 826 dmas = <&dmamux1 39 0x400 0x05>, 827 <&dmamux1 40 0x400 0x05>; 828 dma-names = "rx", "tx"; 829 access-controllers = <&etzpc STM32MP1_ETZPC_SPI2_ID>; 830 status = "disabled"; 831 }; 832 833 i2s2: audio-controller@4000b000 { 834 compatible = "st,stm32h7-i2s"; 835 #sound-dai-cells = <0>; 836 reg = <0x4000b000 0x400>; 837 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 838 dmas = <&dmamux1 39 0x400 0x01>, 839 <&dmamux1 40 0x400 0x01>; 840 dma-names = "rx", "tx"; 841 access-controllers = <&etzpc STM32MP1_ETZPC_SPI2_ID>; 842 status = "disabled"; 843 }; 844 845 spi3: spi@4000c000 { 846 #address-cells = <1>; 847 #size-cells = <0>; 848 compatible = "st,stm32h7-spi"; 849 reg = <0x4000c000 0x400>; 850 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 851 clocks = <&rcc SPI3_K>; 852 resets = <&rcc SPI3_R>; 853 dmas = <&dmamux1 61 0x400 0x05>, 854 <&dmamux1 62 0x400 0x05>; 855 dma-names = "rx", "tx"; 856 access-controllers = <&etzpc STM32MP1_ETZPC_SPI3_ID>; 857 status = "disabled"; 858 }; 859 860 i2s3: audio-controller@4000c000 { 861 compatible = "st,stm32h7-i2s"; 862 #sound-dai-cells = <0>; 863 reg = <0x4000c000 0x400>; 864 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 865 dmas = <&dmamux1 61 0x400 0x01>, 866 <&dmamux1 62 0x400 0x01>; 867 dma-names = "rx", "tx"; 868 access-controllers = <&etzpc STM32MP1_ETZPC_SPI3_ID>; 869 status = "disabled"; 870 }; 871 872 spdifrx: audio-controller@4000d000 { 873 compatible = "st,stm32h7-spdifrx"; 874 #sound-dai-cells = <0>; 875 reg = <0x4000d000 0x400>; 876 clocks = <&rcc SPDIF_K>; 877 clock-names = "kclk"; 878 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 879 dmas = <&dmamux1 93 0x400 0x01>, 880 <&dmamux1 94 0x400 0x01>; 881 dma-names = "rx", "rx-ctrl"; 882 access-controllers = <&etzpc STM32MP1_ETZPC_SPDIFRX_ID>; 883 status = "disabled"; 884 }; 885 886 usart2: serial@4000e000 { 887 compatible = "st,stm32h7-uart"; 888 reg = <0x4000e000 0x400>; 889 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; 890 clocks = <&rcc USART2_K>; 891 wakeup-source; 892 dmas = <&dmamux1 43 0x400 0x15>, 893 <&dmamux1 44 0x400 0x11>; 894 dma-names = "rx", "tx"; 895 access-controllers = <&etzpc STM32MP1_ETZPC_USART2_ID>; 896 status = "disabled"; 897 }; 898 899 usart3: serial@4000f000 { 900 compatible = "st,stm32h7-uart"; 901 reg = <0x4000f000 0x400>; 902 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; 903 clocks = <&rcc USART3_K>; 904 wakeup-source; 905 dmas = <&dmamux1 45 0x400 0x15>, 906 <&dmamux1 46 0x400 0x11>; 907 dma-names = "rx", "tx"; 908 access-controllers = <&etzpc STM32MP1_ETZPC_USART3_ID>; 909 status = "disabled"; 910 }; 911 912 uart4: serial@40010000 { 913 compatible = "st,stm32h7-uart"; 914 reg = <0x40010000 0x400>; 915 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; 916 clocks = <&rcc UART4_K>; 917 wakeup-source; 918 dmas = <&dmamux1 63 0x400 0x15>, 919 <&dmamux1 64 0x400 0x11>; 920 dma-names = "rx", "tx"; 921 access-controllers = <&etzpc STM32MP1_ETZPC_UART4_ID>; 922 status = "disabled"; 923 }; 924 925 uart5: serial@40011000 { 926 compatible = "st,stm32h7-uart"; 927 reg = <0x40011000 0x400>; 928 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; 929 clocks = <&rcc UART5_K>; 930 wakeup-source; 931 dmas = <&dmamux1 65 0x400 0x15>, 932 <&dmamux1 66 0x400 0x11>; 933 dma-names = "rx", "tx"; 934 access-controllers = <&etzpc STM32MP1_ETZPC_UART5_ID>; 935 status = "disabled"; 936 }; 937 938 i2c1: i2c@40012000 { 939 compatible = "st,stm32mp15-i2c"; 940 reg = <0x40012000 0x400>; 941 interrupt-names = "event", "error"; 942 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 944 clocks = <&rcc I2C1_K>; 945 resets = <&rcc I2C1_R>; 946 #address-cells = <1>; 947 #size-cells = <0>; 948 st,syscfg-fmp = <&syscfg 0x4 0x1>; 949 wakeup-source; 950 i2c-analog-filter; 951 access-controllers = <&etzpc STM32MP1_ETZPC_I2C1_ID>; 952 status = "disabled"; 953 }; 954 955 i2c2: i2c@40013000 { 956 compatible = "st,stm32mp15-i2c"; 957 reg = <0x40013000 0x400>; 958 interrupt-names = "event", "error"; 959 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 961 clocks = <&rcc I2C2_K>; 962 resets = <&rcc I2C2_R>; 963 #address-cells = <1>; 964 #size-cells = <0>; 965 st,syscfg-fmp = <&syscfg 0x4 0x2>; 966 wakeup-source; 967 i2c-analog-filter; 968 access-controllers = <&etzpc STM32MP1_ETZPC_I2C2_ID>; 969 status = "disabled"; 970 }; 971 972 i2c3: i2c@40014000 { 973 compatible = "st,stm32mp15-i2c"; 974 reg = <0x40014000 0x400>; 975 interrupt-names = "event", "error"; 976 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 977 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 978 clocks = <&rcc I2C3_K>; 979 resets = <&rcc I2C3_R>; 980 #address-cells = <1>; 981 #size-cells = <0>; 982 st,syscfg-fmp = <&syscfg 0x4 0x4>; 983 wakeup-source; 984 i2c-analog-filter; 985 access-controllers = <&etzpc STM32MP1_ETZPC_I2C3_ID>; 986 status = "disabled"; 987 }; 988 989 i2c5: i2c@40015000 { 990 compatible = "st,stm32mp15-i2c"; 991 reg = <0x40015000 0x400>; 992 interrupt-names = "event", "error"; 993 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 995 clocks = <&rcc I2C5_K>; 996 resets = <&rcc I2C5_R>; 997 #address-cells = <1>; 998 #size-cells = <0>; 999 st,syscfg-fmp = <&syscfg 0x4 0x10>; 1000 wakeup-source; 1001 i2c-analog-filter; 1002 access-controllers = <&etzpc STM32MP1_ETZPC_I2C5_ID>; 1003 status = "disabled"; 1004 }; 1005 1006 cec: cec@40016000 { 1007 compatible = "st,stm32-cec"; 1008 reg = <0x40016000 0x400>; 1009 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1010 clocks = <&rcc CEC_K>, <&rcc CEC>; 1011 clock-names = "cec", "hdmi-cec"; 1012 access-controllers = <&etzpc STM32MP1_ETZPC_CEC_ID>; 1013 status = "disabled"; 1014 }; 1015 1016 dac: dac@40017000 { 1017 compatible = "st,stm32h7-dac-core"; 1018 reg = <0x40017000 0x400>; 1019 clocks = <&rcc DAC12>; 1020 clock-names = "pclk"; 1021 #address-cells = <1>; 1022 #size-cells = <0>; 1023 access-controllers = <&etzpc STM32MP1_ETZPC_DAC_ID>; 1024 status = "disabled"; 1025 1026 dac1: dac@1 { 1027 compatible = "st,stm32-dac"; 1028 #io-channel-cells = <1>; 1029 reg = <1>; 1030 status = "disabled"; 1031 }; 1032 1033 dac2: dac@2 { 1034 compatible = "st,stm32-dac"; 1035 #io-channel-cells = <1>; 1036 reg = <2>; 1037 status = "disabled"; 1038 }; 1039 }; 1040 1041 uart7: serial@40018000 { 1042 compatible = "st,stm32h7-uart"; 1043 reg = <0x40018000 0x400>; 1044 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; 1045 clocks = <&rcc UART7_K>; 1046 wakeup-source; 1047 dmas = <&dmamux1 79 0x400 0x15>, 1048 <&dmamux1 80 0x400 0x11>; 1049 dma-names = "rx", "tx"; 1050 access-controllers = <&etzpc STM32MP1_ETZPC_UART7_ID>; 1051 status = "disabled"; 1052 }; 1053 1054 uart8: serial@40019000 { 1055 compatible = "st,stm32h7-uart"; 1056 reg = <0x40019000 0x400>; 1057 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; 1058 clocks = <&rcc UART8_K>; 1059 wakeup-source; 1060 dmas = <&dmamux1 81 0x400 0x15>, 1061 <&dmamux1 82 0x400 0x11>; 1062 dma-names = "rx", "tx"; 1063 access-controllers = <&etzpc STM32MP1_ETZPC_UART8_ID>; 1064 status = "disabled"; 1065 }; 1066 1067 timers1: timer@44000000 { 1068 #address-cells = <1>; 1069 #size-cells = <0>; 1070 compatible = "st,stm32-timers"; 1071 reg = <0x44000000 0x400>; 1072 clocks = <&rcc TIM1_K>; 1073 clock-names = "int"; 1074 dmas = <&dmamux1 11 0x400 0x1>, 1075 <&dmamux1 12 0x400 0x1>, 1076 <&dmamux1 13 0x400 0x1>, 1077 <&dmamux1 14 0x400 0x1>, 1078 <&dmamux1 15 0x400 0x1>, 1079 <&dmamux1 16 0x400 0x1>, 1080 <&dmamux1 17 0x400 0x1>; 1081 dma-names = "ch1", "ch2", "ch3", "ch4", 1082 "up", "trig", "com"; 1083 access-controllers = <&etzpc STM32MP1_ETZPC_TIM1_ID>; 1084 status = "disabled"; 1085 1086 pwm { 1087 compatible = "st,stm32-pwm"; 1088 #pwm-cells = <3>; 1089 status = "disabled"; 1090 }; 1091 1092 timer@0 { 1093 compatible = "st,stm32h7-timer-trigger"; 1094 reg = <0>; 1095 status = "disabled"; 1096 }; 1097 1098 counter { 1099 compatible = "st,stm32-timer-counter"; 1100 status = "disabled"; 1101 }; 1102 }; 1103 1104 timers8: timer@44001000 { 1105 #address-cells = <1>; 1106 #size-cells = <0>; 1107 compatible = "st,stm32-timers"; 1108 reg = <0x44001000 0x400>; 1109 clocks = <&rcc TIM8_K>; 1110 clock-names = "int"; 1111 dmas = <&dmamux1 47 0x400 0x1>, 1112 <&dmamux1 48 0x400 0x1>, 1113 <&dmamux1 49 0x400 0x1>, 1114 <&dmamux1 50 0x400 0x1>, 1115 <&dmamux1 51 0x400 0x1>, 1116 <&dmamux1 52 0x400 0x1>, 1117 <&dmamux1 53 0x400 0x1>; 1118 dma-names = "ch1", "ch2", "ch3", "ch4", 1119 "up", "trig", "com"; 1120 access-controllers = <&etzpc STM32MP1_ETZPC_TIM8_ID>; 1121 status = "disabled"; 1122 1123 pwm { 1124 compatible = "st,stm32-pwm"; 1125 #pwm-cells = <3>; 1126 status = "disabled"; 1127 }; 1128 1129 timer@7 { 1130 compatible = "st,stm32h7-timer-trigger"; 1131 reg = <7>; 1132 status = "disabled"; 1133 }; 1134 1135 counter { 1136 compatible = "st,stm32-timer-counter"; 1137 status = "disabled"; 1138 }; 1139 }; 1140 1141 usart6: serial@44003000 { 1142 compatible = "st,stm32h7-uart"; 1143 reg = <0x44003000 0x400>; 1144 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; 1145 clocks = <&rcc USART6_K>; 1146 wakeup-source; 1147 dmas = <&dmamux1 71 0x400 0x15>, 1148 <&dmamux1 72 0x400 0x11>; 1149 dma-names = "rx", "tx"; 1150 access-controllers = <&etzpc STM32MP1_ETZPC_USART6_ID>; 1151 status = "disabled"; 1152 }; 1153 1154 spi1: spi@44004000 { 1155 #address-cells = <1>; 1156 #size-cells = <0>; 1157 compatible = "st,stm32h7-spi"; 1158 reg = <0x44004000 0x400>; 1159 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1160 clocks = <&rcc SPI1_K>; 1161 resets = <&rcc SPI1_R>; 1162 dmas = <&dmamux1 37 0x400 0x05>, 1163 <&dmamux1 38 0x400 0x05>; 1164 dma-names = "rx", "tx"; 1165 access-controllers = <&etzpc STM32MP1_ETZPC_SPI1_ID>; 1166 status = "disabled"; 1167 }; 1168 1169 i2s1: audio-controller@44004000 { 1170 compatible = "st,stm32h7-i2s"; 1171 #sound-dai-cells = <0>; 1172 reg = <0x44004000 0x400>; 1173 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1174 dmas = <&dmamux1 37 0x400 0x01>, 1175 <&dmamux1 38 0x400 0x01>; 1176 dma-names = "rx", "tx"; 1177 access-controllers = <&etzpc STM32MP1_ETZPC_SPI1_ID>; 1178 status = "disabled"; 1179 }; 1180 1181 spi4: spi@44005000 { 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 compatible = "st,stm32h7-spi"; 1185 reg = <0x44005000 0x400>; 1186 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1187 clocks = <&rcc SPI4_K>; 1188 resets = <&rcc SPI4_R>; 1189 dmas = <&dmamux1 83 0x400 0x05>, 1190 <&dmamux1 84 0x400 0x05>; 1191 dma-names = "rx", "tx"; 1192 access-controllers = <&etzpc STM32MP1_ETZPC_SPI4_ID>; 1193 status = "disabled"; 1194 }; 1195 1196 timers15: timer@44006000 { 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 compatible = "st,stm32-timers"; 1200 reg = <0x44006000 0x400>; 1201 clocks = <&rcc TIM15_K>; 1202 clock-names = "int"; 1203 dmas = <&dmamux1 105 0x400 0x1>, 1204 <&dmamux1 106 0x400 0x1>, 1205 <&dmamux1 107 0x400 0x1>, 1206 <&dmamux1 108 0x400 0x1>; 1207 dma-names = "ch1", "up", "trig", "com"; 1208 access-controllers = <&etzpc STM32MP1_ETZPC_TIM15_ID>; 1209 status = "disabled"; 1210 1211 pwm { 1212 compatible = "st,stm32-pwm"; 1213 #pwm-cells = <3>; 1214 status = "disabled"; 1215 }; 1216 1217 timer@14 { 1218 compatible = "st,stm32h7-timer-trigger"; 1219 reg = <14>; 1220 status = "disabled"; 1221 }; 1222 }; 1223 1224 timers16: timer@44007000 { 1225 #address-cells = <1>; 1226 #size-cells = <0>; 1227 compatible = "st,stm32-timers"; 1228 reg = <0x44007000 0x400>; 1229 clocks = <&rcc TIM16_K>; 1230 clock-names = "int"; 1231 dmas = <&dmamux1 109 0x400 0x1>, 1232 <&dmamux1 110 0x400 0x1>; 1233 dma-names = "ch1", "up"; 1234 access-controllers = <&etzpc STM32MP1_ETZPC_TIM16_ID>; 1235 status = "disabled"; 1236 1237 pwm { 1238 compatible = "st,stm32-pwm"; 1239 #pwm-cells = <3>; 1240 status = "disabled"; 1241 }; 1242 timer@15 { 1243 compatible = "st,stm32h7-timer-trigger"; 1244 reg = <15>; 1245 status = "disabled"; 1246 }; 1247 }; 1248 1249 timers17: timer@44008000 { 1250 #address-cells = <1>; 1251 #size-cells = <0>; 1252 compatible = "st,stm32-timers"; 1253 reg = <0x44008000 0x400>; 1254 clocks = <&rcc TIM17_K>; 1255 clock-names = "int"; 1256 dmas = <&dmamux1 111 0x400 0x1>, 1257 <&dmamux1 112 0x400 0x1>; 1258 dma-names = "ch1", "up"; 1259 access-controllers = <&etzpc STM32MP1_ETZPC_TIM17_ID>; 1260 status = "disabled"; 1261 1262 pwm { 1263 compatible = "st,stm32-pwm"; 1264 #pwm-cells = <3>; 1265 status = "disabled"; 1266 }; 1267 1268 timer@16 { 1269 compatible = "st,stm32h7-timer-trigger"; 1270 reg = <16>; 1271 status = "disabled"; 1272 }; 1273 }; 1274 1275 spi5: spi@44009000 { 1276 #address-cells = <1>; 1277 #size-cells = <0>; 1278 compatible = "st,stm32h7-spi"; 1279 reg = <0x44009000 0x400>; 1280 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1281 clocks = <&rcc SPI5_K>; 1282 resets = <&rcc SPI5_R>; 1283 dmas = <&dmamux1 85 0x400 0x05>, 1284 <&dmamux1 86 0x400 0x05>; 1285 dma-names = "rx", "tx"; 1286 access-controllers = <&etzpc STM32MP1_ETZPC_SPI5_ID>; 1287 status = "disabled"; 1288 }; 1289 1290 sai1: sai@4400a000 { 1291 compatible = "st,stm32h7-sai"; 1292 #address-cells = <1>; 1293 #size-cells = <1>; 1294 ranges = <0 0x4400a000 0x400>; 1295 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; 1296 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1297 resets = <&rcc SAI1_R>; 1298 access-controllers = <&etzpc STM32MP1_ETZPC_SAI1_ID>; 1299 status = "disabled"; 1300 1301 sai1a: audio-controller@4400a004 { 1302 #sound-dai-cells = <0>; 1303 1304 compatible = "st,stm32-sai-sub-a"; 1305 reg = <0x4 0x20>; 1306 clocks = <&rcc SAI1_K>; 1307 clock-names = "sai_ck"; 1308 dmas = <&dmamux1 87 0x400 0x01>; 1309 status = "disabled"; 1310 }; 1311 1312 sai1b: audio-controller@4400a024 { 1313 #sound-dai-cells = <0>; 1314 compatible = "st,stm32-sai-sub-b"; 1315 reg = <0x24 0x20>; 1316 clocks = <&rcc SAI1_K>; 1317 clock-names = "sai_ck"; 1318 dmas = <&dmamux1 88 0x400 0x01>; 1319 status = "disabled"; 1320 }; 1321 }; 1322 1323 sai2: sai@4400b000 { 1324 compatible = "st,stm32h7-sai"; 1325 #address-cells = <1>; 1326 #size-cells = <1>; 1327 ranges = <0 0x4400b000 0x400>; 1328 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; 1329 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1330 resets = <&rcc SAI2_R>; 1331 access-controllers = <&etzpc STM32MP1_ETZPC_SAI2_ID>; 1332 status = "disabled"; 1333 1334 sai2a: audio-controller@4400b004 { 1335 #sound-dai-cells = <0>; 1336 compatible = "st,stm32-sai-sub-a"; 1337 reg = <0x4 0x20>; 1338 clocks = <&rcc SAI2_K>; 1339 clock-names = "sai_ck"; 1340 dmas = <&dmamux1 89 0x400 0x01>; 1341 status = "disabled"; 1342 }; 1343 1344 sai2b: audio-controller@4400b024 { 1345 #sound-dai-cells = <0>; 1346 compatible = "st,stm32-sai-sub-b"; 1347 reg = <0x24 0x20>; 1348 clocks = <&rcc SAI2_K>; 1349 clock-names = "sai_ck"; 1350 dmas = <&dmamux1 90 0x400 0x01>; 1351 status = "disabled"; 1352 }; 1353 }; 1354 1355 sai3: sai@4400c000 { 1356 compatible = "st,stm32h7-sai"; 1357 #address-cells = <1>; 1358 #size-cells = <1>; 1359 ranges = <0 0x4400c000 0x400>; 1360 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; 1361 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1362 resets = <&rcc SAI3_R>; 1363 access-controllers = <&etzpc STM32MP1_ETZPC_SAI3_ID>; 1364 status = "disabled"; 1365 1366 sai3a: audio-controller@4400c004 { 1367 #sound-dai-cells = <0>; 1368 compatible = "st,stm32-sai-sub-a"; 1369 reg = <0x04 0x20>; 1370 clocks = <&rcc SAI3_K>; 1371 clock-names = "sai_ck"; 1372 dmas = <&dmamux1 113 0x400 0x01>; 1373 status = "disabled"; 1374 }; 1375 1376 sai3b: audio-controller@4400c024 { 1377 #sound-dai-cells = <0>; 1378 compatible = "st,stm32-sai-sub-b"; 1379 reg = <0x24 0x20>; 1380 clocks = <&rcc SAI3_K>; 1381 clock-names = "sai_ck"; 1382 dmas = <&dmamux1 114 0x400 0x01>; 1383 status = "disabled"; 1384 }; 1385 }; 1386 1387 dfsdm: dfsdm@4400d000 { 1388 compatible = "st,stm32mp1-dfsdm"; 1389 reg = <0x4400d000 0x800>; 1390 clocks = <&rcc DFSDM_K>; 1391 clock-names = "dfsdm"; 1392 #address-cells = <1>; 1393 #size-cells = <0>; 1394 access-controllers = <&etzpc STM32MP1_ETZPC_DFSDM_ID>; 1395 status = "disabled"; 1396 1397 dfsdm0: filter@0 { 1398 compatible = "st,stm32-dfsdm-adc"; 1399 #io-channel-cells = <1>; 1400 reg = <0>; 1401 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 1402 dmas = <&dmamux1 101 0x400 0x01>; 1403 dma-names = "rx"; 1404 status = "disabled"; 1405 }; 1406 1407 dfsdm1: filter@1 { 1408 compatible = "st,stm32-dfsdm-adc"; 1409 #io-channel-cells = <1>; 1410 reg = <1>; 1411 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1412 dmas = <&dmamux1 102 0x400 0x01>; 1413 dma-names = "rx"; 1414 status = "disabled"; 1415 }; 1416 1417 dfsdm2: filter@2 { 1418 compatible = "st,stm32-dfsdm-adc"; 1419 #io-channel-cells = <1>; 1420 reg = <2>; 1421 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1422 dmas = <&dmamux1 103 0x400 0x01>; 1423 dma-names = "rx"; 1424 status = "disabled"; 1425 }; 1426 1427 dfsdm3: filter@3 { 1428 compatible = "st,stm32-dfsdm-adc"; 1429 #io-channel-cells = <1>; 1430 reg = <3>; 1431 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1432 dmas = <&dmamux1 104 0x400 0x01>; 1433 dma-names = "rx"; 1434 status = "disabled"; 1435 }; 1436 1437 dfsdm4: filter@4 { 1438 compatible = "st,stm32-dfsdm-adc"; 1439 #io-channel-cells = <1>; 1440 reg = <4>; 1441 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1442 dmas = <&dmamux1 91 0x400 0x01>; 1443 dma-names = "rx"; 1444 status = "disabled"; 1445 }; 1446 1447 dfsdm5: filter@5 { 1448 compatible = "st,stm32-dfsdm-adc"; 1449 #io-channel-cells = <1>; 1450 reg = <5>; 1451 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1452 dmas = <&dmamux1 92 0x400 0x01>; 1453 dma-names = "rx"; 1454 status = "disabled"; 1455 }; 1456 }; 1457 1458 dma1: dma-controller@48000000 { 1459 compatible = "st,stm32-dma"; 1460 reg = <0x48000000 0x400>; 1461 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1466 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1469 clocks = <&rcc DMA1>; 1470 resets = <&rcc DMA1_R>; 1471 #dma-cells = <4>; 1472 st,mem2mem; 1473 dma-requests = <8>; 1474 access-controllers = <&etzpc STM32MP1_ETZPC_DMA1_ID>; 1475 status = "disabled"; 1476 }; 1477 1478 dma2: dma-controller@48001000 { 1479 compatible = "st,stm32-dma"; 1480 reg = <0x48001000 0x400>; 1481 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1489 clocks = <&rcc DMA2>; 1490 resets = <&rcc DMA2_R>; 1491 #dma-cells = <4>; 1492 st,mem2mem; 1493 dma-requests = <8>; 1494 access-controllers = <&etzpc STM32MP1_ETZPC_DMA2_ID>; 1495 status = "disabled"; 1496 }; 1497 1498 dmamux1: dma-router@48002000 { 1499 compatible = "st,stm32h7-dmamux"; 1500 reg = <0x48002000 0x40>; 1501 #dma-cells = <3>; 1502 dma-requests = <128>; 1503 dma-masters = <&dma1 &dma2>; 1504 dma-channels = <16>; 1505 clocks = <&rcc DMAMUX>; 1506 resets = <&rcc DMAMUX_R>; 1507 access-controllers = <&etzpc STM32MP1_ETZPC_DMAMUX_ID>; 1508 status = "disabled"; 1509 }; 1510 1511 adc: adc@48003000 { 1512 compatible = "st,stm32mp1-adc-core"; 1513 reg = <0x48003000 0x400>; 1514 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1515 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1516 clocks = <&rcc ADC12>, <&rcc ADC12_K>; 1517 clock-names = "bus", "adc"; 1518 interrupt-controller; 1519 st,syscfg = <&syscfg>; 1520 #interrupt-cells = <1>; 1521 #address-cells = <1>; 1522 #size-cells = <0>; 1523 access-controllers = <&etzpc STM32MP1_ETZPC_ADC_ID>; 1524 status = "disabled"; 1525 1526 adc1: adc@0 { 1527 compatible = "st,stm32mp1-adc"; 1528 #io-channel-cells = <1>; 1529 reg = <0x0>; 1530 interrupt-parent = <&adc>; 1531 interrupts = <0>; 1532 dmas = <&dmamux1 9 0x400 0x01>; 1533 dma-names = "rx"; 1534 status = "disabled"; 1535 }; 1536 1537 adc2: adc@100 { 1538 compatible = "st,stm32mp1-adc"; 1539 #io-channel-cells = <1>; 1540 reg = <0x100>; 1541 interrupt-parent = <&adc>; 1542 interrupts = <1>; 1543 dmas = <&dmamux1 10 0x400 0x01>; 1544 dma-names = "rx"; 1545 status = "disabled"; 1546 }; 1547 }; 1548 1549 sdmmc3: mmc@48004000 { 1550 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 1551 arm,primecell-periphid = <0x00253180>; 1552 reg = <0x48004000 0x400>; 1553 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1554 interrupt-names = "cmd_irq"; 1555 clocks = <&rcc SDMMC3_K>; 1556 clock-names = "apb_pclk"; 1557 resets = <&rcc SDMMC3_R>; 1558 cap-sd-highspeed; 1559 cap-mmc-highspeed; 1560 max-frequency = <120000000>; 1561 access-controllers = <&etzpc STM32MP1_ETZPC_SDMMC3_ID>; 1562 status = "disabled"; 1563 }; 1564 1565 usbotg_hs: usb-otg@49000000 { 1566 compatible = "st,stm32mp15-hsotg", "snps,dwc2"; 1567 reg = <0x49000000 0x10000>; 1568 clocks = <&rcc USBO_K>; 1569 clock-names = "otg"; 1570 resets = <&rcc USBO_R>; 1571 reset-names = "dwc2"; 1572 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1573 g-rx-fifo-size = <512>; 1574 g-np-tx-fifo-size = <32>; 1575 g-tx-fifo-size = <256 16 16 16 16 16 16 16>; 1576 dr_mode = "otg"; 1577 otg-rev = <0x200>; 1578 usb33d-supply = <&usb33>; 1579 access-controllers = <&etzpc STM32MP1_ETZPC_OTG_ID>; 1580 status = "disabled"; 1581 }; 1582 1583 dcmi: dcmi@4c006000 { 1584 compatible = "st,stm32-dcmi"; 1585 reg = <0x4c006000 0x400>; 1586 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1587 resets = <&rcc CAMITF_R>; 1588 clocks = <&rcc DCMI>; 1589 clock-names = "mclk"; 1590 dmas = <&dmamux1 75 0x400 0x01>; 1591 dma-names = "tx"; 1592 access-controllers = <&etzpc STM32MP1_ETZPC_DCMI_ID>; 1593 status = "disabled"; 1594 }; 1595 1596 lptimer2: timer@50021000 { 1597 #address-cells = <1>; 1598 #size-cells = <0>; 1599 compatible = "st,stm32-lptimer"; 1600 reg = <0x50021000 0x400>; 1601 interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; 1602 clocks = <&rcc LPTIM2_K>; 1603 clock-names = "mux"; 1604 wakeup-source; 1605 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM2_ID>; 1606 status = "disabled"; 1607 1608 pwm { 1609 compatible = "st,stm32-pwm-lp"; 1610 #pwm-cells = <3>; 1611 status = "disabled"; 1612 }; 1613 1614 trigger@1 { 1615 compatible = "st,stm32-lptimer-trigger"; 1616 reg = <1>; 1617 status = "disabled"; 1618 }; 1619 1620 counter { 1621 compatible = "st,stm32-lptimer-counter"; 1622 status = "disabled"; 1623 }; 1624 }; 1625 1626 lptimer3: timer@50022000 { 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 compatible = "st,stm32-lptimer"; 1630 reg = <0x50022000 0x400>; 1631 interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; 1632 clocks = <&rcc LPTIM3_K>; 1633 clock-names = "mux"; 1634 wakeup-source; 1635 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM3_ID>; 1636 status = "disabled"; 1637 1638 pwm { 1639 compatible = "st,stm32-pwm-lp"; 1640 #pwm-cells = <3>; 1641 status = "disabled"; 1642 }; 1643 1644 trigger@2 { 1645 compatible = "st,stm32-lptimer-trigger"; 1646 reg = <2>; 1647 status = "disabled"; 1648 }; 1649 }; 1650 1651 lptimer4: timer@50023000 { 1652 compatible = "st,stm32-lptimer"; 1653 reg = <0x50023000 0x400>; 1654 interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; 1655 clocks = <&rcc LPTIM4_K>; 1656 clock-names = "mux"; 1657 wakeup-source; 1658 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM4_ID>; 1659 status = "disabled"; 1660 1661 pwm { 1662 compatible = "st,stm32-pwm-lp"; 1663 #pwm-cells = <3>; 1664 status = "disabled"; 1665 }; 1666 }; 1667 1668 lptimer5: timer@50024000 { 1669 compatible = "st,stm32-lptimer"; 1670 reg = <0x50024000 0x400>; 1671 interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; 1672 clocks = <&rcc LPTIM5_K>; 1673 clock-names = "mux"; 1674 wakeup-source; 1675 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM5_ID>; 1676 status = "disabled"; 1677 1678 pwm { 1679 compatible = "st,stm32-pwm-lp"; 1680 #pwm-cells = <3>; 1681 status = "disabled"; 1682 }; 1683 }; 1684 1685 vrefbuf: vrefbuf@50025000 { 1686 compatible = "st,stm32-vrefbuf"; 1687 reg = <0x50025000 0x8>; 1688 regulator-min-microvolt = <1500000>; 1689 regulator-max-microvolt = <2500000>; 1690 clocks = <&rcc VREF>; 1691 access-controllers = <&etzpc STM32MP1_ETZPC_VREFBUF_ID>; 1692 status = "disabled"; 1693 }; 1694 1695 sai4: sai@50027000 { 1696 compatible = "st,stm32h7-sai"; 1697 #address-cells = <1>; 1698 #size-cells = <1>; 1699 ranges = <0 0x50027000 0x400>; 1700 reg = <0x50027000 0x4>, <0x500273f0 0x10>; 1701 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1702 resets = <&rcc SAI4_R>; 1703 access-controllers = <&etzpc STM32MP1_ETZPC_SAI4_ID>; 1704 status = "disabled"; 1705 1706 sai4a: audio-controller@50027004 { 1707 #sound-dai-cells = <0>; 1708 compatible = "st,stm32-sai-sub-a"; 1709 reg = <0x04 0x20>; 1710 clocks = <&rcc SAI4_K>; 1711 clock-names = "sai_ck"; 1712 dmas = <&dmamux1 99 0x400 0x01>; 1713 status = "disabled"; 1714 }; 1715 1716 sai4b: audio-controller@50027024 { 1717 #sound-dai-cells = <0>; 1718 compatible = "st,stm32-sai-sub-b"; 1719 reg = <0x24 0x20>; 1720 clocks = <&rcc SAI4_K>; 1721 clock-names = "sai_ck"; 1722 dmas = <&dmamux1 100 0x400 0x01>; 1723 status = "disabled"; 1724 }; 1725 }; 1726 1727 hash1: hash@54002000 { 1728 compatible = "st,stm32f756-hash"; 1729 reg = <0x54002000 0x400>; 1730 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1731 clocks = <&rcc HASH1>; 1732 resets = <&rcc HASH1_R>; 1733 dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; 1734 dma-names = "in"; 1735 dma-maxburst = <2>; 1736 access-controllers = <&etzpc STM32MP1_ETZPC_HASH1_ID>; 1737 status = "disabled"; 1738 }; 1739 1740 rng1: rng@54003000 { 1741 compatible = "st,stm32-rng"; 1742 reg = <0x54003000 0x400>; 1743 clocks = <&rcc RNG1_K>; 1744 resets = <&rcc RNG1_R>; 1745 access-controllers = <&etzpc STM32MP1_ETZPC_RNG1_ID>; 1746 status = "disabled"; 1747 }; 1748 1749 fmc: memory-controller@58002000 { 1750 #address-cells = <2>; 1751 #size-cells = <1>; 1752 compatible = "st,stm32mp1-fmc2-ebi"; 1753 reg = <0x58002000 0x1000>; 1754 clocks = <&rcc FMC_K>; 1755 resets = <&rcc FMC_R>; 1756 access-controllers = <&etzpc STM32MP1_ETZPC_FMC_ID>; 1757 status = "disabled"; 1758 1759 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 1760 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 1761 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 1762 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 1763 <4 0 0x80000000 0x10000000>; /* NAND */ 1764 1765 nand-controller@4,0 { 1766 #address-cells = <1>; 1767 #size-cells = <0>; 1768 compatible = "st,stm32mp1-fmc2-nfc"; 1769 reg = <4 0x00000000 0x1000>, 1770 <4 0x08010000 0x1000>, 1771 <4 0x08020000 0x1000>, 1772 <4 0x01000000 0x1000>, 1773 <4 0x09010000 0x1000>, 1774 <4 0x09020000 0x1000>; 1775 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1776 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, 1777 <&mdma1 20 0x2 0x12000a08 0x0 0x0>, 1778 <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; 1779 dma-names = "tx", "rx", "ecc"; 1780 status = "disabled"; 1781 }; 1782 }; 1783 1784 qspi: spi@58003000 { 1785 compatible = "st,stm32f469-qspi"; 1786 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; 1787 reg-names = "qspi", "qspi_mm"; 1788 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 1789 dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, 1790 <&mdma1 22 0x2 0x10100008 0x0 0x0>; 1791 dma-names = "tx", "rx"; 1792 clocks = <&rcc QSPI_K>; 1793 resets = <&rcc QSPI_R>; 1794 #address-cells = <1>; 1795 #size-cells = <0>; 1796 access-controllers = <&etzpc STM32MP1_ETZPC_QSPI_ID>; 1797 status = "disabled"; 1798 }; 1799 1800 ethernet0: ethernet@5800a000 { 1801 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; 1802 reg = <0x5800a000 0x2000>; 1803 reg-names = "stmmaceth"; 1804 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1805 interrupt-names = "macirq"; 1806 clock-names = "stmmaceth", 1807 "mac-clk-tx", 1808 "mac-clk-rx", 1809 "eth-ck", 1810 "ptp_ref", 1811 "ethstp"; 1812 clocks = <&rcc ETHMAC>, 1813 <&rcc ETHTX>, 1814 <&rcc ETHRX>, 1815 <&rcc ETHCK_K>, 1816 <&rcc ETHPTP_K>, 1817 <&rcc ETHSTP>; 1818 st,syscon = <&syscfg 0x4>; 1819 snps,mixed-burst; 1820 snps,pbl = <2>; 1821 snps,en-tx-lpi-clockgating; 1822 snps,axi-config = <&stmmac_axi_config_0>; 1823 snps,tso; 1824 access-controllers = <&etzpc STM32MP1_ETZPC_ETH_ID>; 1825 status = "disabled"; 1826 1827 stmmac_axi_config_0: stmmac-axi-config { 1828 snps,wr_osr_lmt = <0x7>; 1829 snps,rd_osr_lmt = <0x7>; 1830 snps,blen = <0 0 0 0 16 8 4>; 1831 }; 1832 }; 1833 1834 usart1: serial@5c000000 { 1835 compatible = "st,stm32h7-uart"; 1836 reg = <0x5c000000 0x400>; 1837 interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; 1838 clocks = <&rcc USART1_K>; 1839 wakeup-source; 1840 access-controllers = <&etzpc STM32MP1_ETZPC_USART1_ID>; 1841 status = "disabled"; 1842 }; 1843 1844 spi6: spi@5c001000 { 1845 #address-cells = <1>; 1846 #size-cells = <0>; 1847 compatible = "st,stm32h7-spi"; 1848 reg = <0x5c001000 0x400>; 1849 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1850 clocks = <&rcc SPI6_K>; 1851 resets = <&rcc SPI6_R>; 1852 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, 1853 <&mdma1 35 0x0 0x40002 0x0 0x0>; 1854 dma-names = "rx", "tx"; 1855 access-controllers = <&etzpc STM32MP1_ETZPC_SPI6_ID>; 1856 status = "disabled"; 1857 }; 1858 1859 i2c4: i2c@5c002000 { 1860 compatible = "st,stm32mp15-i2c"; 1861 reg = <0x5c002000 0x400>; 1862 interrupt-names = "event", "error"; 1863 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1865 clocks = <&rcc I2C4_K>; 1866 resets = <&rcc I2C4_R>; 1867 #address-cells = <1>; 1868 #size-cells = <0>; 1869 st,syscfg-fmp = <&syscfg 0x4 0x8>; 1870 wakeup-source; 1871 i2c-analog-filter; 1872 access-controllers = <&etzpc STM32MP1_ETZPC_I2C4_ID>; 1873 status = "disabled"; 1874 }; 1875 1876 iwdg1: watchdog@5c003000 { 1877 compatible = "st,stm32mp1-iwdg"; 1878 reg = <0x5C003000 0x400>; 1879 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1880 clocks = <&rcc IWDG1>, <&rcc CK_LSI>; 1881 clock-names = "pclk", "lsi"; 1882 access-controllers = <&etzpc STM32MP1_ETZPC_IWDG1_ID>; 1883 status = "disabled"; 1884 }; 1885 1886 i2c6: i2c@5c009000 { 1887 compatible = "st,stm32mp15-i2c"; 1888 reg = <0x5c009000 0x400>; 1889 interrupt-names = "event", "error"; 1890 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1891 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1892 clocks = <&rcc I2C6_K>; 1893 resets = <&rcc I2C6_R>; 1894 #address-cells = <1>; 1895 #size-cells = <0>; 1896 st,syscfg-fmp = <&syscfg 0x4 0x20>; 1897 wakeup-source; 1898 i2c-analog-filter; 1899 access-controllers = <&etzpc STM32MP1_ETZPC_I2C6_ID>; 1900 status = "disabled"; 1901 }; 1902 }; 1903 }; 1904 1905 mlahb: ahb { 1906 compatible = "st,mlahb", "simple-bus"; 1907 #address-cells = <1>; 1908 #size-cells = <1>; 1909 ranges; 1910 dma-ranges = <0x00000000 0x38000000 0x10000>, 1911 <0x10000000 0x10000000 0x60000>, 1912 <0x30000000 0x30000000 0x60000>; 1913 1914 m4_rproc: m4@10000000 { 1915 compatible = "st,stm32mp1-m4"; 1916 reg = <0x10000000 0x40000>, 1917 <0x30000000 0x40000>, 1918 <0x38000000 0x10000>; 1919 resets = <&rcc MCU_R>, <&rcc MCU_HOLD_BOOT_R>; 1920 reset-names = "mcu_rst", "hold_boot"; 1921 st,syscfg-tz = <&rcc 0x000 0x1>; 1922 st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; 1923 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; 1924 st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; 1925 status = "disabled"; 1926 }; 1927 }; 1928}; 1929