1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2017-2024 - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/stm32mp1-clks.h> 8#include <dt-bindings/reset/stm32mp1-resets.h> 9#include <dt-bindings/firewall/stm32mp15-etzpc.h> 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a7"; 21 clock-frequency = <650000000>; 22 device_type = "cpu"; 23 reg = <0>; 24 }; 25 }; 26 27 arm-pmu { 28 compatible = "arm,cortex-a7-pmu"; 29 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 30 interrupt-affinity = <&cpu0>; 31 interrupt-parent = <&intc>; 32 }; 33 34 psci { 35 compatible = "arm,psci-1.0"; 36 method = "smc"; 37 }; 38 39 intc: interrupt-controller@a0021000 { 40 compatible = "arm,cortex-a7-gic"; 41 #interrupt-cells = <3>; 42 interrupt-controller; 43 reg = <0xa0021000 0x1000>, 44 <0xa0022000 0x2000>; 45 }; 46 47 timer { 48 compatible = "arm,armv7-timer"; 49 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 50 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 51 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 52 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 53 interrupt-parent = <&intc>; 54 }; 55 56 clocks { 57 clk_hse: clk-hse { 58 #clock-cells = <0>; 59 compatible = "fixed-clock"; 60 clock-frequency = <24000000>; 61 }; 62 63 clk_hsi: clk-hsi { 64 #clock-cells = <0>; 65 compatible = "fixed-clock"; 66 clock-frequency = <64000000>; 67 }; 68 69 clk_lse: clk-lse { 70 #clock-cells = <0>; 71 compatible = "fixed-clock"; 72 clock-frequency = <32768>; 73 }; 74 75 clk_lsi: clk-lsi { 76 #clock-cells = <0>; 77 compatible = "fixed-clock"; 78 clock-frequency = <32000>; 79 }; 80 81 clk_csi: clk-csi { 82 #clock-cells = <0>; 83 compatible = "fixed-clock"; 84 clock-frequency = <4000000>; 85 }; 86 }; 87 88 thermal-zones { 89 cpu_thermal: cpu-thermal { 90 polling-delay-passive = <0>; 91 polling-delay = <0>; 92 thermal-sensors = <&dts>; 93 94 trips { 95 cpu_alert1: cpu-alert1 { 96 temperature = <85000>; 97 hysteresis = <0>; 98 type = "passive"; 99 }; 100 101 cpu-crit { 102 temperature = <120000>; 103 hysteresis = <0>; 104 type = "critical"; 105 }; 106 }; 107 108 cooling-maps { 109 }; 110 }; 111 }; 112 113 booster: regulator-booster { 114 compatible = "st,stm32mp1-booster"; 115 st,syscfg = <&syscfg>; 116 status = "disabled"; 117 }; 118 119 soc { 120 compatible = "simple-bus"; 121 #address-cells = <1>; 122 #size-cells = <1>; 123 interrupt-parent = <&intc>; 124 ranges; 125 126 ipcc: mailbox@4c001000 { 127 compatible = "st,stm32mp1-ipcc"; 128 #mbox-cells = <1>; 129 reg = <0x4c001000 0x400>; 130 st,proc-id = <0>; 131 interrupts-extended = 132 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 133 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 134 <&exti 61 1>; 135 interrupt-names = "rx", "tx", "wakeup"; 136 clocks = <&rcc IPCC>; 137 wakeup-source; 138 status = "disabled"; 139 }; 140 141 rcc: rcc@50000000 { 142 compatible = "st,stm32mp1-rcc", "syscon"; 143 reg = <0x50000000 0x1000>; 144 #clock-cells = <1>; 145 #reset-cells = <1>; 146 }; 147 148 pwr_regulators: pwr@50001000 { 149 compatible = "st,stm32mp1,pwr-reg"; 150 reg = <0x50001000 0x10>; 151 152 reg11: reg11 { 153 regulator-name = "reg11"; 154 regulator-min-microvolt = <1100000>; 155 regulator-max-microvolt = <1100000>; 156 }; 157 158 reg18: reg18 { 159 regulator-name = "reg18"; 160 regulator-min-microvolt = <1800000>; 161 regulator-max-microvolt = <1800000>; 162 }; 163 164 usb33: usb33 { 165 regulator-name = "usb33"; 166 regulator-min-microvolt = <3300000>; 167 regulator-max-microvolt = <3300000>; 168 }; 169 }; 170 171 pwr_mcu: pwr_mcu@50001014 { 172 compatible = "st,stm32mp151-pwr-mcu", "syscon"; 173 reg = <0x50001014 0x4>; 174 }; 175 176 exti: interrupt-controller@5000d000 { 177 compatible = "st,stm32mp1-exti", "syscon"; 178 interrupt-controller; 179 #interrupt-cells = <2>; 180 reg = <0x5000d000 0x400>; 181 }; 182 183 syscfg: syscon@50020000 { 184 compatible = "st,stm32mp157-syscfg", "syscon"; 185 reg = <0x50020000 0x400>; 186 clocks = <&rcc SYSCFG>; 187 }; 188 189 dts: thermal@50028000 { 190 compatible = "st,stm32-thermal"; 191 reg = <0x50028000 0x100>; 192 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 193 clocks = <&rcc TMPSENS>; 194 clock-names = "pclk"; 195 #thermal-sensor-cells = <0>; 196 status = "disabled"; 197 }; 198 199 mdma1: dma-controller@58000000 { 200 compatible = "st,stm32h7-mdma"; 201 reg = <0x58000000 0x1000>; 202 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 203 clocks = <&rcc MDMA>; 204 resets = <&rcc MDMA_R>; 205 #dma-cells = <5>; 206 dma-channels = <32>; 207 dma-requests = <48>; 208 }; 209 210 sdmmc1: mmc@58005000 { 211 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 212 arm,primecell-periphid = <0x00253180>; 213 reg = <0x58005000 0x1000>; 214 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 215 interrupt-names = "cmd_irq"; 216 clocks = <&rcc SDMMC1_K>; 217 clock-names = "apb_pclk"; 218 resets = <&rcc SDMMC1_R>; 219 cap-sd-highspeed; 220 cap-mmc-highspeed; 221 max-frequency = <120000000>; 222 status = "disabled"; 223 }; 224 225 sdmmc2: mmc@58007000 { 226 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 227 arm,primecell-periphid = <0x00253180>; 228 reg = <0x58007000 0x1000>; 229 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 230 interrupt-names = "cmd_irq"; 231 clocks = <&rcc SDMMC2_K>; 232 clock-names = "apb_pclk"; 233 resets = <&rcc SDMMC2_R>; 234 cap-sd-highspeed; 235 cap-mmc-highspeed; 236 max-frequency = <120000000>; 237 status = "disabled"; 238 }; 239 240 crc1: crc@58009000 { 241 compatible = "st,stm32f7-crc"; 242 reg = <0x58009000 0x400>; 243 clocks = <&rcc CRC1>; 244 status = "disabled"; 245 }; 246 247 usbh_ohci: usb@5800c000 { 248 compatible = "generic-ohci"; 249 reg = <0x5800c000 0x1000>; 250 clocks = <&usbphyc>, <&rcc USBH>; 251 resets = <&rcc USBH_R>; 252 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 253 status = "disabled"; 254 }; 255 256 usbh_ehci: usb@5800d000 { 257 compatible = "generic-ehci"; 258 reg = <0x5800d000 0x1000>; 259 clocks = <&usbphyc>, <&rcc USBH>; 260 resets = <&rcc USBH_R>; 261 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 262 companion = <&usbh_ohci>; 263 status = "disabled"; 264 }; 265 266 ltdc: display-controller@5a001000 { 267 compatible = "st,stm32-ltdc"; 268 reg = <0x5a001000 0x400>; 269 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 271 clocks = <&rcc LTDC_PX>; 272 clock-names = "lcd"; 273 resets = <&rcc LTDC_R>; 274 status = "disabled"; 275 276 port { 277 #address-cells = <1>; 278 #size-cells = <0>; 279 }; 280 }; 281 282 iwdg2: watchdog@5a002000 { 283 compatible = "st,stm32mp1-iwdg"; 284 reg = <0x5a002000 0x400>; 285 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&rcc IWDG2>, <&rcc CK_LSI>; 287 clock-names = "pclk", "lsi"; 288 status = "disabled"; 289 }; 290 291 usbphyc: usbphyc@5a006000 { 292 #address-cells = <1>; 293 #size-cells = <0>; 294 #clock-cells = <0>; 295 compatible = "st,stm32mp1-usbphyc"; 296 reg = <0x5a006000 0x1000>; 297 clocks = <&rcc USBPHY_K>; 298 resets = <&rcc USBPHY_R>; 299 vdda1v1-supply = <®11>; 300 vdda1v8-supply = <®18>; 301 status = "disabled"; 302 303 usbphyc_port0: usb-phy@0 { 304 #phy-cells = <0>; 305 reg = <0>; 306 }; 307 308 usbphyc_port1: usb-phy@1 { 309 #phy-cells = <1>; 310 reg = <1>; 311 }; 312 }; 313 314 rtc: rtc@5c004000 { 315 compatible = "st,stm32mp1-rtc"; 316 reg = <0x5c004000 0x400>; 317 clocks = <&rcc RTCAPB>, <&rcc RTC>; 318 clock-names = "pclk", "rtc_ck"; 319 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; 320 status = "disabled"; 321 }; 322 323 bsec: efuse@5c005000 { 324 compatible = "st,stm32mp15-bsec"; 325 reg = <0x5c005000 0x400>; 326 #address-cells = <1>; 327 #size-cells = <1>; 328 329 cfg0_otp: cfg0_otp@0 { 330 reg = <0x0 0x1>; 331 }; 332 part_number_otp: part_number_otp@4 { 333 reg = <0x4 0x1>; 334 }; 335 monotonic_otp: monotonic_otp@10 { 336 reg = <0x10 0x4>; 337 }; 338 nand_otp: nand_otp@24 { 339 reg = <0x24 0x4>; 340 }; 341 uid_otp: uid_otp@34 { 342 reg = <0x34 0xc>; 343 }; 344 package_otp: package_otp@40 { 345 reg = <0x40 0x4>; 346 }; 347 hw2_otp: hw2_otp@48 { 348 reg = <0x48 0x4>; 349 }; 350 ts_cal1: calib@5c { 351 reg = <0x5c 0x2>; 352 }; 353 ts_cal2: calib@5e { 354 reg = <0x5e 0x2>; 355 }; 356 pkh_otp: pkh_otp@60 { 357 reg = <0x60 0x20>; 358 }; 359 ethernet_mac_address: mac@e4 { 360 reg = <0xe4 0x8>; 361 st,non-secure-otp; 362 }; 363 }; 364 365 tamp: tamp@5c00a000 { 366 compatible = "st,stm32-tamp", "syscon", "simple-mfd"; 367 reg = <0x5c00a000 0x400>; 368 clocks = <&rcc RTCAPB>; 369 st,backup-zones = <10 5 17>; 370 }; 371 372 /* 373 * Break node order to solve dependency probe issue between 374 * pinctrl and exti. 375 */ 376 pinctrl: pinctrl@50002000 { 377 #address-cells = <1>; 378 #size-cells = <1>; 379 compatible = "st,stm32mp157-pinctrl"; 380 ranges = <0 0x50002000 0xa400>; 381 interrupt-parent = <&exti>; 382 st,syscfg = <&exti 0x60 0xff>; 383 pins-are-numbered; 384 385 gpioa: gpio@50002000 { 386 gpio-controller; 387 #gpio-cells = <2>; 388 interrupt-controller; 389 #interrupt-cells = <2>; 390 reg = <0x0 0x400>; 391 clocks = <&rcc GPIOA>; 392 st,bank-name = "GPIOA"; 393 status = "disabled"; 394 }; 395 396 gpiob: gpio@50003000 { 397 gpio-controller; 398 #gpio-cells = <2>; 399 interrupt-controller; 400 #interrupt-cells = <2>; 401 reg = <0x1000 0x400>; 402 clocks = <&rcc GPIOB>; 403 st,bank-name = "GPIOB"; 404 status = "disabled"; 405 }; 406 407 gpioc: gpio@50004000 { 408 gpio-controller; 409 #gpio-cells = <2>; 410 interrupt-controller; 411 #interrupt-cells = <2>; 412 reg = <0x2000 0x400>; 413 clocks = <&rcc GPIOC>; 414 st,bank-name = "GPIOC"; 415 status = "disabled"; 416 }; 417 418 gpiod: gpio@50005000 { 419 gpio-controller; 420 #gpio-cells = <2>; 421 interrupt-controller; 422 #interrupt-cells = <2>; 423 reg = <0x3000 0x400>; 424 clocks = <&rcc GPIOD>; 425 st,bank-name = "GPIOD"; 426 status = "disabled"; 427 }; 428 429 gpioe: gpio@50006000 { 430 gpio-controller; 431 #gpio-cells = <2>; 432 interrupt-controller; 433 #interrupt-cells = <2>; 434 reg = <0x4000 0x400>; 435 clocks = <&rcc GPIOE>; 436 st,bank-name = "GPIOE"; 437 status = "disabled"; 438 }; 439 440 gpiof: gpio@50007000 { 441 gpio-controller; 442 #gpio-cells = <2>; 443 interrupt-controller; 444 #interrupt-cells = <2>; 445 reg = <0x5000 0x400>; 446 clocks = <&rcc GPIOF>; 447 st,bank-name = "GPIOF"; 448 status = "disabled"; 449 }; 450 451 gpiog: gpio@50008000 { 452 gpio-controller; 453 #gpio-cells = <2>; 454 interrupt-controller; 455 #interrupt-cells = <2>; 456 reg = <0x6000 0x400>; 457 clocks = <&rcc GPIOG>; 458 st,bank-name = "GPIOG"; 459 status = "disabled"; 460 }; 461 462 gpioh: gpio@50009000 { 463 gpio-controller; 464 #gpio-cells = <2>; 465 interrupt-controller; 466 #interrupt-cells = <2>; 467 reg = <0x7000 0x400>; 468 clocks = <&rcc GPIOH>; 469 st,bank-name = "GPIOH"; 470 status = "disabled"; 471 }; 472 473 gpioi: gpio@5000a000 { 474 gpio-controller; 475 #gpio-cells = <2>; 476 interrupt-controller; 477 #interrupt-cells = <2>; 478 reg = <0x8000 0x400>; 479 clocks = <&rcc GPIOI>; 480 st,bank-name = "GPIOI"; 481 status = "disabled"; 482 }; 483 484 gpioj: gpio@5000b000 { 485 gpio-controller; 486 #gpio-cells = <2>; 487 interrupt-controller; 488 #interrupt-cells = <2>; 489 reg = <0x9000 0x400>; 490 clocks = <&rcc GPIOJ>; 491 st,bank-name = "GPIOJ"; 492 status = "disabled"; 493 }; 494 495 gpiok: gpio@5000c000 { 496 gpio-controller; 497 #gpio-cells = <2>; 498 interrupt-controller; 499 #interrupt-cells = <2>; 500 reg = <0xa000 0x400>; 501 clocks = <&rcc GPIOK>; 502 st,bank-name = "GPIOK"; 503 status = "disabled"; 504 }; 505 }; 506 507 pinctrl_z: pinctrl@54004000 { 508 #address-cells = <1>; 509 #size-cells = <1>; 510 compatible = "st,stm32mp157-z-pinctrl"; 511 ranges = <0 0x54004000 0x400>; 512 pins-are-numbered; 513 interrupt-parent = <&exti>; 514 st,syscfg = <&exti 0x60 0xff>; 515 516 gpioz: gpio@54004000 { 517 gpio-controller; 518 #gpio-cells = <2>; 519 interrupt-controller; 520 #interrupt-cells = <2>; 521 #access-controller-cells = <1>; 522 reg = <0 0x400>; 523 clocks = <&rcc GPIOZ>; 524 st,bank-name = "GPIOZ"; 525 st,bank-ioport = <11>; 526 status = "disabled"; 527 }; 528 }; 529 530 tzc400: tzc@5c006000 { 531 compatible = "st,stm32mp1-tzc"; 532 reg = <0x5c006000 0x1000>; 533 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 534 clocks = <&rcc TZC1>, <&rcc TZC2>; 535 st,mem-map = <0xc0000000 0x40000000>; 536 }; 537 538 etzpc: etzpc@5c007000 { 539 compatible = "st,stm32-etzpc", "simple-bus"; 540 reg = <0x5C007000 0x400>; 541 clocks = <&rcc TZPC>; 542 #address-cells = <1>; 543 #size-cells = <1>; 544 #access-controller-cells = <1>; 545 546 timers2: timer@40000000 { 547 #address-cells = <1>; 548 #size-cells = <0>; 549 compatible = "st,stm32-timers"; 550 reg = <0x40000000 0x400>; 551 clocks = <&rcc TIM2_K>; 552 clock-names = "int"; 553 dmas = <&dmamux1 18 0x400 0x1>, 554 <&dmamux1 19 0x400 0x1>, 555 <&dmamux1 20 0x400 0x1>, 556 <&dmamux1 21 0x400 0x1>, 557 <&dmamux1 22 0x400 0x1>; 558 dma-names = "ch1", "ch2", "ch3", "ch4", "up"; 559 access-controllers = <&etzpc STM32MP1_ETZPC_TIM2_ID>; 560 status = "disabled"; 561 562 pwm { 563 compatible = "st,stm32-pwm"; 564 #pwm-cells = <3>; 565 status = "disabled"; 566 }; 567 568 timer@1 { 569 compatible = "st,stm32h7-timer-trigger"; 570 reg = <1>; 571 status = "disabled"; 572 }; 573 574 counter { 575 compatible = "st,stm32-timer-counter"; 576 status = "disabled"; 577 }; 578 }; 579 580 timers3: timer@40001000 { 581 #address-cells = <1>; 582 #size-cells = <0>; 583 compatible = "st,stm32-timers"; 584 reg = <0x40001000 0x400>; 585 clocks = <&rcc TIM3_K>; 586 clock-names = "int"; 587 dmas = <&dmamux1 23 0x400 0x1>, 588 <&dmamux1 24 0x400 0x1>, 589 <&dmamux1 25 0x400 0x1>, 590 <&dmamux1 26 0x400 0x1>, 591 <&dmamux1 27 0x400 0x1>, 592 <&dmamux1 28 0x400 0x1>; 593 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 594 access-controllers = <&etzpc STM32MP1_ETZPC_TIM3_ID>; 595 status = "disabled"; 596 597 pwm { 598 compatible = "st,stm32-pwm"; 599 #pwm-cells = <3>; 600 status = "disabled"; 601 }; 602 603 timer@2 { 604 compatible = "st,stm32h7-timer-trigger"; 605 reg = <2>; 606 status = "disabled"; 607 }; 608 609 counter { 610 compatible = "st,stm32-timer-counter"; 611 status = "disabled"; 612 }; 613 }; 614 615 timers4: timer@40002000 { 616 #address-cells = <1>; 617 #size-cells = <0>; 618 compatible = "st,stm32-timers"; 619 reg = <0x40002000 0x400>; 620 clocks = <&rcc TIM4_K>; 621 clock-names = "int"; 622 dmas = <&dmamux1 29 0x400 0x1>, 623 <&dmamux1 30 0x400 0x1>, 624 <&dmamux1 31 0x400 0x1>, 625 <&dmamux1 32 0x400 0x1>; 626 dma-names = "ch1", "ch2", "ch3", "ch4"; 627 access-controllers = <&etzpc STM32MP1_ETZPC_TIM4_ID>; 628 status = "disabled"; 629 630 pwm { 631 compatible = "st,stm32-pwm"; 632 #pwm-cells = <3>; 633 status = "disabled"; 634 }; 635 636 timer@3 { 637 compatible = "st,stm32h7-timer-trigger"; 638 reg = <3>; 639 status = "disabled"; 640 }; 641 642 counter { 643 compatible = "st,stm32-timer-counter"; 644 status = "disabled"; 645 }; 646 }; 647 648 timers5: timer@40003000 { 649 #address-cells = <1>; 650 #size-cells = <0>; 651 compatible = "st,stm32-timers"; 652 reg = <0x40003000 0x400>; 653 clocks = <&rcc TIM5_K>; 654 clock-names = "int"; 655 dmas = <&dmamux1 55 0x400 0x1>, 656 <&dmamux1 56 0x400 0x1>, 657 <&dmamux1 57 0x400 0x1>, 658 <&dmamux1 58 0x400 0x1>, 659 <&dmamux1 59 0x400 0x1>, 660 <&dmamux1 60 0x400 0x1>; 661 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 662 access-controllers = <&etzpc STM32MP1_ETZPC_TIM5_ID>; 663 status = "disabled"; 664 665 pwm { 666 compatible = "st,stm32-pwm"; 667 #pwm-cells = <3>; 668 status = "disabled"; 669 }; 670 671 timer@4 { 672 compatible = "st,stm32h7-timer-trigger"; 673 reg = <4>; 674 status = "disabled"; 675 }; 676 677 counter { 678 compatible = "st,stm32-timer-counter"; 679 status = "disabled"; 680 }; 681 }; 682 683 timers6: timer@40004000 { 684 #address-cells = <1>; 685 #size-cells = <0>; 686 compatible = "st,stm32-timers"; 687 reg = <0x40004000 0x400>; 688 clocks = <&rcc TIM6_K>; 689 clock-names = "int"; 690 dmas = <&dmamux1 69 0x400 0x1>; 691 dma-names = "up"; 692 access-controllers = <&etzpc STM32MP1_ETZPC_TIM6_ID>; 693 status = "disabled"; 694 695 timer@5 { 696 compatible = "st,stm32h7-timer-trigger"; 697 reg = <5>; 698 status = "disabled"; 699 }; 700 }; 701 702 timers7: timer@40005000 { 703 #address-cells = <1>; 704 #size-cells = <0>; 705 compatible = "st,stm32-timers"; 706 reg = <0x40005000 0x400>; 707 clocks = <&rcc TIM7_K>; 708 clock-names = "int"; 709 dmas = <&dmamux1 70 0x400 0x1>; 710 dma-names = "up"; 711 access-controllers = <&etzpc STM32MP1_ETZPC_TIM7_ID>; 712 status = "disabled"; 713 714 timer@6 { 715 compatible = "st,stm32h7-timer-trigger"; 716 reg = <6>; 717 status = "disabled"; 718 }; 719 }; 720 721 timers12: timer@40006000 { 722 #address-cells = <1>; 723 #size-cells = <0>; 724 compatible = "st,stm32-timers"; 725 reg = <0x40006000 0x400>; 726 clocks = <&rcc TIM12_K>; 727 clock-names = "int"; 728 access-controllers = <&etzpc STM32MP1_ETZPC_TIM12_ID>; 729 status = "disabled"; 730 731 pwm { 732 compatible = "st,stm32-pwm"; 733 #pwm-cells = <3>; 734 status = "disabled"; 735 }; 736 737 timer@11 { 738 compatible = "st,stm32h7-timer-trigger"; 739 reg = <11>; 740 status = "disabled"; 741 }; 742 }; 743 744 timers13: timer@40007000 { 745 #address-cells = <1>; 746 #size-cells = <0>; 747 compatible = "st,stm32-timers"; 748 reg = <0x40007000 0x400>; 749 clocks = <&rcc TIM13_K>; 750 clock-names = "int"; 751 access-controllers = <&etzpc STM32MP1_ETZPC_TIM13_ID>; 752 status = "disabled"; 753 754 pwm { 755 compatible = "st,stm32-pwm"; 756 #pwm-cells = <3>; 757 status = "disabled"; 758 }; 759 760 timer@12 { 761 compatible = "st,stm32h7-timer-trigger"; 762 reg = <12>; 763 status = "disabled"; 764 }; 765 }; 766 767 timers14: timer@40008000 { 768 #address-cells = <1>; 769 #size-cells = <0>; 770 compatible = "st,stm32-timers"; 771 reg = <0x40008000 0x400>; 772 clocks = <&rcc TIM14_K>; 773 clock-names = "int"; 774 access-controllers = <&etzpc STM32MP1_ETZPC_TIM14_ID>; 775 status = "disabled"; 776 777 pwm { 778 compatible = "st,stm32-pwm"; 779 #pwm-cells = <3>; 780 status = "disabled"; 781 }; 782 783 timer@13 { 784 compatible = "st,stm32h7-timer-trigger"; 785 reg = <13>; 786 status = "disabled"; 787 }; 788 }; 789 790 lptimer1: timer@40009000 { 791 #address-cells = <1>; 792 #size-cells = <0>; 793 compatible = "st,stm32-lptimer"; 794 reg = <0x40009000 0x400>; 795 interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; 796 clocks = <&rcc LPTIM1_K>; 797 clock-names = "mux"; 798 wakeup-source; 799 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM1_ID>; 800 status = "disabled"; 801 802 pwm { 803 compatible = "st,stm32-pwm-lp"; 804 #pwm-cells = <3>; 805 status = "disabled"; 806 }; 807 808 trigger@0 { 809 compatible = "st,stm32-lptimer-trigger"; 810 reg = <0>; 811 status = "disabled"; 812 }; 813 814 counter { 815 compatible = "st,stm32-lptimer-counter"; 816 status = "disabled"; 817 }; 818 }; 819 820 spi2: spi@4000b000 { 821 #address-cells = <1>; 822 #size-cells = <0>; 823 compatible = "st,stm32h7-spi"; 824 reg = <0x4000b000 0x400>; 825 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 826 clocks = <&rcc SPI2_K>; 827 resets = <&rcc SPI2_R>; 828 dmas = <&dmamux1 39 0x400 0x05>, 829 <&dmamux1 40 0x400 0x05>; 830 dma-names = "rx", "tx"; 831 access-controllers = <&etzpc STM32MP1_ETZPC_SPI2_ID>; 832 status = "disabled"; 833 }; 834 835 i2s2: audio-controller@4000b000 { 836 compatible = "st,stm32h7-i2s"; 837 #sound-dai-cells = <0>; 838 reg = <0x4000b000 0x400>; 839 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 840 dmas = <&dmamux1 39 0x400 0x01>, 841 <&dmamux1 40 0x400 0x01>; 842 dma-names = "rx", "tx"; 843 access-controllers = <&etzpc STM32MP1_ETZPC_SPI2_ID>; 844 status = "disabled"; 845 }; 846 847 spi3: spi@4000c000 { 848 #address-cells = <1>; 849 #size-cells = <0>; 850 compatible = "st,stm32h7-spi"; 851 reg = <0x4000c000 0x400>; 852 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 853 clocks = <&rcc SPI3_K>; 854 resets = <&rcc SPI3_R>; 855 dmas = <&dmamux1 61 0x400 0x05>, 856 <&dmamux1 62 0x400 0x05>; 857 dma-names = "rx", "tx"; 858 access-controllers = <&etzpc STM32MP1_ETZPC_SPI3_ID>; 859 status = "disabled"; 860 }; 861 862 i2s3: audio-controller@4000c000 { 863 compatible = "st,stm32h7-i2s"; 864 #sound-dai-cells = <0>; 865 reg = <0x4000c000 0x400>; 866 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 867 dmas = <&dmamux1 61 0x400 0x01>, 868 <&dmamux1 62 0x400 0x01>; 869 dma-names = "rx", "tx"; 870 access-controllers = <&etzpc STM32MP1_ETZPC_SPI3_ID>; 871 status = "disabled"; 872 }; 873 874 spdifrx: audio-controller@4000d000 { 875 compatible = "st,stm32h7-spdifrx"; 876 #sound-dai-cells = <0>; 877 reg = <0x4000d000 0x400>; 878 clocks = <&rcc SPDIF_K>; 879 clock-names = "kclk"; 880 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 881 dmas = <&dmamux1 93 0x400 0x01>, 882 <&dmamux1 94 0x400 0x01>; 883 dma-names = "rx", "rx-ctrl"; 884 access-controllers = <&etzpc STM32MP1_ETZPC_SPDIFRX_ID>; 885 status = "disabled"; 886 }; 887 888 usart2: serial@4000e000 { 889 compatible = "st,stm32h7-uart"; 890 reg = <0x4000e000 0x400>; 891 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; 892 clocks = <&rcc USART2_K>; 893 wakeup-source; 894 dmas = <&dmamux1 43 0x400 0x15>, 895 <&dmamux1 44 0x400 0x11>; 896 dma-names = "rx", "tx"; 897 access-controllers = <&etzpc STM32MP1_ETZPC_USART2_ID>; 898 status = "disabled"; 899 }; 900 901 usart3: serial@4000f000 { 902 compatible = "st,stm32h7-uart"; 903 reg = <0x4000f000 0x400>; 904 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; 905 clocks = <&rcc USART3_K>; 906 wakeup-source; 907 dmas = <&dmamux1 45 0x400 0x15>, 908 <&dmamux1 46 0x400 0x11>; 909 dma-names = "rx", "tx"; 910 access-controllers = <&etzpc STM32MP1_ETZPC_USART3_ID>; 911 status = "disabled"; 912 }; 913 914 uart4: serial@40010000 { 915 compatible = "st,stm32h7-uart"; 916 reg = <0x40010000 0x400>; 917 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; 918 clocks = <&rcc UART4_K>; 919 wakeup-source; 920 dmas = <&dmamux1 63 0x400 0x15>, 921 <&dmamux1 64 0x400 0x11>; 922 dma-names = "rx", "tx"; 923 access-controllers = <&etzpc STM32MP1_ETZPC_UART4_ID>; 924 status = "disabled"; 925 }; 926 927 uart5: serial@40011000 { 928 compatible = "st,stm32h7-uart"; 929 reg = <0x40011000 0x400>; 930 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; 931 clocks = <&rcc UART5_K>; 932 wakeup-source; 933 dmas = <&dmamux1 65 0x400 0x15>, 934 <&dmamux1 66 0x400 0x11>; 935 dma-names = "rx", "tx"; 936 access-controllers = <&etzpc STM32MP1_ETZPC_UART5_ID>; 937 status = "disabled"; 938 }; 939 940 i2c1: i2c@40012000 { 941 compatible = "st,stm32mp15-i2c"; 942 reg = <0x40012000 0x400>; 943 interrupt-names = "event", "error"; 944 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 946 clocks = <&rcc I2C1_K>; 947 resets = <&rcc I2C1_R>; 948 #address-cells = <1>; 949 #size-cells = <0>; 950 st,syscfg-fmp = <&syscfg 0x4 0x1>; 951 wakeup-source; 952 i2c-analog-filter; 953 access-controllers = <&etzpc STM32MP1_ETZPC_I2C1_ID>; 954 status = "disabled"; 955 }; 956 957 i2c2: i2c@40013000 { 958 compatible = "st,stm32mp15-i2c"; 959 reg = <0x40013000 0x400>; 960 interrupt-names = "event", "error"; 961 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 962 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 963 clocks = <&rcc I2C2_K>; 964 resets = <&rcc I2C2_R>; 965 #address-cells = <1>; 966 #size-cells = <0>; 967 st,syscfg-fmp = <&syscfg 0x4 0x2>; 968 wakeup-source; 969 i2c-analog-filter; 970 access-controllers = <&etzpc STM32MP1_ETZPC_I2C2_ID>; 971 status = "disabled"; 972 }; 973 974 i2c3: i2c@40014000 { 975 compatible = "st,stm32mp15-i2c"; 976 reg = <0x40014000 0x400>; 977 interrupt-names = "event", "error"; 978 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 979 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 980 clocks = <&rcc I2C3_K>; 981 resets = <&rcc I2C3_R>; 982 #address-cells = <1>; 983 #size-cells = <0>; 984 st,syscfg-fmp = <&syscfg 0x4 0x4>; 985 wakeup-source; 986 i2c-analog-filter; 987 access-controllers = <&etzpc STM32MP1_ETZPC_I2C3_ID>; 988 status = "disabled"; 989 }; 990 991 i2c5: i2c@40015000 { 992 compatible = "st,stm32mp15-i2c"; 993 reg = <0x40015000 0x400>; 994 interrupt-names = "event", "error"; 995 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 997 clocks = <&rcc I2C5_K>; 998 resets = <&rcc I2C5_R>; 999 #address-cells = <1>; 1000 #size-cells = <0>; 1001 st,syscfg-fmp = <&syscfg 0x4 0x10>; 1002 wakeup-source; 1003 i2c-analog-filter; 1004 access-controllers = <&etzpc STM32MP1_ETZPC_I2C5_ID>; 1005 status = "disabled"; 1006 }; 1007 1008 cec: cec@40016000 { 1009 compatible = "st,stm32-cec"; 1010 reg = <0x40016000 0x400>; 1011 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1012 clocks = <&rcc CEC_K>, <&rcc CEC>; 1013 clock-names = "cec", "hdmi-cec"; 1014 access-controllers = <&etzpc STM32MP1_ETZPC_CEC_ID>; 1015 status = "disabled"; 1016 }; 1017 1018 dac: dac@40017000 { 1019 compatible = "st,stm32h7-dac-core"; 1020 reg = <0x40017000 0x400>; 1021 clocks = <&rcc DAC12>; 1022 clock-names = "pclk"; 1023 #address-cells = <1>; 1024 #size-cells = <0>; 1025 access-controllers = <&etzpc STM32MP1_ETZPC_DAC_ID>; 1026 status = "disabled"; 1027 1028 dac1: dac@1 { 1029 compatible = "st,stm32-dac"; 1030 #io-channel-cells = <1>; 1031 reg = <1>; 1032 status = "disabled"; 1033 }; 1034 1035 dac2: dac@2 { 1036 compatible = "st,stm32-dac"; 1037 #io-channel-cells = <1>; 1038 reg = <2>; 1039 status = "disabled"; 1040 }; 1041 }; 1042 1043 uart7: serial@40018000 { 1044 compatible = "st,stm32h7-uart"; 1045 reg = <0x40018000 0x400>; 1046 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; 1047 clocks = <&rcc UART7_K>; 1048 wakeup-source; 1049 dmas = <&dmamux1 79 0x400 0x15>, 1050 <&dmamux1 80 0x400 0x11>; 1051 dma-names = "rx", "tx"; 1052 access-controllers = <&etzpc STM32MP1_ETZPC_UART7_ID>; 1053 status = "disabled"; 1054 }; 1055 1056 uart8: serial@40019000 { 1057 compatible = "st,stm32h7-uart"; 1058 reg = <0x40019000 0x400>; 1059 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; 1060 clocks = <&rcc UART8_K>; 1061 wakeup-source; 1062 dmas = <&dmamux1 81 0x400 0x15>, 1063 <&dmamux1 82 0x400 0x11>; 1064 dma-names = "rx", "tx"; 1065 access-controllers = <&etzpc STM32MP1_ETZPC_UART8_ID>; 1066 status = "disabled"; 1067 }; 1068 1069 timers1: timer@44000000 { 1070 #address-cells = <1>; 1071 #size-cells = <0>; 1072 compatible = "st,stm32-timers"; 1073 reg = <0x44000000 0x400>; 1074 clocks = <&rcc TIM1_K>; 1075 clock-names = "int"; 1076 dmas = <&dmamux1 11 0x400 0x1>, 1077 <&dmamux1 12 0x400 0x1>, 1078 <&dmamux1 13 0x400 0x1>, 1079 <&dmamux1 14 0x400 0x1>, 1080 <&dmamux1 15 0x400 0x1>, 1081 <&dmamux1 16 0x400 0x1>, 1082 <&dmamux1 17 0x400 0x1>; 1083 dma-names = "ch1", "ch2", "ch3", "ch4", 1084 "up", "trig", "com"; 1085 access-controllers = <&etzpc STM32MP1_ETZPC_TIM1_ID>; 1086 status = "disabled"; 1087 1088 pwm { 1089 compatible = "st,stm32-pwm"; 1090 #pwm-cells = <3>; 1091 status = "disabled"; 1092 }; 1093 1094 timer@0 { 1095 compatible = "st,stm32h7-timer-trigger"; 1096 reg = <0>; 1097 status = "disabled"; 1098 }; 1099 1100 counter { 1101 compatible = "st,stm32-timer-counter"; 1102 status = "disabled"; 1103 }; 1104 }; 1105 1106 timers8: timer@44001000 { 1107 #address-cells = <1>; 1108 #size-cells = <0>; 1109 compatible = "st,stm32-timers"; 1110 reg = <0x44001000 0x400>; 1111 clocks = <&rcc TIM8_K>; 1112 clock-names = "int"; 1113 dmas = <&dmamux1 47 0x400 0x1>, 1114 <&dmamux1 48 0x400 0x1>, 1115 <&dmamux1 49 0x400 0x1>, 1116 <&dmamux1 50 0x400 0x1>, 1117 <&dmamux1 51 0x400 0x1>, 1118 <&dmamux1 52 0x400 0x1>, 1119 <&dmamux1 53 0x400 0x1>; 1120 dma-names = "ch1", "ch2", "ch3", "ch4", 1121 "up", "trig", "com"; 1122 access-controllers = <&etzpc STM32MP1_ETZPC_TIM8_ID>; 1123 status = "disabled"; 1124 1125 pwm { 1126 compatible = "st,stm32-pwm"; 1127 #pwm-cells = <3>; 1128 status = "disabled"; 1129 }; 1130 1131 timer@7 { 1132 compatible = "st,stm32h7-timer-trigger"; 1133 reg = <7>; 1134 status = "disabled"; 1135 }; 1136 1137 counter { 1138 compatible = "st,stm32-timer-counter"; 1139 status = "disabled"; 1140 }; 1141 }; 1142 1143 usart6: serial@44003000 { 1144 compatible = "st,stm32h7-uart"; 1145 reg = <0x44003000 0x400>; 1146 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; 1147 clocks = <&rcc USART6_K>; 1148 wakeup-source; 1149 dmas = <&dmamux1 71 0x400 0x15>, 1150 <&dmamux1 72 0x400 0x11>; 1151 dma-names = "rx", "tx"; 1152 access-controllers = <&etzpc STM32MP1_ETZPC_USART6_ID>; 1153 status = "disabled"; 1154 }; 1155 1156 spi1: spi@44004000 { 1157 #address-cells = <1>; 1158 #size-cells = <0>; 1159 compatible = "st,stm32h7-spi"; 1160 reg = <0x44004000 0x400>; 1161 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1162 clocks = <&rcc SPI1_K>; 1163 resets = <&rcc SPI1_R>; 1164 dmas = <&dmamux1 37 0x400 0x05>, 1165 <&dmamux1 38 0x400 0x05>; 1166 dma-names = "rx", "tx"; 1167 access-controllers = <&etzpc STM32MP1_ETZPC_SPI1_ID>; 1168 status = "disabled"; 1169 }; 1170 1171 i2s1: audio-controller@44004000 { 1172 compatible = "st,stm32h7-i2s"; 1173 #sound-dai-cells = <0>; 1174 reg = <0x44004000 0x400>; 1175 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1176 dmas = <&dmamux1 37 0x400 0x01>, 1177 <&dmamux1 38 0x400 0x01>; 1178 dma-names = "rx", "tx"; 1179 access-controllers = <&etzpc STM32MP1_ETZPC_SPI1_ID>; 1180 status = "disabled"; 1181 }; 1182 1183 spi4: spi@44005000 { 1184 #address-cells = <1>; 1185 #size-cells = <0>; 1186 compatible = "st,stm32h7-spi"; 1187 reg = <0x44005000 0x400>; 1188 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1189 clocks = <&rcc SPI4_K>; 1190 resets = <&rcc SPI4_R>; 1191 dmas = <&dmamux1 83 0x400 0x05>, 1192 <&dmamux1 84 0x400 0x05>; 1193 dma-names = "rx", "tx"; 1194 access-controllers = <&etzpc STM32MP1_ETZPC_SPI4_ID>; 1195 status = "disabled"; 1196 }; 1197 1198 timers15: timer@44006000 { 1199 #address-cells = <1>; 1200 #size-cells = <0>; 1201 compatible = "st,stm32-timers"; 1202 reg = <0x44006000 0x400>; 1203 clocks = <&rcc TIM15_K>; 1204 clock-names = "int"; 1205 dmas = <&dmamux1 105 0x400 0x1>, 1206 <&dmamux1 106 0x400 0x1>, 1207 <&dmamux1 107 0x400 0x1>, 1208 <&dmamux1 108 0x400 0x1>; 1209 dma-names = "ch1", "up", "trig", "com"; 1210 access-controllers = <&etzpc STM32MP1_ETZPC_TIM15_ID>; 1211 status = "disabled"; 1212 1213 pwm { 1214 compatible = "st,stm32-pwm"; 1215 #pwm-cells = <3>; 1216 status = "disabled"; 1217 }; 1218 1219 timer@14 { 1220 compatible = "st,stm32h7-timer-trigger"; 1221 reg = <14>; 1222 status = "disabled"; 1223 }; 1224 }; 1225 1226 timers16: timer@44007000 { 1227 #address-cells = <1>; 1228 #size-cells = <0>; 1229 compatible = "st,stm32-timers"; 1230 reg = <0x44007000 0x400>; 1231 clocks = <&rcc TIM16_K>; 1232 clock-names = "int"; 1233 dmas = <&dmamux1 109 0x400 0x1>, 1234 <&dmamux1 110 0x400 0x1>; 1235 dma-names = "ch1", "up"; 1236 access-controllers = <&etzpc STM32MP1_ETZPC_TIM16_ID>; 1237 status = "disabled"; 1238 1239 pwm { 1240 compatible = "st,stm32-pwm"; 1241 #pwm-cells = <3>; 1242 status = "disabled"; 1243 }; 1244 timer@15 { 1245 compatible = "st,stm32h7-timer-trigger"; 1246 reg = <15>; 1247 status = "disabled"; 1248 }; 1249 }; 1250 1251 timers17: timer@44008000 { 1252 #address-cells = <1>; 1253 #size-cells = <0>; 1254 compatible = "st,stm32-timers"; 1255 reg = <0x44008000 0x400>; 1256 clocks = <&rcc TIM17_K>; 1257 clock-names = "int"; 1258 dmas = <&dmamux1 111 0x400 0x1>, 1259 <&dmamux1 112 0x400 0x1>; 1260 dma-names = "ch1", "up"; 1261 access-controllers = <&etzpc STM32MP1_ETZPC_TIM17_ID>; 1262 status = "disabled"; 1263 1264 pwm { 1265 compatible = "st,stm32-pwm"; 1266 #pwm-cells = <3>; 1267 status = "disabled"; 1268 }; 1269 1270 timer@16 { 1271 compatible = "st,stm32h7-timer-trigger"; 1272 reg = <16>; 1273 status = "disabled"; 1274 }; 1275 }; 1276 1277 spi5: spi@44009000 { 1278 #address-cells = <1>; 1279 #size-cells = <0>; 1280 compatible = "st,stm32h7-spi"; 1281 reg = <0x44009000 0x400>; 1282 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1283 clocks = <&rcc SPI5_K>; 1284 resets = <&rcc SPI5_R>; 1285 dmas = <&dmamux1 85 0x400 0x05>, 1286 <&dmamux1 86 0x400 0x05>; 1287 dma-names = "rx", "tx"; 1288 access-controllers = <&etzpc STM32MP1_ETZPC_SPI5_ID>; 1289 status = "disabled"; 1290 }; 1291 1292 sai1: sai@4400a000 { 1293 compatible = "st,stm32h7-sai"; 1294 #address-cells = <1>; 1295 #size-cells = <1>; 1296 ranges = <0 0x4400a000 0x400>; 1297 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; 1298 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1299 resets = <&rcc SAI1_R>; 1300 access-controllers = <&etzpc STM32MP1_ETZPC_SAI1_ID>; 1301 status = "disabled"; 1302 1303 sai1a: audio-controller@4400a004 { 1304 #sound-dai-cells = <0>; 1305 1306 compatible = "st,stm32-sai-sub-a"; 1307 reg = <0x4 0x20>; 1308 clocks = <&rcc SAI1_K>; 1309 clock-names = "sai_ck"; 1310 dmas = <&dmamux1 87 0x400 0x01>; 1311 status = "disabled"; 1312 }; 1313 1314 sai1b: audio-controller@4400a024 { 1315 #sound-dai-cells = <0>; 1316 compatible = "st,stm32-sai-sub-b"; 1317 reg = <0x24 0x20>; 1318 clocks = <&rcc SAI1_K>; 1319 clock-names = "sai_ck"; 1320 dmas = <&dmamux1 88 0x400 0x01>; 1321 status = "disabled"; 1322 }; 1323 }; 1324 1325 sai2: sai@4400b000 { 1326 compatible = "st,stm32h7-sai"; 1327 #address-cells = <1>; 1328 #size-cells = <1>; 1329 ranges = <0 0x4400b000 0x400>; 1330 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; 1331 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1332 resets = <&rcc SAI2_R>; 1333 access-controllers = <&etzpc STM32MP1_ETZPC_SAI2_ID>; 1334 status = "disabled"; 1335 1336 sai2a: audio-controller@4400b004 { 1337 #sound-dai-cells = <0>; 1338 compatible = "st,stm32-sai-sub-a"; 1339 reg = <0x4 0x20>; 1340 clocks = <&rcc SAI2_K>; 1341 clock-names = "sai_ck"; 1342 dmas = <&dmamux1 89 0x400 0x01>; 1343 status = "disabled"; 1344 }; 1345 1346 sai2b: audio-controller@4400b024 { 1347 #sound-dai-cells = <0>; 1348 compatible = "st,stm32-sai-sub-b"; 1349 reg = <0x24 0x20>; 1350 clocks = <&rcc SAI2_K>; 1351 clock-names = "sai_ck"; 1352 dmas = <&dmamux1 90 0x400 0x01>; 1353 status = "disabled"; 1354 }; 1355 }; 1356 1357 sai3: sai@4400c000 { 1358 compatible = "st,stm32h7-sai"; 1359 #address-cells = <1>; 1360 #size-cells = <1>; 1361 ranges = <0 0x4400c000 0x400>; 1362 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; 1363 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1364 resets = <&rcc SAI3_R>; 1365 access-controllers = <&etzpc STM32MP1_ETZPC_SAI3_ID>; 1366 status = "disabled"; 1367 1368 sai3a: audio-controller@4400c004 { 1369 #sound-dai-cells = <0>; 1370 compatible = "st,stm32-sai-sub-a"; 1371 reg = <0x04 0x20>; 1372 clocks = <&rcc SAI3_K>; 1373 clock-names = "sai_ck"; 1374 dmas = <&dmamux1 113 0x400 0x01>; 1375 status = "disabled"; 1376 }; 1377 1378 sai3b: audio-controller@4400c024 { 1379 #sound-dai-cells = <0>; 1380 compatible = "st,stm32-sai-sub-b"; 1381 reg = <0x24 0x20>; 1382 clocks = <&rcc SAI3_K>; 1383 clock-names = "sai_ck"; 1384 dmas = <&dmamux1 114 0x400 0x01>; 1385 status = "disabled"; 1386 }; 1387 }; 1388 1389 dfsdm: dfsdm@4400d000 { 1390 compatible = "st,stm32mp1-dfsdm"; 1391 reg = <0x4400d000 0x800>; 1392 clocks = <&rcc DFSDM_K>; 1393 clock-names = "dfsdm"; 1394 #address-cells = <1>; 1395 #size-cells = <0>; 1396 access-controllers = <&etzpc STM32MP1_ETZPC_DFSDM_ID>; 1397 status = "disabled"; 1398 1399 dfsdm0: filter@0 { 1400 compatible = "st,stm32-dfsdm-adc"; 1401 #io-channel-cells = <1>; 1402 reg = <0>; 1403 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 1404 dmas = <&dmamux1 101 0x400 0x01>; 1405 dma-names = "rx"; 1406 status = "disabled"; 1407 }; 1408 1409 dfsdm1: filter@1 { 1410 compatible = "st,stm32-dfsdm-adc"; 1411 #io-channel-cells = <1>; 1412 reg = <1>; 1413 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1414 dmas = <&dmamux1 102 0x400 0x01>; 1415 dma-names = "rx"; 1416 status = "disabled"; 1417 }; 1418 1419 dfsdm2: filter@2 { 1420 compatible = "st,stm32-dfsdm-adc"; 1421 #io-channel-cells = <1>; 1422 reg = <2>; 1423 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1424 dmas = <&dmamux1 103 0x400 0x01>; 1425 dma-names = "rx"; 1426 status = "disabled"; 1427 }; 1428 1429 dfsdm3: filter@3 { 1430 compatible = "st,stm32-dfsdm-adc"; 1431 #io-channel-cells = <1>; 1432 reg = <3>; 1433 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1434 dmas = <&dmamux1 104 0x400 0x01>; 1435 dma-names = "rx"; 1436 status = "disabled"; 1437 }; 1438 1439 dfsdm4: filter@4 { 1440 compatible = "st,stm32-dfsdm-adc"; 1441 #io-channel-cells = <1>; 1442 reg = <4>; 1443 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1444 dmas = <&dmamux1 91 0x400 0x01>; 1445 dma-names = "rx"; 1446 status = "disabled"; 1447 }; 1448 1449 dfsdm5: filter@5 { 1450 compatible = "st,stm32-dfsdm-adc"; 1451 #io-channel-cells = <1>; 1452 reg = <5>; 1453 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1454 dmas = <&dmamux1 92 0x400 0x01>; 1455 dma-names = "rx"; 1456 status = "disabled"; 1457 }; 1458 }; 1459 1460 dma1: dma-controller@48000000 { 1461 compatible = "st,stm32-dma"; 1462 reg = <0x48000000 0x400>; 1463 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1466 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1471 clocks = <&rcc DMA1>; 1472 resets = <&rcc DMA1_R>; 1473 #dma-cells = <4>; 1474 st,mem2mem; 1475 dma-requests = <8>; 1476 access-controllers = <&etzpc STM32MP1_ETZPC_DMA1_ID>; 1477 status = "disabled"; 1478 }; 1479 1480 dma2: dma-controller@48001000 { 1481 compatible = "st,stm32-dma"; 1482 reg = <0x48001000 0x400>; 1483 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1490 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1491 clocks = <&rcc DMA2>; 1492 resets = <&rcc DMA2_R>; 1493 #dma-cells = <4>; 1494 st,mem2mem; 1495 dma-requests = <8>; 1496 access-controllers = <&etzpc STM32MP1_ETZPC_DMA2_ID>; 1497 status = "disabled"; 1498 }; 1499 1500 dmamux1: dma-router@48002000 { 1501 compatible = "st,stm32h7-dmamux"; 1502 reg = <0x48002000 0x40>; 1503 #dma-cells = <3>; 1504 dma-requests = <128>; 1505 dma-masters = <&dma1 &dma2>; 1506 dma-channels = <16>; 1507 clocks = <&rcc DMAMUX>; 1508 resets = <&rcc DMAMUX_R>; 1509 access-controllers = <&etzpc STM32MP1_ETZPC_DMAMUX_ID>; 1510 status = "disabled"; 1511 }; 1512 1513 adc: adc@48003000 { 1514 compatible = "st,stm32mp1-adc-core"; 1515 reg = <0x48003000 0x400>; 1516 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1517 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1518 clocks = <&rcc ADC12>, <&rcc ADC12_K>; 1519 clock-names = "bus", "adc"; 1520 interrupt-controller; 1521 st,syscfg = <&syscfg>; 1522 #interrupt-cells = <1>; 1523 #address-cells = <1>; 1524 #size-cells = <0>; 1525 access-controllers = <&etzpc STM32MP1_ETZPC_ADC_ID>; 1526 status = "disabled"; 1527 1528 adc1: adc@0 { 1529 compatible = "st,stm32mp1-adc"; 1530 #io-channel-cells = <1>; 1531 reg = <0x0>; 1532 interrupt-parent = <&adc>; 1533 interrupts = <0>; 1534 dmas = <&dmamux1 9 0x400 0x01>; 1535 dma-names = "rx"; 1536 status = "disabled"; 1537 }; 1538 1539 adc2: adc@100 { 1540 compatible = "st,stm32mp1-adc"; 1541 #io-channel-cells = <1>; 1542 reg = <0x100>; 1543 interrupt-parent = <&adc>; 1544 interrupts = <1>; 1545 dmas = <&dmamux1 10 0x400 0x01>; 1546 dma-names = "rx"; 1547 status = "disabled"; 1548 }; 1549 }; 1550 1551 sdmmc3: mmc@48004000 { 1552 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 1553 arm,primecell-periphid = <0x00253180>; 1554 reg = <0x48004000 0x400>; 1555 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1556 interrupt-names = "cmd_irq"; 1557 clocks = <&rcc SDMMC3_K>; 1558 clock-names = "apb_pclk"; 1559 resets = <&rcc SDMMC3_R>; 1560 cap-sd-highspeed; 1561 cap-mmc-highspeed; 1562 max-frequency = <120000000>; 1563 access-controllers = <&etzpc STM32MP1_ETZPC_SDMMC3_ID>; 1564 status = "disabled"; 1565 }; 1566 1567 usbotg_hs: usb-otg@49000000 { 1568 compatible = "st,stm32mp15-hsotg", "snps,dwc2"; 1569 reg = <0x49000000 0x10000>; 1570 clocks = <&rcc USBO_K>; 1571 clock-names = "otg"; 1572 resets = <&rcc USBO_R>; 1573 reset-names = "dwc2"; 1574 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1575 g-rx-fifo-size = <512>; 1576 g-np-tx-fifo-size = <32>; 1577 g-tx-fifo-size = <256 16 16 16 16 16 16 16>; 1578 dr_mode = "otg"; 1579 otg-rev = <0x200>; 1580 usb33d-supply = <&usb33>; 1581 access-controllers = <&etzpc STM32MP1_ETZPC_OTG_ID>; 1582 status = "disabled"; 1583 }; 1584 1585 dcmi: dcmi@4c006000 { 1586 compatible = "st,stm32-dcmi"; 1587 reg = <0x4c006000 0x400>; 1588 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1589 resets = <&rcc CAMITF_R>; 1590 clocks = <&rcc DCMI>; 1591 clock-names = "mclk"; 1592 dmas = <&dmamux1 75 0x400 0x01>; 1593 dma-names = "tx"; 1594 access-controllers = <&etzpc STM32MP1_ETZPC_DCMI_ID>; 1595 status = "disabled"; 1596 }; 1597 1598 lptimer2: timer@50021000 { 1599 #address-cells = <1>; 1600 #size-cells = <0>; 1601 compatible = "st,stm32-lptimer"; 1602 reg = <0x50021000 0x400>; 1603 interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; 1604 clocks = <&rcc LPTIM2_K>; 1605 clock-names = "mux"; 1606 wakeup-source; 1607 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM2_ID>; 1608 status = "disabled"; 1609 1610 pwm { 1611 compatible = "st,stm32-pwm-lp"; 1612 #pwm-cells = <3>; 1613 status = "disabled"; 1614 }; 1615 1616 trigger@1 { 1617 compatible = "st,stm32-lptimer-trigger"; 1618 reg = <1>; 1619 status = "disabled"; 1620 }; 1621 1622 counter { 1623 compatible = "st,stm32-lptimer-counter"; 1624 status = "disabled"; 1625 }; 1626 }; 1627 1628 lptimer3: timer@50022000 { 1629 #address-cells = <1>; 1630 #size-cells = <0>; 1631 compatible = "st,stm32-lptimer"; 1632 reg = <0x50022000 0x400>; 1633 interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; 1634 clocks = <&rcc LPTIM3_K>; 1635 clock-names = "mux"; 1636 wakeup-source; 1637 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM3_ID>; 1638 status = "disabled"; 1639 1640 pwm { 1641 compatible = "st,stm32-pwm-lp"; 1642 #pwm-cells = <3>; 1643 status = "disabled"; 1644 }; 1645 1646 trigger@2 { 1647 compatible = "st,stm32-lptimer-trigger"; 1648 reg = <2>; 1649 status = "disabled"; 1650 }; 1651 }; 1652 1653 lptimer4: timer@50023000 { 1654 compatible = "st,stm32-lptimer"; 1655 reg = <0x50023000 0x400>; 1656 interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; 1657 clocks = <&rcc LPTIM4_K>; 1658 clock-names = "mux"; 1659 wakeup-source; 1660 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM4_ID>; 1661 status = "disabled"; 1662 1663 pwm { 1664 compatible = "st,stm32-pwm-lp"; 1665 #pwm-cells = <3>; 1666 status = "disabled"; 1667 }; 1668 }; 1669 1670 lptimer5: timer@50024000 { 1671 compatible = "st,stm32-lptimer"; 1672 reg = <0x50024000 0x400>; 1673 interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; 1674 clocks = <&rcc LPTIM5_K>; 1675 clock-names = "mux"; 1676 wakeup-source; 1677 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM5_ID>; 1678 status = "disabled"; 1679 1680 pwm { 1681 compatible = "st,stm32-pwm-lp"; 1682 #pwm-cells = <3>; 1683 status = "disabled"; 1684 }; 1685 }; 1686 1687 vrefbuf: vrefbuf@50025000 { 1688 compatible = "st,stm32-vrefbuf"; 1689 reg = <0x50025000 0x8>; 1690 regulator-min-microvolt = <1500000>; 1691 regulator-max-microvolt = <2500000>; 1692 clocks = <&rcc VREF>; 1693 access-controllers = <&etzpc STM32MP1_ETZPC_VREFBUF_ID>; 1694 status = "disabled"; 1695 }; 1696 1697 sai4: sai@50027000 { 1698 compatible = "st,stm32h7-sai"; 1699 #address-cells = <1>; 1700 #size-cells = <1>; 1701 ranges = <0 0x50027000 0x400>; 1702 reg = <0x50027000 0x4>, <0x500273f0 0x10>; 1703 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1704 resets = <&rcc SAI4_R>; 1705 access-controllers = <&etzpc STM32MP1_ETZPC_SAI4_ID>; 1706 status = "disabled"; 1707 1708 sai4a: audio-controller@50027004 { 1709 #sound-dai-cells = <0>; 1710 compatible = "st,stm32-sai-sub-a"; 1711 reg = <0x04 0x20>; 1712 clocks = <&rcc SAI4_K>; 1713 clock-names = "sai_ck"; 1714 dmas = <&dmamux1 99 0x400 0x01>; 1715 status = "disabled"; 1716 }; 1717 1718 sai4b: audio-controller@50027024 { 1719 #sound-dai-cells = <0>; 1720 compatible = "st,stm32-sai-sub-b"; 1721 reg = <0x24 0x20>; 1722 clocks = <&rcc SAI4_K>; 1723 clock-names = "sai_ck"; 1724 dmas = <&dmamux1 100 0x400 0x01>; 1725 status = "disabled"; 1726 }; 1727 }; 1728 1729 hash1: hash@54002000 { 1730 compatible = "st,stm32f756-hash"; 1731 reg = <0x54002000 0x400>; 1732 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1733 clocks = <&rcc HASH1>; 1734 resets = <&rcc HASH1_R>; 1735 dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; 1736 dma-names = "in"; 1737 dma-maxburst = <2>; 1738 access-controllers = <&etzpc STM32MP1_ETZPC_HASH1_ID>; 1739 status = "disabled"; 1740 }; 1741 1742 rng1: rng@54003000 { 1743 compatible = "st,stm32-rng"; 1744 reg = <0x54003000 0x400>; 1745 clocks = <&rcc RNG1_K>; 1746 resets = <&rcc RNG1_R>; 1747 access-controllers = <&etzpc STM32MP1_ETZPC_RNG1_ID>; 1748 status = "disabled"; 1749 }; 1750 1751 fmc: memory-controller@58002000 { 1752 #address-cells = <2>; 1753 #size-cells = <1>; 1754 compatible = "st,stm32mp1-fmc2-ebi"; 1755 reg = <0x58002000 0x1000>; 1756 clocks = <&rcc FMC_K>; 1757 resets = <&rcc FMC_R>; 1758 access-controllers = <&etzpc STM32MP1_ETZPC_FMC_ID>; 1759 status = "disabled"; 1760 1761 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 1762 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 1763 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 1764 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 1765 <4 0 0x80000000 0x10000000>; /* NAND */ 1766 1767 nand-controller@4,0 { 1768 #address-cells = <1>; 1769 #size-cells = <0>; 1770 compatible = "st,stm32mp1-fmc2-nfc"; 1771 reg = <4 0x00000000 0x1000>, 1772 <4 0x08010000 0x1000>, 1773 <4 0x08020000 0x1000>, 1774 <4 0x01000000 0x1000>, 1775 <4 0x09010000 0x1000>, 1776 <4 0x09020000 0x1000>; 1777 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1778 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, 1779 <&mdma1 20 0x2 0x12000a08 0x0 0x0>, 1780 <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; 1781 dma-names = "tx", "rx", "ecc"; 1782 status = "disabled"; 1783 }; 1784 }; 1785 1786 qspi: spi@58003000 { 1787 compatible = "st,stm32f469-qspi"; 1788 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; 1789 reg-names = "qspi", "qspi_mm"; 1790 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 1791 dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, 1792 <&mdma1 22 0x2 0x10100008 0x0 0x0>; 1793 dma-names = "tx", "rx"; 1794 clocks = <&rcc QSPI_K>; 1795 resets = <&rcc QSPI_R>; 1796 #address-cells = <1>; 1797 #size-cells = <0>; 1798 access-controllers = <&etzpc STM32MP1_ETZPC_QSPI_ID>; 1799 status = "disabled"; 1800 }; 1801 1802 ethernet0: ethernet@5800a000 { 1803 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; 1804 reg = <0x5800a000 0x2000>; 1805 reg-names = "stmmaceth"; 1806 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1807 interrupt-names = "macirq"; 1808 clock-names = "stmmaceth", 1809 "mac-clk-tx", 1810 "mac-clk-rx", 1811 "eth-ck", 1812 "ptp_ref", 1813 "ethstp"; 1814 clocks = <&rcc ETHMAC>, 1815 <&rcc ETHTX>, 1816 <&rcc ETHRX>, 1817 <&rcc ETHCK_K>, 1818 <&rcc ETHPTP_K>, 1819 <&rcc ETHSTP>; 1820 st,syscon = <&syscfg 0x4>; 1821 snps,mixed-burst; 1822 snps,pbl = <2>; 1823 snps,en-tx-lpi-clockgating; 1824 snps,axi-config = <&stmmac_axi_config_0>; 1825 snps,tso; 1826 access-controllers = <&etzpc STM32MP1_ETZPC_ETH_ID>; 1827 status = "disabled"; 1828 1829 stmmac_axi_config_0: stmmac-axi-config { 1830 snps,wr_osr_lmt = <0x7>; 1831 snps,rd_osr_lmt = <0x7>; 1832 snps,blen = <0 0 0 0 16 8 4>; 1833 }; 1834 }; 1835 1836 usart1: serial@5c000000 { 1837 compatible = "st,stm32h7-uart"; 1838 reg = <0x5c000000 0x400>; 1839 interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; 1840 clocks = <&rcc USART1_K>; 1841 wakeup-source; 1842 access-controllers = <&etzpc STM32MP1_ETZPC_USART1_ID>; 1843 status = "disabled"; 1844 }; 1845 1846 spi6: spi@5c001000 { 1847 #address-cells = <1>; 1848 #size-cells = <0>; 1849 compatible = "st,stm32h7-spi"; 1850 reg = <0x5c001000 0x400>; 1851 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1852 clocks = <&rcc SPI6_K>; 1853 resets = <&rcc SPI6_R>; 1854 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, 1855 <&mdma1 35 0x0 0x40002 0x0 0x0>; 1856 dma-names = "rx", "tx"; 1857 access-controllers = <&etzpc STM32MP1_ETZPC_SPI6_ID>; 1858 status = "disabled"; 1859 }; 1860 1861 i2c4: i2c@5c002000 { 1862 compatible = "st,stm32mp15-i2c"; 1863 reg = <0x5c002000 0x400>; 1864 interrupt-names = "event", "error"; 1865 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1867 clocks = <&rcc I2C4_K>; 1868 resets = <&rcc I2C4_R>; 1869 #address-cells = <1>; 1870 #size-cells = <0>; 1871 st,syscfg-fmp = <&syscfg 0x4 0x8>; 1872 wakeup-source; 1873 i2c-analog-filter; 1874 access-controllers = <&etzpc STM32MP1_ETZPC_I2C4_ID>; 1875 status = "disabled"; 1876 }; 1877 1878 iwdg1: watchdog@5c003000 { 1879 compatible = "st,stm32mp1-iwdg"; 1880 reg = <0x5C003000 0x400>; 1881 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1882 clocks = <&rcc IWDG1>, <&rcc CK_LSI>; 1883 clock-names = "pclk", "lsi"; 1884 access-controllers = <&etzpc STM32MP1_ETZPC_IWDG1_ID>; 1885 status = "disabled"; 1886 }; 1887 1888 i2c6: i2c@5c009000 { 1889 compatible = "st,stm32mp15-i2c"; 1890 reg = <0x5c009000 0x400>; 1891 interrupt-names = "event", "error"; 1892 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1893 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1894 clocks = <&rcc I2C6_K>; 1895 resets = <&rcc I2C6_R>; 1896 #address-cells = <1>; 1897 #size-cells = <0>; 1898 st,syscfg-fmp = <&syscfg 0x4 0x20>; 1899 wakeup-source; 1900 i2c-analog-filter; 1901 access-controllers = <&etzpc STM32MP1_ETZPC_I2C6_ID>; 1902 status = "disabled"; 1903 }; 1904 }; 1905 }; 1906 1907 mlahb: ahb { 1908 compatible = "st,mlahb", "simple-bus"; 1909 #address-cells = <1>; 1910 #size-cells = <1>; 1911 ranges; 1912 dma-ranges = <0x00000000 0x38000000 0x10000>, 1913 <0x10000000 0x10000000 0x60000>, 1914 <0x30000000 0x30000000 0x60000>; 1915 1916 m4_rproc: m4@10000000 { 1917 compatible = "st,stm32mp1-m4"; 1918 reg = <0x10000000 0x40000>, 1919 <0x30000000 0x40000>, 1920 <0x38000000 0x10000>; 1921 resets = <&rcc MCU_R>, <&rcc MCU_HOLD_BOOT_R>; 1922 reset-names = "mcu_rst", "hold_boot"; 1923 st,syscfg-tz = <&rcc 0x000 0x1>; 1924 st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; 1925 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; 1926 st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; 1927 status = "disabled"; 1928 }; 1929 }; 1930}; 1931