1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2017-2024 - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/stm32mp1-clks.h> 8#include <dt-bindings/reset/stm32mp1-resets.h> 9#include <dt-bindings/firewall/stm32mp15-etzpc.h> 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a7"; 21 clock-frequency = <650000000>; 22 device_type = "cpu"; 23 reg = <0>; 24 }; 25 }; 26 27 arm-pmu { 28 compatible = "arm,cortex-a7-pmu"; 29 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 30 interrupt-affinity = <&cpu0>; 31 interrupt-parent = <&intc>; 32 }; 33 34 psci { 35 compatible = "arm,psci-1.0"; 36 method = "smc"; 37 }; 38 39 intc: interrupt-controller@a0021000 { 40 compatible = "arm,cortex-a7-gic"; 41 #interrupt-cells = <3>; 42 interrupt-controller; 43 reg = <0xa0021000 0x1000>, 44 <0xa0022000 0x2000>; 45 }; 46 47 timer { 48 compatible = "arm,armv7-timer"; 49 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 50 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 51 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 52 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 53 interrupt-parent = <&intc>; 54 }; 55 56 clocks { 57 clk_hse: clk-hse { 58 #clock-cells = <0>; 59 compatible = "fixed-clock"; 60 clock-frequency = <24000000>; 61 }; 62 63 clk_hsi: clk-hsi { 64 #clock-cells = <0>; 65 compatible = "fixed-clock"; 66 clock-frequency = <64000000>; 67 }; 68 69 clk_lse: clk-lse { 70 #clock-cells = <0>; 71 compatible = "fixed-clock"; 72 clock-frequency = <32768>; 73 }; 74 75 clk_lsi: clk-lsi { 76 #clock-cells = <0>; 77 compatible = "fixed-clock"; 78 clock-frequency = <32000>; 79 }; 80 81 clk_csi: clk-csi { 82 #clock-cells = <0>; 83 compatible = "fixed-clock"; 84 clock-frequency = <4000000>; 85 }; 86 }; 87 88 thermal-zones { 89 cpu_thermal: cpu-thermal { 90 polling-delay-passive = <0>; 91 polling-delay = <0>; 92 thermal-sensors = <&dts>; 93 94 trips { 95 cpu_alert1: cpu-alert1 { 96 temperature = <85000>; 97 hysteresis = <0>; 98 type = "passive"; 99 }; 100 101 cpu-crit { 102 temperature = <120000>; 103 hysteresis = <0>; 104 type = "critical"; 105 }; 106 }; 107 108 cooling-maps { 109 }; 110 }; 111 }; 112 113 booster: regulator-booster { 114 compatible = "st,stm32mp1-booster"; 115 st,syscfg = <&syscfg>; 116 status = "disabled"; 117 }; 118 119 soc { 120 compatible = "simple-bus"; 121 #address-cells = <1>; 122 #size-cells = <1>; 123 interrupt-parent = <&intc>; 124 ranges; 125 126 ipcc: mailbox@4c001000 { 127 compatible = "st,stm32mp1-ipcc"; 128 #mbox-cells = <1>; 129 reg = <0x4c001000 0x400>; 130 st,proc-id = <0>; 131 interrupts-extended = 132 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 133 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 134 <&exti 61 1>; 135 interrupt-names = "rx", "tx", "wakeup"; 136 clocks = <&rcc IPCC>; 137 wakeup-source; 138 status = "disabled"; 139 }; 140 141 rcc: rcc@50000000 { 142 compatible = "st,stm32mp1-rcc", "syscon"; 143 reg = <0x50000000 0x1000>; 144 #clock-cells = <1>; 145 #reset-cells = <1>; 146 }; 147 148 pwr_regulators: pwr@50001000 { 149 compatible = "st,stm32mp1,pwr-reg"; 150 reg = <0x50001000 0x10>; 151 152 reg11: reg11 { 153 regulator-name = "reg11"; 154 regulator-min-microvolt = <1100000>; 155 regulator-max-microvolt = <1100000>; 156 }; 157 158 reg18: reg18 { 159 regulator-name = "reg18"; 160 regulator-min-microvolt = <1800000>; 161 regulator-max-microvolt = <1800000>; 162 }; 163 164 usb33: usb33 { 165 regulator-name = "usb33"; 166 regulator-min-microvolt = <3300000>; 167 regulator-max-microvolt = <3300000>; 168 }; 169 }; 170 171 pwr_mcu: pwr_mcu@50001014 { 172 compatible = "st,stm32mp151-pwr-mcu", "syscon"; 173 reg = <0x50001014 0x4>; 174 }; 175 176 exti: interrupt-controller@5000d000 { 177 compatible = "st,stm32mp1-exti", "syscon"; 178 interrupt-controller; 179 #interrupt-cells = <2>; 180 reg = <0x5000d000 0x400>; 181 }; 182 183 syscfg: syscon@50020000 { 184 compatible = "st,stm32mp157-syscfg", "syscon"; 185 reg = <0x50020000 0x400>; 186 clocks = <&rcc SYSCFG>; 187 }; 188 189 dts: thermal@50028000 { 190 compatible = "st,stm32-thermal"; 191 reg = <0x50028000 0x100>; 192 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 193 clocks = <&rcc TMPSENS>; 194 clock-names = "pclk"; 195 #thermal-sensor-cells = <0>; 196 status = "disabled"; 197 }; 198 199 mdma1: dma-controller@58000000 { 200 compatible = "st,stm32h7-mdma"; 201 reg = <0x58000000 0x1000>; 202 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 203 clocks = <&rcc MDMA>; 204 resets = <&rcc MDMA_R>; 205 #dma-cells = <5>; 206 dma-channels = <32>; 207 dma-requests = <48>; 208 }; 209 210 sdmmc1: mmc@58005000 { 211 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 212 arm,primecell-periphid = <0x00253180>; 213 reg = <0x58005000 0x1000>; 214 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 215 interrupt-names = "cmd_irq"; 216 clocks = <&rcc SDMMC1_K>; 217 clock-names = "apb_pclk"; 218 resets = <&rcc SDMMC1_R>; 219 cap-sd-highspeed; 220 cap-mmc-highspeed; 221 max-frequency = <120000000>; 222 status = "disabled"; 223 }; 224 225 sdmmc2: mmc@58007000 { 226 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 227 arm,primecell-periphid = <0x00253180>; 228 reg = <0x58007000 0x1000>; 229 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 230 interrupt-names = "cmd_irq"; 231 clocks = <&rcc SDMMC2_K>; 232 clock-names = "apb_pclk"; 233 resets = <&rcc SDMMC2_R>; 234 cap-sd-highspeed; 235 cap-mmc-highspeed; 236 max-frequency = <120000000>; 237 status = "disabled"; 238 }; 239 240 crc1: crc@58009000 { 241 compatible = "st,stm32f7-crc"; 242 reg = <0x58009000 0x400>; 243 clocks = <&rcc CRC1>; 244 status = "disabled"; 245 }; 246 247 usbh_ohci: usb@5800c000 { 248 compatible = "generic-ohci"; 249 reg = <0x5800c000 0x1000>; 250 clocks = <&usbphyc>, <&rcc USBH>; 251 resets = <&rcc USBH_R>; 252 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 253 status = "disabled"; 254 }; 255 256 usbh_ehci: usb@5800d000 { 257 compatible = "generic-ehci"; 258 reg = <0x5800d000 0x1000>; 259 clocks = <&usbphyc>, <&rcc USBH>; 260 resets = <&rcc USBH_R>; 261 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 262 companion = <&usbh_ohci>; 263 status = "disabled"; 264 }; 265 266 ltdc: display-controller@5a001000 { 267 compatible = "st,stm32-ltdc"; 268 reg = <0x5a001000 0x400>; 269 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 271 clocks = <&rcc LTDC_PX>; 272 clock-names = "lcd"; 273 resets = <&rcc LTDC_R>; 274 status = "disabled"; 275 276 port { 277 #address-cells = <1>; 278 #size-cells = <0>; 279 }; 280 }; 281 282 iwdg2: watchdog@5a002000 { 283 compatible = "st,stm32mp1-iwdg"; 284 reg = <0x5a002000 0x400>; 285 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&rcc IWDG2>, <&rcc CK_LSI>; 287 clock-names = "pclk", "lsi"; 288 status = "disabled"; 289 }; 290 291 usbphyc: usbphyc@5a006000 { 292 #address-cells = <1>; 293 #size-cells = <0>; 294 #clock-cells = <0>; 295 compatible = "st,stm32mp1-usbphyc"; 296 reg = <0x5a006000 0x1000>; 297 clocks = <&rcc USBPHY_K>; 298 resets = <&rcc USBPHY_R>; 299 vdda1v1-supply = <®11>; 300 vdda1v8-supply = <®18>; 301 status = "disabled"; 302 303 usbphyc_port0: usb-phy@0 { 304 #phy-cells = <0>; 305 reg = <0>; 306 }; 307 308 usbphyc_port1: usb-phy@1 { 309 #phy-cells = <1>; 310 reg = <1>; 311 }; 312 }; 313 314 rtc: rtc@5c004000 { 315 compatible = "st,stm32mp1-rtc"; 316 reg = <0x5c004000 0x400>; 317 clocks = <&rcc RTCAPB>, <&rcc RTC>; 318 clock-names = "pclk", "rtc_ck"; 319 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; 320 status = "disabled"; 321 }; 322 323 bsec: efuse@5c005000 { 324 compatible = "st,stm32mp15-bsec"; 325 reg = <0x5c005000 0x400>; 326 #address-cells = <1>; 327 #size-cells = <1>; 328 329 cfg0_otp: cfg0_otp@0 { 330 reg = <0x0 0x1>; 331 }; 332 part_number_otp: part_number_otp@4 { 333 reg = <0x4 0x1>; 334 }; 335 monotonic_otp: monotonic_otp@10 { 336 reg = <0x10 0x4>; 337 }; 338 nand_otp: nand_otp@24 { 339 reg = <0x24 0x4>; 340 }; 341 uid_otp: uid_otp@34 { 342 reg = <0x34 0xc>; 343 }; 344 package_otp: package_otp@40 { 345 reg = <0x40 0x4>; 346 }; 347 hw2_otp: hw2_otp@48 { 348 reg = <0x48 0x4>; 349 }; 350 ts_cal1: calib@5c { 351 reg = <0x5c 0x2>; 352 }; 353 ts_cal2: calib@5e { 354 reg = <0x5e 0x2>; 355 }; 356 pkh_otp: pkh_otp@60 { 357 reg = <0x60 0x20>; 358 }; 359 ethernet_mac_address: mac@e4 { 360 reg = <0xe4 0x8>; 361 st,non-secure-otp; 362 }; 363 }; 364 365 tamp: tamp@5c00a000 { 366 compatible = "st,stm32-tamp", "syscon", "simple-mfd"; 367 reg = <0x5c00a000 0x400>; 368 clocks = <&rcc RTCAPB>; 369 st,backup-zones = <10 5 17>; 370 }; 371 372 /* 373 * Break node order to solve dependency probe issue between 374 * pinctrl and exti. 375 */ 376 pinctrl: pinctrl@50002000 { 377 #address-cells = <1>; 378 #size-cells = <1>; 379 compatible = "st,stm32mp157-pinctrl"; 380 ranges = <0 0x50002000 0xa400>; 381 interrupt-parent = <&exti>; 382 st,syscfg = <&exti 0x60 0xff>; 383 pins-are-numbered; 384 385 gpioa: gpio@50002000 { 386 gpio-controller; 387 #gpio-cells = <2>; 388 interrupt-controller; 389 #interrupt-cells = <2>; 390 reg = <0x0 0x400>; 391 clocks = <&rcc GPIOA>; 392 st,bank-name = "GPIOA"; 393 status = "disabled"; 394 }; 395 396 gpiob: gpio@50003000 { 397 gpio-controller; 398 #gpio-cells = <2>; 399 interrupt-controller; 400 #interrupt-cells = <2>; 401 reg = <0x1000 0x400>; 402 clocks = <&rcc GPIOB>; 403 st,bank-name = "GPIOB"; 404 status = "disabled"; 405 }; 406 407 gpioc: gpio@50004000 { 408 gpio-controller; 409 #gpio-cells = <2>; 410 interrupt-controller; 411 #interrupt-cells = <2>; 412 reg = <0x2000 0x400>; 413 clocks = <&rcc GPIOC>; 414 st,bank-name = "GPIOC"; 415 status = "disabled"; 416 }; 417 418 gpiod: gpio@50005000 { 419 gpio-controller; 420 #gpio-cells = <2>; 421 interrupt-controller; 422 #interrupt-cells = <2>; 423 reg = <0x3000 0x400>; 424 clocks = <&rcc GPIOD>; 425 st,bank-name = "GPIOD"; 426 status = "disabled"; 427 }; 428 429 gpioe: gpio@50006000 { 430 gpio-controller; 431 #gpio-cells = <2>; 432 interrupt-controller; 433 #interrupt-cells = <2>; 434 reg = <0x4000 0x400>; 435 clocks = <&rcc GPIOE>; 436 st,bank-name = "GPIOE"; 437 status = "disabled"; 438 }; 439 440 gpiof: gpio@50007000 { 441 gpio-controller; 442 #gpio-cells = <2>; 443 interrupt-controller; 444 #interrupt-cells = <2>; 445 reg = <0x5000 0x400>; 446 clocks = <&rcc GPIOF>; 447 st,bank-name = "GPIOF"; 448 status = "disabled"; 449 }; 450 451 gpiog: gpio@50008000 { 452 gpio-controller; 453 #gpio-cells = <2>; 454 interrupt-controller; 455 #interrupt-cells = <2>; 456 reg = <0x6000 0x400>; 457 clocks = <&rcc GPIOG>; 458 st,bank-name = "GPIOG"; 459 status = "disabled"; 460 }; 461 462 gpioh: gpio@50009000 { 463 gpio-controller; 464 #gpio-cells = <2>; 465 interrupt-controller; 466 #interrupt-cells = <2>; 467 reg = <0x7000 0x400>; 468 clocks = <&rcc GPIOH>; 469 st,bank-name = "GPIOH"; 470 status = "disabled"; 471 }; 472 473 gpioi: gpio@5000a000 { 474 gpio-controller; 475 #gpio-cells = <2>; 476 interrupt-controller; 477 #interrupt-cells = <2>; 478 reg = <0x8000 0x400>; 479 clocks = <&rcc GPIOI>; 480 st,bank-name = "GPIOI"; 481 status = "disabled"; 482 }; 483 484 gpioj: gpio@5000b000 { 485 gpio-controller; 486 #gpio-cells = <2>; 487 interrupt-controller; 488 #interrupt-cells = <2>; 489 reg = <0x9000 0x400>; 490 clocks = <&rcc GPIOJ>; 491 st,bank-name = "GPIOJ"; 492 status = "disabled"; 493 }; 494 495 gpiok: gpio@5000c000 { 496 gpio-controller; 497 #gpio-cells = <2>; 498 interrupt-controller; 499 #interrupt-cells = <2>; 500 reg = <0xa000 0x400>; 501 clocks = <&rcc GPIOK>; 502 st,bank-name = "GPIOK"; 503 status = "disabled"; 504 }; 505 }; 506 507 pinctrl_z: pinctrl@54004000 { 508 #address-cells = <1>; 509 #size-cells = <1>; 510 compatible = "st,stm32mp157-z-pinctrl"; 511 ranges = <0 0x54004000 0x400>; 512 pins-are-numbered; 513 interrupt-parent = <&exti>; 514 st,syscfg = <&exti 0x60 0xff>; 515 516 gpioz: gpio@54004000 { 517 gpio-controller; 518 #gpio-cells = <2>; 519 interrupt-controller; 520 #interrupt-cells = <2>; 521 reg = <0 0x400>; 522 clocks = <&rcc GPIOZ>; 523 st,bank-name = "GPIOZ"; 524 st,bank-ioport = <11>; 525 status = "disabled"; 526 }; 527 }; 528 529 tzc400: tzc@5c006000 { 530 compatible = "st,stm32mp1-tzc"; 531 reg = <0x5c006000 0x1000>; 532 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 533 clocks = <&rcc TZC1>, <&rcc TZC2>; 534 st,mem-map = <0xc0000000 0x40000000>; 535 }; 536 537 etzpc: etzpc@5c007000 { 538 compatible = "st,stm32-etzpc", "simple-bus"; 539 reg = <0x5C007000 0x400>; 540 clocks = <&rcc TZPC>; 541 #address-cells = <1>; 542 #size-cells = <1>; 543 #access-controller-cells = <1>; 544 545 timers2: timer@40000000 { 546 #address-cells = <1>; 547 #size-cells = <0>; 548 compatible = "st,stm32-timers"; 549 reg = <0x40000000 0x400>; 550 clocks = <&rcc TIM2_K>; 551 clock-names = "int"; 552 dmas = <&dmamux1 18 0x400 0x1>, 553 <&dmamux1 19 0x400 0x1>, 554 <&dmamux1 20 0x400 0x1>, 555 <&dmamux1 21 0x400 0x1>, 556 <&dmamux1 22 0x400 0x1>; 557 dma-names = "ch1", "ch2", "ch3", "ch4", "up"; 558 access-controllers = <&etzpc STM32MP1_ETZPC_TIM2_ID>; 559 status = "disabled"; 560 561 pwm { 562 compatible = "st,stm32-pwm"; 563 #pwm-cells = <3>; 564 status = "disabled"; 565 }; 566 567 timer@1 { 568 compatible = "st,stm32h7-timer-trigger"; 569 reg = <1>; 570 status = "disabled"; 571 }; 572 573 counter { 574 compatible = "st,stm32-timer-counter"; 575 status = "disabled"; 576 }; 577 }; 578 579 timers3: timer@40001000 { 580 #address-cells = <1>; 581 #size-cells = <0>; 582 compatible = "st,stm32-timers"; 583 reg = <0x40001000 0x400>; 584 clocks = <&rcc TIM3_K>; 585 clock-names = "int"; 586 dmas = <&dmamux1 23 0x400 0x1>, 587 <&dmamux1 24 0x400 0x1>, 588 <&dmamux1 25 0x400 0x1>, 589 <&dmamux1 26 0x400 0x1>, 590 <&dmamux1 27 0x400 0x1>, 591 <&dmamux1 28 0x400 0x1>; 592 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 593 access-controllers = <&etzpc STM32MP1_ETZPC_TIM3_ID>; 594 status = "disabled"; 595 596 pwm { 597 compatible = "st,stm32-pwm"; 598 #pwm-cells = <3>; 599 status = "disabled"; 600 }; 601 602 timer@2 { 603 compatible = "st,stm32h7-timer-trigger"; 604 reg = <2>; 605 status = "disabled"; 606 }; 607 608 counter { 609 compatible = "st,stm32-timer-counter"; 610 status = "disabled"; 611 }; 612 }; 613 614 timers4: timer@40002000 { 615 #address-cells = <1>; 616 #size-cells = <0>; 617 compatible = "st,stm32-timers"; 618 reg = <0x40002000 0x400>; 619 clocks = <&rcc TIM4_K>; 620 clock-names = "int"; 621 dmas = <&dmamux1 29 0x400 0x1>, 622 <&dmamux1 30 0x400 0x1>, 623 <&dmamux1 31 0x400 0x1>, 624 <&dmamux1 32 0x400 0x1>; 625 dma-names = "ch1", "ch2", "ch3", "ch4"; 626 access-controllers = <&etzpc STM32MP1_ETZPC_TIM4_ID>; 627 status = "disabled"; 628 629 pwm { 630 compatible = "st,stm32-pwm"; 631 #pwm-cells = <3>; 632 status = "disabled"; 633 }; 634 635 timer@3 { 636 compatible = "st,stm32h7-timer-trigger"; 637 reg = <3>; 638 status = "disabled"; 639 }; 640 641 counter { 642 compatible = "st,stm32-timer-counter"; 643 status = "disabled"; 644 }; 645 }; 646 647 timers5: timer@40003000 { 648 #address-cells = <1>; 649 #size-cells = <0>; 650 compatible = "st,stm32-timers"; 651 reg = <0x40003000 0x400>; 652 clocks = <&rcc TIM5_K>; 653 clock-names = "int"; 654 dmas = <&dmamux1 55 0x400 0x1>, 655 <&dmamux1 56 0x400 0x1>, 656 <&dmamux1 57 0x400 0x1>, 657 <&dmamux1 58 0x400 0x1>, 658 <&dmamux1 59 0x400 0x1>, 659 <&dmamux1 60 0x400 0x1>; 660 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 661 access-controllers = <&etzpc STM32MP1_ETZPC_TIM5_ID>; 662 status = "disabled"; 663 664 pwm { 665 compatible = "st,stm32-pwm"; 666 #pwm-cells = <3>; 667 status = "disabled"; 668 }; 669 670 timer@4 { 671 compatible = "st,stm32h7-timer-trigger"; 672 reg = <4>; 673 status = "disabled"; 674 }; 675 676 counter { 677 compatible = "st,stm32-timer-counter"; 678 status = "disabled"; 679 }; 680 }; 681 682 timers6: timer@40004000 { 683 #address-cells = <1>; 684 #size-cells = <0>; 685 compatible = "st,stm32-timers"; 686 reg = <0x40004000 0x400>; 687 clocks = <&rcc TIM6_K>; 688 clock-names = "int"; 689 dmas = <&dmamux1 69 0x400 0x1>; 690 dma-names = "up"; 691 access-controllers = <&etzpc STM32MP1_ETZPC_TIM6_ID>; 692 status = "disabled"; 693 694 timer@5 { 695 compatible = "st,stm32h7-timer-trigger"; 696 reg = <5>; 697 status = "disabled"; 698 }; 699 }; 700 701 timers7: timer@40005000 { 702 #address-cells = <1>; 703 #size-cells = <0>; 704 compatible = "st,stm32-timers"; 705 reg = <0x40005000 0x400>; 706 clocks = <&rcc TIM7_K>; 707 clock-names = "int"; 708 dmas = <&dmamux1 70 0x400 0x1>; 709 dma-names = "up"; 710 access-controllers = <&etzpc STM32MP1_ETZPC_TIM7_ID>; 711 status = "disabled"; 712 713 timer@6 { 714 compatible = "st,stm32h7-timer-trigger"; 715 reg = <6>; 716 status = "disabled"; 717 }; 718 }; 719 720 timers12: timer@40006000 { 721 #address-cells = <1>; 722 #size-cells = <0>; 723 compatible = "st,stm32-timers"; 724 reg = <0x40006000 0x400>; 725 clocks = <&rcc TIM12_K>; 726 clock-names = "int"; 727 access-controllers = <&etzpc STM32MP1_ETZPC_TIM12_ID>; 728 status = "disabled"; 729 730 pwm { 731 compatible = "st,stm32-pwm"; 732 #pwm-cells = <3>; 733 status = "disabled"; 734 }; 735 736 timer@11 { 737 compatible = "st,stm32h7-timer-trigger"; 738 reg = <11>; 739 status = "disabled"; 740 }; 741 }; 742 743 timers13: timer@40007000 { 744 #address-cells = <1>; 745 #size-cells = <0>; 746 compatible = "st,stm32-timers"; 747 reg = <0x40007000 0x400>; 748 clocks = <&rcc TIM13_K>; 749 clock-names = "int"; 750 access-controllers = <&etzpc STM32MP1_ETZPC_TIM13_ID>; 751 status = "disabled"; 752 753 pwm { 754 compatible = "st,stm32-pwm"; 755 #pwm-cells = <3>; 756 status = "disabled"; 757 }; 758 759 timer@12 { 760 compatible = "st,stm32h7-timer-trigger"; 761 reg = <12>; 762 status = "disabled"; 763 }; 764 }; 765 766 timers14: timer@40008000 { 767 #address-cells = <1>; 768 #size-cells = <0>; 769 compatible = "st,stm32-timers"; 770 reg = <0x40008000 0x400>; 771 clocks = <&rcc TIM14_K>; 772 clock-names = "int"; 773 access-controllers = <&etzpc STM32MP1_ETZPC_TIM14_ID>; 774 status = "disabled"; 775 776 pwm { 777 compatible = "st,stm32-pwm"; 778 #pwm-cells = <3>; 779 status = "disabled"; 780 }; 781 782 timer@13 { 783 compatible = "st,stm32h7-timer-trigger"; 784 reg = <13>; 785 status = "disabled"; 786 }; 787 }; 788 789 lptimer1: timer@40009000 { 790 #address-cells = <1>; 791 #size-cells = <0>; 792 compatible = "st,stm32-lptimer"; 793 reg = <0x40009000 0x400>; 794 interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; 795 clocks = <&rcc LPTIM1_K>; 796 clock-names = "mux"; 797 wakeup-source; 798 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM1_ID>; 799 status = "disabled"; 800 801 pwm { 802 compatible = "st,stm32-pwm-lp"; 803 #pwm-cells = <3>; 804 status = "disabled"; 805 }; 806 807 trigger@0 { 808 compatible = "st,stm32-lptimer-trigger"; 809 reg = <0>; 810 status = "disabled"; 811 }; 812 813 counter { 814 compatible = "st,stm32-lptimer-counter"; 815 status = "disabled"; 816 }; 817 }; 818 819 spi2: spi@4000b000 { 820 #address-cells = <1>; 821 #size-cells = <0>; 822 compatible = "st,stm32h7-spi"; 823 reg = <0x4000b000 0x400>; 824 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 825 clocks = <&rcc SPI2_K>; 826 resets = <&rcc SPI2_R>; 827 dmas = <&dmamux1 39 0x400 0x05>, 828 <&dmamux1 40 0x400 0x05>; 829 dma-names = "rx", "tx"; 830 access-controllers = <&etzpc STM32MP1_ETZPC_SPI2_ID>; 831 status = "disabled"; 832 }; 833 834 i2s2: audio-controller@4000b000 { 835 compatible = "st,stm32h7-i2s"; 836 #sound-dai-cells = <0>; 837 reg = <0x4000b000 0x400>; 838 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 839 dmas = <&dmamux1 39 0x400 0x01>, 840 <&dmamux1 40 0x400 0x01>; 841 dma-names = "rx", "tx"; 842 access-controllers = <&etzpc STM32MP1_ETZPC_SPI2_ID>; 843 status = "disabled"; 844 }; 845 846 spi3: spi@4000c000 { 847 #address-cells = <1>; 848 #size-cells = <0>; 849 compatible = "st,stm32h7-spi"; 850 reg = <0x4000c000 0x400>; 851 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 852 clocks = <&rcc SPI3_K>; 853 resets = <&rcc SPI3_R>; 854 dmas = <&dmamux1 61 0x400 0x05>, 855 <&dmamux1 62 0x400 0x05>; 856 dma-names = "rx", "tx"; 857 access-controllers = <&etzpc STM32MP1_ETZPC_SPI3_ID>; 858 status = "disabled"; 859 }; 860 861 i2s3: audio-controller@4000c000 { 862 compatible = "st,stm32h7-i2s"; 863 #sound-dai-cells = <0>; 864 reg = <0x4000c000 0x400>; 865 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 866 dmas = <&dmamux1 61 0x400 0x01>, 867 <&dmamux1 62 0x400 0x01>; 868 dma-names = "rx", "tx"; 869 access-controllers = <&etzpc STM32MP1_ETZPC_SPI3_ID>; 870 status = "disabled"; 871 }; 872 873 spdifrx: audio-controller@4000d000 { 874 compatible = "st,stm32h7-spdifrx"; 875 #sound-dai-cells = <0>; 876 reg = <0x4000d000 0x400>; 877 clocks = <&rcc SPDIF_K>; 878 clock-names = "kclk"; 879 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 880 dmas = <&dmamux1 93 0x400 0x01>, 881 <&dmamux1 94 0x400 0x01>; 882 dma-names = "rx", "rx-ctrl"; 883 access-controllers = <&etzpc STM32MP1_ETZPC_SPDIFRX_ID>; 884 status = "disabled"; 885 }; 886 887 usart2: serial@4000e000 { 888 compatible = "st,stm32h7-uart"; 889 reg = <0x4000e000 0x400>; 890 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; 891 clocks = <&rcc USART2_K>; 892 wakeup-source; 893 dmas = <&dmamux1 43 0x400 0x15>, 894 <&dmamux1 44 0x400 0x11>; 895 dma-names = "rx", "tx"; 896 access-controllers = <&etzpc STM32MP1_ETZPC_USART2_ID>; 897 status = "disabled"; 898 }; 899 900 usart3: serial@4000f000 { 901 compatible = "st,stm32h7-uart"; 902 reg = <0x4000f000 0x400>; 903 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; 904 clocks = <&rcc USART3_K>; 905 wakeup-source; 906 dmas = <&dmamux1 45 0x400 0x15>, 907 <&dmamux1 46 0x400 0x11>; 908 dma-names = "rx", "tx"; 909 access-controllers = <&etzpc STM32MP1_ETZPC_USART3_ID>; 910 status = "disabled"; 911 }; 912 913 uart4: serial@40010000 { 914 compatible = "st,stm32h7-uart"; 915 reg = <0x40010000 0x400>; 916 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; 917 clocks = <&rcc UART4_K>; 918 wakeup-source; 919 dmas = <&dmamux1 63 0x400 0x15>, 920 <&dmamux1 64 0x400 0x11>; 921 dma-names = "rx", "tx"; 922 access-controllers = <&etzpc STM32MP1_ETZPC_UART4_ID>; 923 status = "disabled"; 924 }; 925 926 uart5: serial@40011000 { 927 compatible = "st,stm32h7-uart"; 928 reg = <0x40011000 0x400>; 929 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; 930 clocks = <&rcc UART5_K>; 931 wakeup-source; 932 dmas = <&dmamux1 65 0x400 0x15>, 933 <&dmamux1 66 0x400 0x11>; 934 dma-names = "rx", "tx"; 935 access-controllers = <&etzpc STM32MP1_ETZPC_UART5_ID>; 936 status = "disabled"; 937 }; 938 939 i2c1: i2c@40012000 { 940 compatible = "st,stm32mp15-i2c"; 941 reg = <0x40012000 0x400>; 942 interrupt-names = "event", "error"; 943 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 945 clocks = <&rcc I2C1_K>; 946 resets = <&rcc I2C1_R>; 947 #address-cells = <1>; 948 #size-cells = <0>; 949 st,syscfg-fmp = <&syscfg 0x4 0x1>; 950 wakeup-source; 951 i2c-analog-filter; 952 access-controllers = <&etzpc STM32MP1_ETZPC_I2C1_ID>; 953 status = "disabled"; 954 }; 955 956 i2c2: i2c@40013000 { 957 compatible = "st,stm32mp15-i2c"; 958 reg = <0x40013000 0x400>; 959 interrupt-names = "event", "error"; 960 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 961 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 962 clocks = <&rcc I2C2_K>; 963 resets = <&rcc I2C2_R>; 964 #address-cells = <1>; 965 #size-cells = <0>; 966 st,syscfg-fmp = <&syscfg 0x4 0x2>; 967 wakeup-source; 968 i2c-analog-filter; 969 access-controllers = <&etzpc STM32MP1_ETZPC_I2C2_ID>; 970 status = "disabled"; 971 }; 972 973 i2c3: i2c@40014000 { 974 compatible = "st,stm32mp15-i2c"; 975 reg = <0x40014000 0x400>; 976 interrupt-names = "event", "error"; 977 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 978 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 979 clocks = <&rcc I2C3_K>; 980 resets = <&rcc I2C3_R>; 981 #address-cells = <1>; 982 #size-cells = <0>; 983 st,syscfg-fmp = <&syscfg 0x4 0x4>; 984 wakeup-source; 985 i2c-analog-filter; 986 access-controllers = <&etzpc STM32MP1_ETZPC_I2C3_ID>; 987 status = "disabled"; 988 }; 989 990 i2c5: i2c@40015000 { 991 compatible = "st,stm32mp15-i2c"; 992 reg = <0x40015000 0x400>; 993 interrupt-names = "event", "error"; 994 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 996 clocks = <&rcc I2C5_K>; 997 resets = <&rcc I2C5_R>; 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 st,syscfg-fmp = <&syscfg 0x4 0x10>; 1001 wakeup-source; 1002 i2c-analog-filter; 1003 access-controllers = <&etzpc STM32MP1_ETZPC_I2C5_ID>; 1004 status = "disabled"; 1005 }; 1006 1007 cec: cec@40016000 { 1008 compatible = "st,stm32-cec"; 1009 reg = <0x40016000 0x400>; 1010 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1011 clocks = <&rcc CEC_K>, <&rcc CEC>; 1012 clock-names = "cec", "hdmi-cec"; 1013 access-controllers = <&etzpc STM32MP1_ETZPC_CEC_ID>; 1014 status = "disabled"; 1015 }; 1016 1017 dac: dac@40017000 { 1018 compatible = "st,stm32h7-dac-core"; 1019 reg = <0x40017000 0x400>; 1020 clocks = <&rcc DAC12>; 1021 clock-names = "pclk"; 1022 #address-cells = <1>; 1023 #size-cells = <0>; 1024 access-controllers = <&etzpc STM32MP1_ETZPC_DAC_ID>; 1025 status = "disabled"; 1026 1027 dac1: dac@1 { 1028 compatible = "st,stm32-dac"; 1029 #io-channel-cells = <1>; 1030 reg = <1>; 1031 status = "disabled"; 1032 }; 1033 1034 dac2: dac@2 { 1035 compatible = "st,stm32-dac"; 1036 #io-channel-cells = <1>; 1037 reg = <2>; 1038 status = "disabled"; 1039 }; 1040 }; 1041 1042 uart7: serial@40018000 { 1043 compatible = "st,stm32h7-uart"; 1044 reg = <0x40018000 0x400>; 1045 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; 1046 clocks = <&rcc UART7_K>; 1047 wakeup-source; 1048 dmas = <&dmamux1 79 0x400 0x15>, 1049 <&dmamux1 80 0x400 0x11>; 1050 dma-names = "rx", "tx"; 1051 access-controllers = <&etzpc STM32MP1_ETZPC_UART7_ID>; 1052 status = "disabled"; 1053 }; 1054 1055 uart8: serial@40019000 { 1056 compatible = "st,stm32h7-uart"; 1057 reg = <0x40019000 0x400>; 1058 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; 1059 clocks = <&rcc UART8_K>; 1060 wakeup-source; 1061 dmas = <&dmamux1 81 0x400 0x15>, 1062 <&dmamux1 82 0x400 0x11>; 1063 dma-names = "rx", "tx"; 1064 access-controllers = <&etzpc STM32MP1_ETZPC_UART8_ID>; 1065 status = "disabled"; 1066 }; 1067 1068 timers1: timer@44000000 { 1069 #address-cells = <1>; 1070 #size-cells = <0>; 1071 compatible = "st,stm32-timers"; 1072 reg = <0x44000000 0x400>; 1073 clocks = <&rcc TIM1_K>; 1074 clock-names = "int"; 1075 dmas = <&dmamux1 11 0x400 0x1>, 1076 <&dmamux1 12 0x400 0x1>, 1077 <&dmamux1 13 0x400 0x1>, 1078 <&dmamux1 14 0x400 0x1>, 1079 <&dmamux1 15 0x400 0x1>, 1080 <&dmamux1 16 0x400 0x1>, 1081 <&dmamux1 17 0x400 0x1>; 1082 dma-names = "ch1", "ch2", "ch3", "ch4", 1083 "up", "trig", "com"; 1084 access-controllers = <&etzpc STM32MP1_ETZPC_TIM1_ID>; 1085 status = "disabled"; 1086 1087 pwm { 1088 compatible = "st,stm32-pwm"; 1089 #pwm-cells = <3>; 1090 status = "disabled"; 1091 }; 1092 1093 timer@0 { 1094 compatible = "st,stm32h7-timer-trigger"; 1095 reg = <0>; 1096 status = "disabled"; 1097 }; 1098 1099 counter { 1100 compatible = "st,stm32-timer-counter"; 1101 status = "disabled"; 1102 }; 1103 }; 1104 1105 timers8: timer@44001000 { 1106 #address-cells = <1>; 1107 #size-cells = <0>; 1108 compatible = "st,stm32-timers"; 1109 reg = <0x44001000 0x400>; 1110 clocks = <&rcc TIM8_K>; 1111 clock-names = "int"; 1112 dmas = <&dmamux1 47 0x400 0x1>, 1113 <&dmamux1 48 0x400 0x1>, 1114 <&dmamux1 49 0x400 0x1>, 1115 <&dmamux1 50 0x400 0x1>, 1116 <&dmamux1 51 0x400 0x1>, 1117 <&dmamux1 52 0x400 0x1>, 1118 <&dmamux1 53 0x400 0x1>; 1119 dma-names = "ch1", "ch2", "ch3", "ch4", 1120 "up", "trig", "com"; 1121 access-controllers = <&etzpc STM32MP1_ETZPC_TIM8_ID>; 1122 status = "disabled"; 1123 1124 pwm { 1125 compatible = "st,stm32-pwm"; 1126 #pwm-cells = <3>; 1127 status = "disabled"; 1128 }; 1129 1130 timer@7 { 1131 compatible = "st,stm32h7-timer-trigger"; 1132 reg = <7>; 1133 status = "disabled"; 1134 }; 1135 1136 counter { 1137 compatible = "st,stm32-timer-counter"; 1138 status = "disabled"; 1139 }; 1140 }; 1141 1142 usart6: serial@44003000 { 1143 compatible = "st,stm32h7-uart"; 1144 reg = <0x44003000 0x400>; 1145 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; 1146 clocks = <&rcc USART6_K>; 1147 wakeup-source; 1148 dmas = <&dmamux1 71 0x400 0x15>, 1149 <&dmamux1 72 0x400 0x11>; 1150 dma-names = "rx", "tx"; 1151 access-controllers = <&etzpc STM32MP1_ETZPC_USART6_ID>; 1152 status = "disabled"; 1153 }; 1154 1155 spi1: spi@44004000 { 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 compatible = "st,stm32h7-spi"; 1159 reg = <0x44004000 0x400>; 1160 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1161 clocks = <&rcc SPI1_K>; 1162 resets = <&rcc SPI1_R>; 1163 dmas = <&dmamux1 37 0x400 0x05>, 1164 <&dmamux1 38 0x400 0x05>; 1165 dma-names = "rx", "tx"; 1166 access-controllers = <&etzpc STM32MP1_ETZPC_SPI1_ID>; 1167 status = "disabled"; 1168 }; 1169 1170 i2s1: audio-controller@44004000 { 1171 compatible = "st,stm32h7-i2s"; 1172 #sound-dai-cells = <0>; 1173 reg = <0x44004000 0x400>; 1174 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1175 dmas = <&dmamux1 37 0x400 0x01>, 1176 <&dmamux1 38 0x400 0x01>; 1177 dma-names = "rx", "tx"; 1178 access-controllers = <&etzpc STM32MP1_ETZPC_SPI1_ID>; 1179 status = "disabled"; 1180 }; 1181 1182 spi4: spi@44005000 { 1183 #address-cells = <1>; 1184 #size-cells = <0>; 1185 compatible = "st,stm32h7-spi"; 1186 reg = <0x44005000 0x400>; 1187 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1188 clocks = <&rcc SPI4_K>; 1189 resets = <&rcc SPI4_R>; 1190 dmas = <&dmamux1 83 0x400 0x05>, 1191 <&dmamux1 84 0x400 0x05>; 1192 dma-names = "rx", "tx"; 1193 access-controllers = <&etzpc STM32MP1_ETZPC_SPI4_ID>; 1194 status = "disabled"; 1195 }; 1196 1197 timers15: timer@44006000 { 1198 #address-cells = <1>; 1199 #size-cells = <0>; 1200 compatible = "st,stm32-timers"; 1201 reg = <0x44006000 0x400>; 1202 clocks = <&rcc TIM15_K>; 1203 clock-names = "int"; 1204 dmas = <&dmamux1 105 0x400 0x1>, 1205 <&dmamux1 106 0x400 0x1>, 1206 <&dmamux1 107 0x400 0x1>, 1207 <&dmamux1 108 0x400 0x1>; 1208 dma-names = "ch1", "up", "trig", "com"; 1209 access-controllers = <&etzpc STM32MP1_ETZPC_TIM15_ID>; 1210 status = "disabled"; 1211 1212 pwm { 1213 compatible = "st,stm32-pwm"; 1214 #pwm-cells = <3>; 1215 status = "disabled"; 1216 }; 1217 1218 timer@14 { 1219 compatible = "st,stm32h7-timer-trigger"; 1220 reg = <14>; 1221 status = "disabled"; 1222 }; 1223 }; 1224 1225 timers16: timer@44007000 { 1226 #address-cells = <1>; 1227 #size-cells = <0>; 1228 compatible = "st,stm32-timers"; 1229 reg = <0x44007000 0x400>; 1230 clocks = <&rcc TIM16_K>; 1231 clock-names = "int"; 1232 dmas = <&dmamux1 109 0x400 0x1>, 1233 <&dmamux1 110 0x400 0x1>; 1234 dma-names = "ch1", "up"; 1235 access-controllers = <&etzpc STM32MP1_ETZPC_TIM16_ID>; 1236 status = "disabled"; 1237 1238 pwm { 1239 compatible = "st,stm32-pwm"; 1240 #pwm-cells = <3>; 1241 status = "disabled"; 1242 }; 1243 timer@15 { 1244 compatible = "st,stm32h7-timer-trigger"; 1245 reg = <15>; 1246 status = "disabled"; 1247 }; 1248 }; 1249 1250 timers17: timer@44008000 { 1251 #address-cells = <1>; 1252 #size-cells = <0>; 1253 compatible = "st,stm32-timers"; 1254 reg = <0x44008000 0x400>; 1255 clocks = <&rcc TIM17_K>; 1256 clock-names = "int"; 1257 dmas = <&dmamux1 111 0x400 0x1>, 1258 <&dmamux1 112 0x400 0x1>; 1259 dma-names = "ch1", "up"; 1260 access-controllers = <&etzpc STM32MP1_ETZPC_TIM17_ID>; 1261 status = "disabled"; 1262 1263 pwm { 1264 compatible = "st,stm32-pwm"; 1265 #pwm-cells = <3>; 1266 status = "disabled"; 1267 }; 1268 1269 timer@16 { 1270 compatible = "st,stm32h7-timer-trigger"; 1271 reg = <16>; 1272 status = "disabled"; 1273 }; 1274 }; 1275 1276 spi5: spi@44009000 { 1277 #address-cells = <1>; 1278 #size-cells = <0>; 1279 compatible = "st,stm32h7-spi"; 1280 reg = <0x44009000 0x400>; 1281 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1282 clocks = <&rcc SPI5_K>; 1283 resets = <&rcc SPI5_R>; 1284 dmas = <&dmamux1 85 0x400 0x05>, 1285 <&dmamux1 86 0x400 0x05>; 1286 dma-names = "rx", "tx"; 1287 access-controllers = <&etzpc STM32MP1_ETZPC_SPI5_ID>; 1288 status = "disabled"; 1289 }; 1290 1291 sai1: sai@4400a000 { 1292 compatible = "st,stm32h7-sai"; 1293 #address-cells = <1>; 1294 #size-cells = <1>; 1295 ranges = <0 0x4400a000 0x400>; 1296 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; 1297 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1298 resets = <&rcc SAI1_R>; 1299 access-controllers = <&etzpc STM32MP1_ETZPC_SAI1_ID>; 1300 status = "disabled"; 1301 1302 sai1a: audio-controller@4400a004 { 1303 #sound-dai-cells = <0>; 1304 1305 compatible = "st,stm32-sai-sub-a"; 1306 reg = <0x4 0x20>; 1307 clocks = <&rcc SAI1_K>; 1308 clock-names = "sai_ck"; 1309 dmas = <&dmamux1 87 0x400 0x01>; 1310 status = "disabled"; 1311 }; 1312 1313 sai1b: audio-controller@4400a024 { 1314 #sound-dai-cells = <0>; 1315 compatible = "st,stm32-sai-sub-b"; 1316 reg = <0x24 0x20>; 1317 clocks = <&rcc SAI1_K>; 1318 clock-names = "sai_ck"; 1319 dmas = <&dmamux1 88 0x400 0x01>; 1320 status = "disabled"; 1321 }; 1322 }; 1323 1324 sai2: sai@4400b000 { 1325 compatible = "st,stm32h7-sai"; 1326 #address-cells = <1>; 1327 #size-cells = <1>; 1328 ranges = <0 0x4400b000 0x400>; 1329 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; 1330 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1331 resets = <&rcc SAI2_R>; 1332 access-controllers = <&etzpc STM32MP1_ETZPC_SAI2_ID>; 1333 status = "disabled"; 1334 1335 sai2a: audio-controller@4400b004 { 1336 #sound-dai-cells = <0>; 1337 compatible = "st,stm32-sai-sub-a"; 1338 reg = <0x4 0x20>; 1339 clocks = <&rcc SAI2_K>; 1340 clock-names = "sai_ck"; 1341 dmas = <&dmamux1 89 0x400 0x01>; 1342 status = "disabled"; 1343 }; 1344 1345 sai2b: audio-controller@4400b024 { 1346 #sound-dai-cells = <0>; 1347 compatible = "st,stm32-sai-sub-b"; 1348 reg = <0x24 0x20>; 1349 clocks = <&rcc SAI2_K>; 1350 clock-names = "sai_ck"; 1351 dmas = <&dmamux1 90 0x400 0x01>; 1352 status = "disabled"; 1353 }; 1354 }; 1355 1356 sai3: sai@4400c000 { 1357 compatible = "st,stm32h7-sai"; 1358 #address-cells = <1>; 1359 #size-cells = <1>; 1360 ranges = <0 0x4400c000 0x400>; 1361 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; 1362 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1363 resets = <&rcc SAI3_R>; 1364 access-controllers = <&etzpc STM32MP1_ETZPC_SAI3_ID>; 1365 status = "disabled"; 1366 1367 sai3a: audio-controller@4400c004 { 1368 #sound-dai-cells = <0>; 1369 compatible = "st,stm32-sai-sub-a"; 1370 reg = <0x04 0x20>; 1371 clocks = <&rcc SAI3_K>; 1372 clock-names = "sai_ck"; 1373 dmas = <&dmamux1 113 0x400 0x01>; 1374 status = "disabled"; 1375 }; 1376 1377 sai3b: audio-controller@4400c024 { 1378 #sound-dai-cells = <0>; 1379 compatible = "st,stm32-sai-sub-b"; 1380 reg = <0x24 0x20>; 1381 clocks = <&rcc SAI3_K>; 1382 clock-names = "sai_ck"; 1383 dmas = <&dmamux1 114 0x400 0x01>; 1384 status = "disabled"; 1385 }; 1386 }; 1387 1388 dfsdm: dfsdm@4400d000 { 1389 compatible = "st,stm32mp1-dfsdm"; 1390 reg = <0x4400d000 0x800>; 1391 clocks = <&rcc DFSDM_K>; 1392 clock-names = "dfsdm"; 1393 #address-cells = <1>; 1394 #size-cells = <0>; 1395 access-controllers = <&etzpc STM32MP1_ETZPC_DFSDM_ID>; 1396 status = "disabled"; 1397 1398 dfsdm0: filter@0 { 1399 compatible = "st,stm32-dfsdm-adc"; 1400 #io-channel-cells = <1>; 1401 reg = <0>; 1402 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 1403 dmas = <&dmamux1 101 0x400 0x01>; 1404 dma-names = "rx"; 1405 status = "disabled"; 1406 }; 1407 1408 dfsdm1: filter@1 { 1409 compatible = "st,stm32-dfsdm-adc"; 1410 #io-channel-cells = <1>; 1411 reg = <1>; 1412 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1413 dmas = <&dmamux1 102 0x400 0x01>; 1414 dma-names = "rx"; 1415 status = "disabled"; 1416 }; 1417 1418 dfsdm2: filter@2 { 1419 compatible = "st,stm32-dfsdm-adc"; 1420 #io-channel-cells = <1>; 1421 reg = <2>; 1422 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1423 dmas = <&dmamux1 103 0x400 0x01>; 1424 dma-names = "rx"; 1425 status = "disabled"; 1426 }; 1427 1428 dfsdm3: filter@3 { 1429 compatible = "st,stm32-dfsdm-adc"; 1430 #io-channel-cells = <1>; 1431 reg = <3>; 1432 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1433 dmas = <&dmamux1 104 0x400 0x01>; 1434 dma-names = "rx"; 1435 status = "disabled"; 1436 }; 1437 1438 dfsdm4: filter@4 { 1439 compatible = "st,stm32-dfsdm-adc"; 1440 #io-channel-cells = <1>; 1441 reg = <4>; 1442 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1443 dmas = <&dmamux1 91 0x400 0x01>; 1444 dma-names = "rx"; 1445 status = "disabled"; 1446 }; 1447 1448 dfsdm5: filter@5 { 1449 compatible = "st,stm32-dfsdm-adc"; 1450 #io-channel-cells = <1>; 1451 reg = <5>; 1452 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1453 dmas = <&dmamux1 92 0x400 0x01>; 1454 dma-names = "rx"; 1455 status = "disabled"; 1456 }; 1457 }; 1458 1459 dma1: dma-controller@48000000 { 1460 compatible = "st,stm32-dma"; 1461 reg = <0x48000000 0x400>; 1462 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1466 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1470 clocks = <&rcc DMA1>; 1471 resets = <&rcc DMA1_R>; 1472 #dma-cells = <4>; 1473 st,mem2mem; 1474 dma-requests = <8>; 1475 access-controllers = <&etzpc STM32MP1_ETZPC_DMA1_ID>; 1476 status = "disabled"; 1477 }; 1478 1479 dma2: dma-controller@48001000 { 1480 compatible = "st,stm32-dma"; 1481 reg = <0x48001000 0x400>; 1482 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1490 clocks = <&rcc DMA2>; 1491 resets = <&rcc DMA2_R>; 1492 #dma-cells = <4>; 1493 st,mem2mem; 1494 dma-requests = <8>; 1495 access-controllers = <&etzpc STM32MP1_ETZPC_DMA2_ID>; 1496 status = "disabled"; 1497 }; 1498 1499 dmamux1: dma-router@48002000 { 1500 compatible = "st,stm32h7-dmamux"; 1501 reg = <0x48002000 0x40>; 1502 #dma-cells = <3>; 1503 dma-requests = <128>; 1504 dma-masters = <&dma1 &dma2>; 1505 dma-channels = <16>; 1506 clocks = <&rcc DMAMUX>; 1507 resets = <&rcc DMAMUX_R>; 1508 access-controllers = <&etzpc STM32MP1_ETZPC_DMAMUX_ID>; 1509 status = "disabled"; 1510 }; 1511 1512 adc: adc@48003000 { 1513 compatible = "st,stm32mp1-adc-core"; 1514 reg = <0x48003000 0x400>; 1515 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1516 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1517 clocks = <&rcc ADC12>, <&rcc ADC12_K>; 1518 clock-names = "bus", "adc"; 1519 interrupt-controller; 1520 st,syscfg = <&syscfg>; 1521 #interrupt-cells = <1>; 1522 #address-cells = <1>; 1523 #size-cells = <0>; 1524 access-controllers = <&etzpc STM32MP1_ETZPC_ADC_ID>; 1525 status = "disabled"; 1526 1527 adc1: adc@0 { 1528 compatible = "st,stm32mp1-adc"; 1529 #io-channel-cells = <1>; 1530 reg = <0x0>; 1531 interrupt-parent = <&adc>; 1532 interrupts = <0>; 1533 dmas = <&dmamux1 9 0x400 0x01>; 1534 dma-names = "rx"; 1535 status = "disabled"; 1536 }; 1537 1538 adc2: adc@100 { 1539 compatible = "st,stm32mp1-adc"; 1540 #io-channel-cells = <1>; 1541 reg = <0x100>; 1542 interrupt-parent = <&adc>; 1543 interrupts = <1>; 1544 dmas = <&dmamux1 10 0x400 0x01>; 1545 dma-names = "rx"; 1546 status = "disabled"; 1547 }; 1548 }; 1549 1550 sdmmc3: mmc@48004000 { 1551 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 1552 arm,primecell-periphid = <0x00253180>; 1553 reg = <0x48004000 0x400>; 1554 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1555 interrupt-names = "cmd_irq"; 1556 clocks = <&rcc SDMMC3_K>; 1557 clock-names = "apb_pclk"; 1558 resets = <&rcc SDMMC3_R>; 1559 cap-sd-highspeed; 1560 cap-mmc-highspeed; 1561 max-frequency = <120000000>; 1562 access-controllers = <&etzpc STM32MP1_ETZPC_SDMMC3_ID>; 1563 status = "disabled"; 1564 }; 1565 1566 usbotg_hs: usb-otg@49000000 { 1567 compatible = "st,stm32mp15-hsotg", "snps,dwc2"; 1568 reg = <0x49000000 0x10000>; 1569 clocks = <&rcc USBO_K>; 1570 clock-names = "otg"; 1571 resets = <&rcc USBO_R>; 1572 reset-names = "dwc2"; 1573 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1574 g-rx-fifo-size = <512>; 1575 g-np-tx-fifo-size = <32>; 1576 g-tx-fifo-size = <256 16 16 16 16 16 16 16>; 1577 dr_mode = "otg"; 1578 otg-rev = <0x200>; 1579 usb33d-supply = <&usb33>; 1580 access-controllers = <&etzpc STM32MP1_ETZPC_OTG_ID>; 1581 status = "disabled"; 1582 }; 1583 1584 dcmi: dcmi@4c006000 { 1585 compatible = "st,stm32-dcmi"; 1586 reg = <0x4c006000 0x400>; 1587 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1588 resets = <&rcc CAMITF_R>; 1589 clocks = <&rcc DCMI>; 1590 clock-names = "mclk"; 1591 dmas = <&dmamux1 75 0x400 0x01>; 1592 dma-names = "tx"; 1593 access-controllers = <&etzpc STM32MP1_ETZPC_DCMI_ID>; 1594 status = "disabled"; 1595 }; 1596 1597 lptimer2: timer@50021000 { 1598 #address-cells = <1>; 1599 #size-cells = <0>; 1600 compatible = "st,stm32-lptimer"; 1601 reg = <0x50021000 0x400>; 1602 interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; 1603 clocks = <&rcc LPTIM2_K>; 1604 clock-names = "mux"; 1605 wakeup-source; 1606 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM2_ID>; 1607 status = "disabled"; 1608 1609 pwm { 1610 compatible = "st,stm32-pwm-lp"; 1611 #pwm-cells = <3>; 1612 status = "disabled"; 1613 }; 1614 1615 trigger@1 { 1616 compatible = "st,stm32-lptimer-trigger"; 1617 reg = <1>; 1618 status = "disabled"; 1619 }; 1620 1621 counter { 1622 compatible = "st,stm32-lptimer-counter"; 1623 status = "disabled"; 1624 }; 1625 }; 1626 1627 lptimer3: timer@50022000 { 1628 #address-cells = <1>; 1629 #size-cells = <0>; 1630 compatible = "st,stm32-lptimer"; 1631 reg = <0x50022000 0x400>; 1632 interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; 1633 clocks = <&rcc LPTIM3_K>; 1634 clock-names = "mux"; 1635 wakeup-source; 1636 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM3_ID>; 1637 status = "disabled"; 1638 1639 pwm { 1640 compatible = "st,stm32-pwm-lp"; 1641 #pwm-cells = <3>; 1642 status = "disabled"; 1643 }; 1644 1645 trigger@2 { 1646 compatible = "st,stm32-lptimer-trigger"; 1647 reg = <2>; 1648 status = "disabled"; 1649 }; 1650 }; 1651 1652 lptimer4: timer@50023000 { 1653 compatible = "st,stm32-lptimer"; 1654 reg = <0x50023000 0x400>; 1655 interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; 1656 clocks = <&rcc LPTIM4_K>; 1657 clock-names = "mux"; 1658 wakeup-source; 1659 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM4_ID>; 1660 status = "disabled"; 1661 1662 pwm { 1663 compatible = "st,stm32-pwm-lp"; 1664 #pwm-cells = <3>; 1665 status = "disabled"; 1666 }; 1667 }; 1668 1669 lptimer5: timer@50024000 { 1670 compatible = "st,stm32-lptimer"; 1671 reg = <0x50024000 0x400>; 1672 interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; 1673 clocks = <&rcc LPTIM5_K>; 1674 clock-names = "mux"; 1675 wakeup-source; 1676 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM5_ID>; 1677 status = "disabled"; 1678 1679 pwm { 1680 compatible = "st,stm32-pwm-lp"; 1681 #pwm-cells = <3>; 1682 status = "disabled"; 1683 }; 1684 }; 1685 1686 vrefbuf: vrefbuf@50025000 { 1687 compatible = "st,stm32-vrefbuf"; 1688 reg = <0x50025000 0x8>; 1689 regulator-min-microvolt = <1500000>; 1690 regulator-max-microvolt = <2500000>; 1691 clocks = <&rcc VREF>; 1692 access-controllers = <&etzpc STM32MP1_ETZPC_VREFBUF_ID>; 1693 status = "disabled"; 1694 }; 1695 1696 sai4: sai@50027000 { 1697 compatible = "st,stm32h7-sai"; 1698 #address-cells = <1>; 1699 #size-cells = <1>; 1700 ranges = <0 0x50027000 0x400>; 1701 reg = <0x50027000 0x4>, <0x500273f0 0x10>; 1702 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1703 resets = <&rcc SAI4_R>; 1704 access-controllers = <&etzpc STM32MP1_ETZPC_SAI4_ID>; 1705 status = "disabled"; 1706 1707 sai4a: audio-controller@50027004 { 1708 #sound-dai-cells = <0>; 1709 compatible = "st,stm32-sai-sub-a"; 1710 reg = <0x04 0x20>; 1711 clocks = <&rcc SAI4_K>; 1712 clock-names = "sai_ck"; 1713 dmas = <&dmamux1 99 0x400 0x01>; 1714 status = "disabled"; 1715 }; 1716 1717 sai4b: audio-controller@50027024 { 1718 #sound-dai-cells = <0>; 1719 compatible = "st,stm32-sai-sub-b"; 1720 reg = <0x24 0x20>; 1721 clocks = <&rcc SAI4_K>; 1722 clock-names = "sai_ck"; 1723 dmas = <&dmamux1 100 0x400 0x01>; 1724 status = "disabled"; 1725 }; 1726 }; 1727 1728 hash1: hash@54002000 { 1729 compatible = "st,stm32f756-hash"; 1730 reg = <0x54002000 0x400>; 1731 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1732 clocks = <&rcc HASH1>; 1733 resets = <&rcc HASH1_R>; 1734 dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; 1735 dma-names = "in"; 1736 dma-maxburst = <2>; 1737 access-controllers = <&etzpc STM32MP1_ETZPC_HASH1_ID>; 1738 status = "disabled"; 1739 }; 1740 1741 rng1: rng@54003000 { 1742 compatible = "st,stm32-rng"; 1743 reg = <0x54003000 0x400>; 1744 clocks = <&rcc RNG1_K>; 1745 resets = <&rcc RNG1_R>; 1746 access-controllers = <&etzpc STM32MP1_ETZPC_RNG1_ID>; 1747 status = "disabled"; 1748 }; 1749 1750 fmc: memory-controller@58002000 { 1751 #address-cells = <2>; 1752 #size-cells = <1>; 1753 compatible = "st,stm32mp1-fmc2-ebi"; 1754 reg = <0x58002000 0x1000>; 1755 clocks = <&rcc FMC_K>; 1756 resets = <&rcc FMC_R>; 1757 access-controllers = <&etzpc STM32MP1_ETZPC_FMC_ID>; 1758 status = "disabled"; 1759 1760 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 1761 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 1762 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 1763 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 1764 <4 0 0x80000000 0x10000000>; /* NAND */ 1765 1766 nand-controller@4,0 { 1767 #address-cells = <1>; 1768 #size-cells = <0>; 1769 compatible = "st,stm32mp1-fmc2-nfc"; 1770 reg = <4 0x00000000 0x1000>, 1771 <4 0x08010000 0x1000>, 1772 <4 0x08020000 0x1000>, 1773 <4 0x01000000 0x1000>, 1774 <4 0x09010000 0x1000>, 1775 <4 0x09020000 0x1000>; 1776 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1777 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, 1778 <&mdma1 20 0x2 0x12000a08 0x0 0x0>, 1779 <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; 1780 dma-names = "tx", "rx", "ecc"; 1781 status = "disabled"; 1782 }; 1783 }; 1784 1785 qspi: spi@58003000 { 1786 compatible = "st,stm32f469-qspi"; 1787 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; 1788 reg-names = "qspi", "qspi_mm"; 1789 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 1790 dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, 1791 <&mdma1 22 0x2 0x10100008 0x0 0x0>; 1792 dma-names = "tx", "rx"; 1793 clocks = <&rcc QSPI_K>; 1794 resets = <&rcc QSPI_R>; 1795 #address-cells = <1>; 1796 #size-cells = <0>; 1797 access-controllers = <&etzpc STM32MP1_ETZPC_QSPI_ID>; 1798 status = "disabled"; 1799 }; 1800 1801 ethernet0: ethernet@5800a000 { 1802 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; 1803 reg = <0x5800a000 0x2000>; 1804 reg-names = "stmmaceth"; 1805 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1806 interrupt-names = "macirq"; 1807 clock-names = "stmmaceth", 1808 "mac-clk-tx", 1809 "mac-clk-rx", 1810 "eth-ck", 1811 "ptp_ref", 1812 "ethstp"; 1813 clocks = <&rcc ETHMAC>, 1814 <&rcc ETHTX>, 1815 <&rcc ETHRX>, 1816 <&rcc ETHCK_K>, 1817 <&rcc ETHPTP_K>, 1818 <&rcc ETHSTP>; 1819 st,syscon = <&syscfg 0x4>; 1820 snps,mixed-burst; 1821 snps,pbl = <2>; 1822 snps,en-tx-lpi-clockgating; 1823 snps,axi-config = <&stmmac_axi_config_0>; 1824 snps,tso; 1825 access-controllers = <&etzpc STM32MP1_ETZPC_ETH_ID>; 1826 status = "disabled"; 1827 1828 stmmac_axi_config_0: stmmac-axi-config { 1829 snps,wr_osr_lmt = <0x7>; 1830 snps,rd_osr_lmt = <0x7>; 1831 snps,blen = <0 0 0 0 16 8 4>; 1832 }; 1833 }; 1834 1835 usart1: serial@5c000000 { 1836 compatible = "st,stm32h7-uart"; 1837 reg = <0x5c000000 0x400>; 1838 interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; 1839 clocks = <&rcc USART1_K>; 1840 wakeup-source; 1841 access-controllers = <&etzpc STM32MP1_ETZPC_USART1_ID>; 1842 status = "disabled"; 1843 }; 1844 1845 spi6: spi@5c001000 { 1846 #address-cells = <1>; 1847 #size-cells = <0>; 1848 compatible = "st,stm32h7-spi"; 1849 reg = <0x5c001000 0x400>; 1850 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1851 clocks = <&rcc SPI6_K>; 1852 resets = <&rcc SPI6_R>; 1853 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, 1854 <&mdma1 35 0x0 0x40002 0x0 0x0>; 1855 dma-names = "rx", "tx"; 1856 access-controllers = <&etzpc STM32MP1_ETZPC_SPI6_ID>; 1857 status = "disabled"; 1858 }; 1859 1860 i2c4: i2c@5c002000 { 1861 compatible = "st,stm32mp15-i2c"; 1862 reg = <0x5c002000 0x400>; 1863 interrupt-names = "event", "error"; 1864 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1866 clocks = <&rcc I2C4_K>; 1867 resets = <&rcc I2C4_R>; 1868 #address-cells = <1>; 1869 #size-cells = <0>; 1870 st,syscfg-fmp = <&syscfg 0x4 0x8>; 1871 wakeup-source; 1872 i2c-analog-filter; 1873 access-controllers = <&etzpc STM32MP1_ETZPC_I2C4_ID>; 1874 status = "disabled"; 1875 }; 1876 1877 iwdg1: watchdog@5c003000 { 1878 compatible = "st,stm32mp1-iwdg"; 1879 reg = <0x5C003000 0x400>; 1880 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1881 clocks = <&rcc IWDG1>, <&rcc CK_LSI>; 1882 clock-names = "pclk", "lsi"; 1883 access-controllers = <&etzpc STM32MP1_ETZPC_IWDG1_ID>; 1884 status = "disabled"; 1885 }; 1886 1887 i2c6: i2c@5c009000 { 1888 compatible = "st,stm32mp15-i2c"; 1889 reg = <0x5c009000 0x400>; 1890 interrupt-names = "event", "error"; 1891 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1892 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1893 clocks = <&rcc I2C6_K>; 1894 resets = <&rcc I2C6_R>; 1895 #address-cells = <1>; 1896 #size-cells = <0>; 1897 st,syscfg-fmp = <&syscfg 0x4 0x20>; 1898 wakeup-source; 1899 i2c-analog-filter; 1900 access-controllers = <&etzpc STM32MP1_ETZPC_I2C6_ID>; 1901 status = "disabled"; 1902 }; 1903 }; 1904 }; 1905 1906 mlahb: ahb { 1907 compatible = "st,mlahb", "simple-bus"; 1908 #address-cells = <1>; 1909 #size-cells = <1>; 1910 ranges; 1911 dma-ranges = <0x00000000 0x38000000 0x10000>, 1912 <0x10000000 0x10000000 0x60000>, 1913 <0x30000000 0x30000000 0x60000>; 1914 1915 m4_rproc: m4@10000000 { 1916 compatible = "st,stm32mp1-m4"; 1917 reg = <0x10000000 0x40000>, 1918 <0x30000000 0x40000>, 1919 <0x38000000 0x10000>; 1920 resets = <&rcc MCU_R>, <&rcc MCU_HOLD_BOOT_R>; 1921 reset-names = "mcu_rst", "hold_boot"; 1922 st,syscfg-tz = <&rcc 0x000 0x1>; 1923 st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; 1924 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; 1925 st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; 1926 status = "disabled"; 1927 }; 1928 }; 1929}; 1930