1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2017-2025 - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/stm32mp1-clks.h> 8#include <dt-bindings/reset/stm32mp1-resets.h> 9#include <dt-bindings/firewall/stm32mp15-etzpc.h> 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a7"; 21 clock-frequency = <650000000>; 22 device_type = "cpu"; 23 reg = <0>; 24 }; 25 }; 26 27 arm-pmu { 28 compatible = "arm,cortex-a7-pmu"; 29 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 30 interrupt-affinity = <&cpu0>; 31 interrupt-parent = <&intc>; 32 }; 33 34 psci { 35 compatible = "arm,psci-1.0"; 36 method = "smc"; 37 }; 38 39 intc: interrupt-controller@a0021000 { 40 compatible = "arm,cortex-a7-gic"; 41 #interrupt-cells = <3>; 42 interrupt-controller; 43 reg = <0xa0021000 0x1000>, 44 <0xa0022000 0x2000>; 45 }; 46 47 timer { 48 compatible = "arm,armv7-timer"; 49 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 50 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 51 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 52 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 53 interrupt-parent = <&intc>; 54 }; 55 56 clocks { 57 clk_hse: clk-hse { 58 #clock-cells = <0>; 59 compatible = "fixed-clock"; 60 clock-frequency = <24000000>; 61 }; 62 63 clk_hsi: clk-hsi { 64 #clock-cells = <0>; 65 compatible = "fixed-clock"; 66 clock-frequency = <64000000>; 67 }; 68 69 clk_lse: clk-lse { 70 #clock-cells = <0>; 71 compatible = "fixed-clock"; 72 clock-frequency = <32768>; 73 }; 74 75 clk_lsi: clk-lsi { 76 #clock-cells = <0>; 77 compatible = "fixed-clock"; 78 clock-frequency = <32000>; 79 }; 80 81 clk_csi: clk-csi { 82 #clock-cells = <0>; 83 compatible = "fixed-clock"; 84 clock-frequency = <4000000>; 85 }; 86 }; 87 88 thermal-zones { 89 cpu_thermal: cpu-thermal { 90 polling-delay-passive = <0>; 91 polling-delay = <0>; 92 thermal-sensors = <&dts>; 93 94 trips { 95 cpu_alert1: cpu-alert1 { 96 temperature = <85000>; 97 hysteresis = <0>; 98 type = "passive"; 99 }; 100 101 cpu-crit { 102 temperature = <120000>; 103 hysteresis = <0>; 104 type = "critical"; 105 }; 106 }; 107 108 cooling-maps { 109 }; 110 }; 111 }; 112 113 booster: regulator-booster { 114 compatible = "st,stm32mp1-booster"; 115 st,syscfg = <&syscfg>; 116 status = "disabled"; 117 }; 118 119 soc { 120 compatible = "simple-bus"; 121 #address-cells = <1>; 122 #size-cells = <1>; 123 interrupt-parent = <&intc>; 124 ranges; 125 126 ipcc: mailbox@4c001000 { 127 compatible = "st,stm32mp1-ipcc"; 128 #mbox-cells = <1>; 129 reg = <0x4c001000 0x400>; 130 st,proc-id = <0>; 131 interrupts-extended = 132 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 133 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 134 <&exti 61 1>; 135 interrupt-names = "rx", "tx", "wakeup"; 136 clocks = <&rcc IPCC>; 137 wakeup-source; 138 status = "disabled"; 139 }; 140 141 rcc: rcc@50000000 { 142 compatible = "st,stm32mp1-rcc", "syscon"; 143 reg = <0x50000000 0x1000>; 144 #clock-cells = <1>; 145 #reset-cells = <1>; 146 }; 147 148 pwr_regulators: pwr@50001000 { 149 compatible = "st,stm32mp1-pwr-reg"; 150 reg = <0x50001000 0x10>; 151 152 reg11: reg11 { 153 regulator-name = "reg11"; 154 regulator-min-microvolt = <1100000>; 155 regulator-max-microvolt = <1100000>; 156 }; 157 158 reg18: reg18 { 159 regulator-name = "reg18"; 160 regulator-min-microvolt = <1800000>; 161 regulator-max-microvolt = <1800000>; 162 }; 163 164 usb33: usb33 { 165 regulator-name = "usb33"; 166 regulator-min-microvolt = <3300000>; 167 regulator-max-microvolt = <3300000>; 168 }; 169 }; 170 171 pwr_mcu: pwr_mcu@50001014 { 172 compatible = "st,stm32mp151-pwr-mcu", "syscon"; 173 reg = <0x50001014 0x4>; 174 }; 175 176 exti: interrupt-controller@5000d000 { 177 compatible = "st,stm32mp1-exti"; 178 interrupt-controller; 179 #interrupt-cells = <2>; 180 reg = <0x5000d000 0x400>; 181 interrupts-extended = 182 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 183 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 184 <&intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 185 <&intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 186 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 187 <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 188 <&intc GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 189 <&intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 190 <&intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 191 <&intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 192 <&intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 193 <&intc GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 194 <&intc GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 195 <&intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 196 <&intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 197 <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 198 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 199 <0>, 200 <0>, 201 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 202 <0>, /* EXTI_20 */ 203 <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 204 <&intc GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 205 <&intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 206 <&intc GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 207 <&intc GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 208 <&intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 209 <&intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 210 <&intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 211 <&intc GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 212 <&intc GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 213 <&intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 214 <&intc GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 215 <&intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 216 <0>, 217 <0>, 218 <0>, 219 <0>, 220 <0>, 221 <0>, 222 <0>, /* EXTI_40 */ 223 <0>, 224 <0>, 225 <&intc GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 226 <&intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 227 <0>, 228 <0>, 229 <&intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 230 <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 231 <0>, 232 <&intc GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 233 <0>, 234 <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 235 <&intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 236 <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 237 <0>, 238 <0>, 239 <0>, 240 <0>, 241 <0>, 242 <0>, /* EXTI_60 */ 243 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 244 <0>, 245 <0>, 246 <0>, 247 <&intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 248 <0>, 249 <0>, 250 <&intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 251 <&intc GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 252 <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ 253 <0>, 254 <0>, 255 <&intc GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 256 }; 257 258 syscfg: syscon@50020000 { 259 compatible = "st,stm32mp157-syscfg", "syscon"; 260 reg = <0x50020000 0x400>; 261 clocks = <&rcc SYSCFG>; 262 }; 263 264 dts: thermal@50028000 { 265 compatible = "st,stm32-thermal"; 266 reg = <0x50028000 0x100>; 267 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&rcc TMPSENS>; 269 clock-names = "pclk"; 270 #thermal-sensor-cells = <0>; 271 status = "disabled"; 272 }; 273 274 mdma1: dma-controller@58000000 { 275 compatible = "st,stm32h7-mdma"; 276 reg = <0x58000000 0x1000>; 277 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 278 clocks = <&rcc MDMA>; 279 resets = <&rcc MDMA_R>; 280 #dma-cells = <5>; 281 dma-channels = <32>; 282 dma-requests = <48>; 283 }; 284 285 sdmmc1: mmc@58005000 { 286 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 287 arm,primecell-periphid = <0x00253180>; 288 reg = <0x58005000 0x1000>; 289 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 290 interrupt-names = "cmd_irq"; 291 clocks = <&rcc SDMMC1_K>; 292 clock-names = "apb_pclk"; 293 resets = <&rcc SDMMC1_R>; 294 cap-sd-highspeed; 295 cap-mmc-highspeed; 296 max-frequency = <120000000>; 297 status = "disabled"; 298 }; 299 300 sdmmc2: mmc@58007000 { 301 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 302 arm,primecell-periphid = <0x00253180>; 303 reg = <0x58007000 0x1000>; 304 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 305 interrupt-names = "cmd_irq"; 306 clocks = <&rcc SDMMC2_K>; 307 clock-names = "apb_pclk"; 308 resets = <&rcc SDMMC2_R>; 309 cap-sd-highspeed; 310 cap-mmc-highspeed; 311 max-frequency = <120000000>; 312 status = "disabled"; 313 }; 314 315 crc1: crc@58009000 { 316 compatible = "st,stm32f7-crc"; 317 reg = <0x58009000 0x400>; 318 clocks = <&rcc CRC1>; 319 status = "disabled"; 320 }; 321 322 usbh_ohci: usb@5800c000 { 323 compatible = "generic-ohci"; 324 reg = <0x5800c000 0x1000>; 325 clocks = <&usbphyc>, <&rcc USBH>; 326 resets = <&rcc USBH_R>; 327 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 328 status = "disabled"; 329 }; 330 331 usbh_ehci: usb@5800d000 { 332 compatible = "generic-ehci"; 333 reg = <0x5800d000 0x1000>; 334 clocks = <&usbphyc>, <&rcc USBH>; 335 resets = <&rcc USBH_R>; 336 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 337 companion = <&usbh_ohci>; 338 status = "disabled"; 339 }; 340 341 ltdc: display-controller@5a001000 { 342 compatible = "st,stm32-ltdc"; 343 reg = <0x5a001000 0x400>; 344 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&rcc LTDC_PX>; 347 clock-names = "lcd"; 348 resets = <&rcc LTDC_R>; 349 status = "disabled"; 350 351 port { 352 #address-cells = <1>; 353 #size-cells = <0>; 354 }; 355 }; 356 357 iwdg2: watchdog@5a002000 { 358 compatible = "st,stm32mp1-iwdg"; 359 reg = <0x5a002000 0x400>; 360 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 361 clocks = <&rcc IWDG2>, <&rcc CK_LSI>; 362 clock-names = "pclk", "lsi"; 363 status = "disabled"; 364 }; 365 366 usbphyc: usbphyc@5a006000 { 367 #address-cells = <1>; 368 #size-cells = <0>; 369 #clock-cells = <0>; 370 compatible = "st,stm32mp1-usbphyc"; 371 reg = <0x5a006000 0x1000>; 372 clocks = <&rcc USBPHY_K>; 373 resets = <&rcc USBPHY_R>; 374 vdda1v1-supply = <®11>; 375 vdda1v8-supply = <®18>; 376 status = "disabled"; 377 378 usbphyc_port0: usb-phy@0 { 379 #phy-cells = <0>; 380 reg = <0>; 381 }; 382 383 usbphyc_port1: usb-phy@1 { 384 #phy-cells = <1>; 385 reg = <1>; 386 }; 387 }; 388 389 rtc: rtc@5c004000 { 390 compatible = "st,stm32mp1-rtc"; 391 reg = <0x5c004000 0x400>; 392 clocks = <&rcc RTCAPB>, <&rcc RTC>; 393 clock-names = "pclk", "rtc_ck"; 394 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; 395 status = "disabled"; 396 }; 397 398 bsec: efuse@5c005000 { 399 compatible = "st,stm32mp15-bsec"; 400 reg = <0x5c005000 0x400>; 401 #address-cells = <1>; 402 #size-cells = <1>; 403 404 cfg0_otp: cfg0_otp@0 { 405 reg = <0x0 0x1>; 406 }; 407 part_number_otp: part_number_otp@4 { 408 reg = <0x4 0x1>; 409 }; 410 monotonic_otp: monotonic_otp@10 { 411 reg = <0x10 0x4>; 412 }; 413 nand_otp: nand_otp@24 { 414 reg = <0x24 0x4>; 415 }; 416 uid_otp: uid_otp@34 { 417 reg = <0x34 0xc>; 418 }; 419 package_otp: package_otp@40 { 420 reg = <0x40 0x4>; 421 }; 422 hw2_otp: hw2_otp@48 { 423 reg = <0x48 0x4>; 424 }; 425 ts_cal1: calib@5c { 426 reg = <0x5c 0x2>; 427 }; 428 ts_cal2: calib@5e { 429 reg = <0x5e 0x2>; 430 }; 431 pkh_otp: pkh_otp@60 { 432 reg = <0x60 0x20>; 433 }; 434 ethernet_mac_address: mac@e4 { 435 reg = <0xe4 0x8>; 436 st,non-secure-otp; 437 }; 438 }; 439 440 tamp: tamp@5c00a000 { 441 compatible = "st,stm32-tamp", "syscon", "simple-mfd"; 442 reg = <0x5c00a000 0x400>; 443 clocks = <&rcc RTCAPB>; 444 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 445 st,backup-zones = <10 5 17>; 446 }; 447 448 /* 449 * Break node order to solve dependency probe issue between 450 * pinctrl and exti. 451 */ 452 pinctrl: pinctrl@50002000 { 453 #address-cells = <1>; 454 #size-cells = <1>; 455 compatible = "st,stm32mp157-pinctrl"; 456 ranges = <0 0x50002000 0xa400>; 457 interrupt-parent = <&exti>; 458 st,syscfg = <&exti 0x60 0xff>; 459 460 gpioa: gpio@50002000 { 461 gpio-controller; 462 #gpio-cells = <2>; 463 interrupt-controller; 464 #interrupt-cells = <2>; 465 reg = <0x0 0x400>; 466 clocks = <&rcc GPIOA>; 467 st,bank-name = "GPIOA"; 468 status = "disabled"; 469 }; 470 471 gpiob: gpio@50003000 { 472 gpio-controller; 473 #gpio-cells = <2>; 474 interrupt-controller; 475 #interrupt-cells = <2>; 476 reg = <0x1000 0x400>; 477 clocks = <&rcc GPIOB>; 478 st,bank-name = "GPIOB"; 479 status = "disabled"; 480 }; 481 482 gpioc: gpio@50004000 { 483 gpio-controller; 484 #gpio-cells = <2>; 485 interrupt-controller; 486 #interrupt-cells = <2>; 487 reg = <0x2000 0x400>; 488 clocks = <&rcc GPIOC>; 489 st,bank-name = "GPIOC"; 490 status = "disabled"; 491 }; 492 493 gpiod: gpio@50005000 { 494 gpio-controller; 495 #gpio-cells = <2>; 496 interrupt-controller; 497 #interrupt-cells = <2>; 498 reg = <0x3000 0x400>; 499 clocks = <&rcc GPIOD>; 500 st,bank-name = "GPIOD"; 501 status = "disabled"; 502 }; 503 504 gpioe: gpio@50006000 { 505 gpio-controller; 506 #gpio-cells = <2>; 507 interrupt-controller; 508 #interrupt-cells = <2>; 509 reg = <0x4000 0x400>; 510 clocks = <&rcc GPIOE>; 511 st,bank-name = "GPIOE"; 512 status = "disabled"; 513 }; 514 515 gpiof: gpio@50007000 { 516 gpio-controller; 517 #gpio-cells = <2>; 518 interrupt-controller; 519 #interrupt-cells = <2>; 520 reg = <0x5000 0x400>; 521 clocks = <&rcc GPIOF>; 522 st,bank-name = "GPIOF"; 523 status = "disabled"; 524 }; 525 526 gpiog: gpio@50008000 { 527 gpio-controller; 528 #gpio-cells = <2>; 529 interrupt-controller; 530 #interrupt-cells = <2>; 531 reg = <0x6000 0x400>; 532 clocks = <&rcc GPIOG>; 533 st,bank-name = "GPIOG"; 534 status = "disabled"; 535 }; 536 537 gpioh: gpio@50009000 { 538 gpio-controller; 539 #gpio-cells = <2>; 540 interrupt-controller; 541 #interrupt-cells = <2>; 542 reg = <0x7000 0x400>; 543 clocks = <&rcc GPIOH>; 544 st,bank-name = "GPIOH"; 545 status = "disabled"; 546 }; 547 548 gpioi: gpio@5000a000 { 549 gpio-controller; 550 #gpio-cells = <2>; 551 interrupt-controller; 552 #interrupt-cells = <2>; 553 reg = <0x8000 0x400>; 554 clocks = <&rcc GPIOI>; 555 st,bank-name = "GPIOI"; 556 status = "disabled"; 557 }; 558 559 gpioj: gpio@5000b000 { 560 gpio-controller; 561 #gpio-cells = <2>; 562 interrupt-controller; 563 #interrupt-cells = <2>; 564 reg = <0x9000 0x400>; 565 clocks = <&rcc GPIOJ>; 566 st,bank-name = "GPIOJ"; 567 status = "disabled"; 568 }; 569 570 gpiok: gpio@5000c000 { 571 gpio-controller; 572 #gpio-cells = <2>; 573 interrupt-controller; 574 #interrupt-cells = <2>; 575 reg = <0xa000 0x400>; 576 clocks = <&rcc GPIOK>; 577 st,bank-name = "GPIOK"; 578 status = "disabled"; 579 }; 580 }; 581 582 pinctrl_z: pinctrl@54004000 { 583 #address-cells = <1>; 584 #size-cells = <1>; 585 compatible = "st,stm32mp157-z-pinctrl"; 586 ranges = <0 0x54004000 0x400>; 587 interrupt-parent = <&exti>; 588 st,syscfg = <&exti 0x60 0xff>; 589 590 gpioz: gpio@54004000 { 591 gpio-controller; 592 #gpio-cells = <2>; 593 interrupt-controller; 594 #interrupt-cells = <2>; 595 #access-controller-cells = <1>; 596 reg = <0 0x400>; 597 clocks = <&rcc GPIOZ>; 598 st,bank-name = "GPIOZ"; 599 st,bank-ioport = <11>; 600 status = "disabled"; 601 }; 602 }; 603 604 tzc400: tzc@5c006000 { 605 compatible = "st,stm32mp1-tzc"; 606 reg = <0x5c006000 0x1000>; 607 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 608 clocks = <&rcc TZC1>, <&rcc TZC2>; 609 st,mem-map = <0xc0000000 0x40000000>; 610 }; 611 612 etzpc: etzpc@5c007000 { 613 compatible = "st,stm32-etzpc", "simple-bus"; 614 reg = <0x5C007000 0x400>; 615 clocks = <&rcc TZPC>; 616 #address-cells = <1>; 617 #size-cells = <1>; 618 #access-controller-cells = <1>; 619 620 timers2: timer@40000000 { 621 #address-cells = <1>; 622 #size-cells = <0>; 623 compatible = "st,stm32-timers"; 624 reg = <0x40000000 0x400>; 625 clocks = <&rcc TIM2_K>; 626 clock-names = "int"; 627 dmas = <&dmamux1 18 0x400 0x1>, 628 <&dmamux1 19 0x400 0x1>, 629 <&dmamux1 20 0x400 0x1>, 630 <&dmamux1 21 0x400 0x1>, 631 <&dmamux1 22 0x400 0x1>; 632 dma-names = "ch1", "ch2", "ch3", "ch4", "up"; 633 access-controllers = <&etzpc STM32MP1_ETZPC_TIM2_ID>; 634 status = "disabled"; 635 636 pwm { 637 compatible = "st,stm32-pwm"; 638 #pwm-cells = <3>; 639 status = "disabled"; 640 }; 641 642 timer@1 { 643 compatible = "st,stm32h7-timer-trigger"; 644 reg = <1>; 645 status = "disabled"; 646 }; 647 648 counter { 649 compatible = "st,stm32-timer-counter"; 650 status = "disabled"; 651 }; 652 }; 653 654 timers3: timer@40001000 { 655 #address-cells = <1>; 656 #size-cells = <0>; 657 compatible = "st,stm32-timers"; 658 reg = <0x40001000 0x400>; 659 clocks = <&rcc TIM3_K>; 660 clock-names = "int"; 661 dmas = <&dmamux1 23 0x400 0x1>, 662 <&dmamux1 24 0x400 0x1>, 663 <&dmamux1 25 0x400 0x1>, 664 <&dmamux1 26 0x400 0x1>, 665 <&dmamux1 27 0x400 0x1>, 666 <&dmamux1 28 0x400 0x1>; 667 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 668 access-controllers = <&etzpc STM32MP1_ETZPC_TIM3_ID>; 669 status = "disabled"; 670 671 pwm { 672 compatible = "st,stm32-pwm"; 673 #pwm-cells = <3>; 674 status = "disabled"; 675 }; 676 677 timer@2 { 678 compatible = "st,stm32h7-timer-trigger"; 679 reg = <2>; 680 status = "disabled"; 681 }; 682 683 counter { 684 compatible = "st,stm32-timer-counter"; 685 status = "disabled"; 686 }; 687 }; 688 689 timers4: timer@40002000 { 690 #address-cells = <1>; 691 #size-cells = <0>; 692 compatible = "st,stm32-timers"; 693 reg = <0x40002000 0x400>; 694 clocks = <&rcc TIM4_K>; 695 clock-names = "int"; 696 dmas = <&dmamux1 29 0x400 0x1>, 697 <&dmamux1 30 0x400 0x1>, 698 <&dmamux1 31 0x400 0x1>, 699 <&dmamux1 32 0x400 0x1>; 700 dma-names = "ch1", "ch2", "ch3", "ch4"; 701 access-controllers = <&etzpc STM32MP1_ETZPC_TIM4_ID>; 702 status = "disabled"; 703 704 pwm { 705 compatible = "st,stm32-pwm"; 706 #pwm-cells = <3>; 707 status = "disabled"; 708 }; 709 710 timer@3 { 711 compatible = "st,stm32h7-timer-trigger"; 712 reg = <3>; 713 status = "disabled"; 714 }; 715 716 counter { 717 compatible = "st,stm32-timer-counter"; 718 status = "disabled"; 719 }; 720 }; 721 722 timers5: timer@40003000 { 723 #address-cells = <1>; 724 #size-cells = <0>; 725 compatible = "st,stm32-timers"; 726 reg = <0x40003000 0x400>; 727 clocks = <&rcc TIM5_K>; 728 clock-names = "int"; 729 dmas = <&dmamux1 55 0x400 0x1>, 730 <&dmamux1 56 0x400 0x1>, 731 <&dmamux1 57 0x400 0x1>, 732 <&dmamux1 58 0x400 0x1>, 733 <&dmamux1 59 0x400 0x1>, 734 <&dmamux1 60 0x400 0x1>; 735 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 736 access-controllers = <&etzpc STM32MP1_ETZPC_TIM5_ID>; 737 status = "disabled"; 738 739 pwm { 740 compatible = "st,stm32-pwm"; 741 #pwm-cells = <3>; 742 status = "disabled"; 743 }; 744 745 timer@4 { 746 compatible = "st,stm32h7-timer-trigger"; 747 reg = <4>; 748 status = "disabled"; 749 }; 750 751 counter { 752 compatible = "st,stm32-timer-counter"; 753 status = "disabled"; 754 }; 755 }; 756 757 timers6: timer@40004000 { 758 #address-cells = <1>; 759 #size-cells = <0>; 760 compatible = "st,stm32-timers"; 761 reg = <0x40004000 0x400>; 762 clocks = <&rcc TIM6_K>; 763 clock-names = "int"; 764 dmas = <&dmamux1 69 0x400 0x1>; 765 dma-names = "up"; 766 access-controllers = <&etzpc STM32MP1_ETZPC_TIM6_ID>; 767 status = "disabled"; 768 769 timer@5 { 770 compatible = "st,stm32h7-timer-trigger"; 771 reg = <5>; 772 status = "disabled"; 773 }; 774 }; 775 776 timers7: timer@40005000 { 777 #address-cells = <1>; 778 #size-cells = <0>; 779 compatible = "st,stm32-timers"; 780 reg = <0x40005000 0x400>; 781 clocks = <&rcc TIM7_K>; 782 clock-names = "int"; 783 dmas = <&dmamux1 70 0x400 0x1>; 784 dma-names = "up"; 785 access-controllers = <&etzpc STM32MP1_ETZPC_TIM7_ID>; 786 status = "disabled"; 787 788 timer@6 { 789 compatible = "st,stm32h7-timer-trigger"; 790 reg = <6>; 791 status = "disabled"; 792 }; 793 }; 794 795 timers12: timer@40006000 { 796 #address-cells = <1>; 797 #size-cells = <0>; 798 compatible = "st,stm32-timers"; 799 reg = <0x40006000 0x400>; 800 clocks = <&rcc TIM12_K>; 801 clock-names = "int"; 802 access-controllers = <&etzpc STM32MP1_ETZPC_TIM12_ID>; 803 status = "disabled"; 804 805 pwm { 806 compatible = "st,stm32-pwm"; 807 #pwm-cells = <3>; 808 status = "disabled"; 809 }; 810 811 timer@11 { 812 compatible = "st,stm32h7-timer-trigger"; 813 reg = <11>; 814 status = "disabled"; 815 }; 816 }; 817 818 timers13: timer@40007000 { 819 #address-cells = <1>; 820 #size-cells = <0>; 821 compatible = "st,stm32-timers"; 822 reg = <0x40007000 0x400>; 823 clocks = <&rcc TIM13_K>; 824 clock-names = "int"; 825 access-controllers = <&etzpc STM32MP1_ETZPC_TIM13_ID>; 826 status = "disabled"; 827 828 pwm { 829 compatible = "st,stm32-pwm"; 830 #pwm-cells = <3>; 831 status = "disabled"; 832 }; 833 834 timer@12 { 835 compatible = "st,stm32h7-timer-trigger"; 836 reg = <12>; 837 status = "disabled"; 838 }; 839 }; 840 841 timers14: timer@40008000 { 842 #address-cells = <1>; 843 #size-cells = <0>; 844 compatible = "st,stm32-timers"; 845 reg = <0x40008000 0x400>; 846 clocks = <&rcc TIM14_K>; 847 clock-names = "int"; 848 access-controllers = <&etzpc STM32MP1_ETZPC_TIM14_ID>; 849 status = "disabled"; 850 851 pwm { 852 compatible = "st,stm32-pwm"; 853 #pwm-cells = <3>; 854 status = "disabled"; 855 }; 856 857 timer@13 { 858 compatible = "st,stm32h7-timer-trigger"; 859 reg = <13>; 860 status = "disabled"; 861 }; 862 }; 863 864 lptimer1: timer@40009000 { 865 #address-cells = <1>; 866 #size-cells = <0>; 867 compatible = "st,stm32-lptimer"; 868 reg = <0x40009000 0x400>; 869 interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; 870 clocks = <&rcc LPTIM1_K>; 871 clock-names = "mux"; 872 wakeup-source; 873 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM1_ID>; 874 status = "disabled"; 875 876 pwm { 877 compatible = "st,stm32-pwm-lp"; 878 #pwm-cells = <3>; 879 status = "disabled"; 880 }; 881 882 trigger@0 { 883 compatible = "st,stm32-lptimer-trigger"; 884 reg = <0>; 885 status = "disabled"; 886 }; 887 888 counter { 889 compatible = "st,stm32-lptimer-counter"; 890 status = "disabled"; 891 }; 892 }; 893 894 spi2: spi@4000b000 { 895 #address-cells = <1>; 896 #size-cells = <0>; 897 compatible = "st,stm32h7-spi"; 898 reg = <0x4000b000 0x400>; 899 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 900 clocks = <&rcc SPI2_K>; 901 resets = <&rcc SPI2_R>; 902 dmas = <&dmamux1 39 0x400 0x05>, 903 <&dmamux1 40 0x400 0x05>; 904 dma-names = "rx", "tx"; 905 access-controllers = <&etzpc STM32MP1_ETZPC_SPI2_ID>; 906 status = "disabled"; 907 }; 908 909 i2s2: audio-controller@4000b000 { 910 compatible = "st,stm32h7-i2s"; 911 #sound-dai-cells = <0>; 912 reg = <0x4000b000 0x400>; 913 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 914 dmas = <&dmamux1 39 0x400 0x01>, 915 <&dmamux1 40 0x400 0x01>; 916 dma-names = "rx", "tx"; 917 access-controllers = <&etzpc STM32MP1_ETZPC_SPI2_ID>; 918 status = "disabled"; 919 }; 920 921 spi3: spi@4000c000 { 922 #address-cells = <1>; 923 #size-cells = <0>; 924 compatible = "st,stm32h7-spi"; 925 reg = <0x4000c000 0x400>; 926 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 927 clocks = <&rcc SPI3_K>; 928 resets = <&rcc SPI3_R>; 929 dmas = <&dmamux1 61 0x400 0x05>, 930 <&dmamux1 62 0x400 0x05>; 931 dma-names = "rx", "tx"; 932 access-controllers = <&etzpc STM32MP1_ETZPC_SPI3_ID>; 933 status = "disabled"; 934 }; 935 936 i2s3: audio-controller@4000c000 { 937 compatible = "st,stm32h7-i2s"; 938 #sound-dai-cells = <0>; 939 reg = <0x4000c000 0x400>; 940 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 941 dmas = <&dmamux1 61 0x400 0x01>, 942 <&dmamux1 62 0x400 0x01>; 943 dma-names = "rx", "tx"; 944 access-controllers = <&etzpc STM32MP1_ETZPC_SPI3_ID>; 945 status = "disabled"; 946 }; 947 948 spdifrx: audio-controller@4000d000 { 949 compatible = "st,stm32h7-spdifrx"; 950 #sound-dai-cells = <0>; 951 reg = <0x4000d000 0x400>; 952 clocks = <&rcc SPDIF_K>; 953 clock-names = "kclk"; 954 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 955 dmas = <&dmamux1 93 0x400 0x01>, 956 <&dmamux1 94 0x400 0x01>; 957 dma-names = "rx", "rx-ctrl"; 958 access-controllers = <&etzpc STM32MP1_ETZPC_SPDIFRX_ID>; 959 status = "disabled"; 960 }; 961 962 usart2: serial@4000e000 { 963 compatible = "st,stm32h7-uart"; 964 reg = <0x4000e000 0x400>; 965 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; 966 clocks = <&rcc USART2_K>; 967 wakeup-source; 968 dmas = <&dmamux1 43 0x400 0x15>, 969 <&dmamux1 44 0x400 0x11>; 970 dma-names = "rx", "tx"; 971 access-controllers = <&etzpc STM32MP1_ETZPC_USART2_ID>; 972 status = "disabled"; 973 }; 974 975 usart3: serial@4000f000 { 976 compatible = "st,stm32h7-uart"; 977 reg = <0x4000f000 0x400>; 978 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; 979 clocks = <&rcc USART3_K>; 980 wakeup-source; 981 dmas = <&dmamux1 45 0x400 0x15>, 982 <&dmamux1 46 0x400 0x11>; 983 dma-names = "rx", "tx"; 984 access-controllers = <&etzpc STM32MP1_ETZPC_USART3_ID>; 985 status = "disabled"; 986 }; 987 988 uart4: serial@40010000 { 989 compatible = "st,stm32h7-uart"; 990 reg = <0x40010000 0x400>; 991 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; 992 clocks = <&rcc UART4_K>; 993 wakeup-source; 994 dmas = <&dmamux1 63 0x400 0x15>, 995 <&dmamux1 64 0x400 0x11>; 996 dma-names = "rx", "tx"; 997 access-controllers = <&etzpc STM32MP1_ETZPC_UART4_ID>; 998 status = "disabled"; 999 }; 1000 1001 uart5: serial@40011000 { 1002 compatible = "st,stm32h7-uart"; 1003 reg = <0x40011000 0x400>; 1004 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; 1005 clocks = <&rcc UART5_K>; 1006 wakeup-source; 1007 dmas = <&dmamux1 65 0x400 0x15>, 1008 <&dmamux1 66 0x400 0x11>; 1009 dma-names = "rx", "tx"; 1010 access-controllers = <&etzpc STM32MP1_ETZPC_UART5_ID>; 1011 status = "disabled"; 1012 }; 1013 1014 i2c1: i2c@40012000 { 1015 compatible = "st,stm32mp15-i2c"; 1016 reg = <0x40012000 0x400>; 1017 interrupt-names = "event", "error"; 1018 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1019 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1020 clocks = <&rcc I2C1_K>; 1021 resets = <&rcc I2C1_R>; 1022 #address-cells = <1>; 1023 #size-cells = <0>; 1024 st,syscfg-fmp = <&syscfg 0x4 0x1>; 1025 wakeup-source; 1026 i2c-analog-filter; 1027 access-controllers = <&etzpc STM32MP1_ETZPC_I2C1_ID>; 1028 status = "disabled"; 1029 }; 1030 1031 i2c2: i2c@40013000 { 1032 compatible = "st,stm32mp15-i2c"; 1033 reg = <0x40013000 0x400>; 1034 interrupt-names = "event", "error"; 1035 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 1036 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1037 clocks = <&rcc I2C2_K>; 1038 resets = <&rcc I2C2_R>; 1039 #address-cells = <1>; 1040 #size-cells = <0>; 1041 st,syscfg-fmp = <&syscfg 0x4 0x2>; 1042 wakeup-source; 1043 i2c-analog-filter; 1044 access-controllers = <&etzpc STM32MP1_ETZPC_I2C2_ID>; 1045 status = "disabled"; 1046 }; 1047 1048 i2c3: i2c@40014000 { 1049 compatible = "st,stm32mp15-i2c"; 1050 reg = <0x40014000 0x400>; 1051 interrupt-names = "event", "error"; 1052 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 1053 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1054 clocks = <&rcc I2C3_K>; 1055 resets = <&rcc I2C3_R>; 1056 #address-cells = <1>; 1057 #size-cells = <0>; 1058 st,syscfg-fmp = <&syscfg 0x4 0x4>; 1059 wakeup-source; 1060 i2c-analog-filter; 1061 access-controllers = <&etzpc STM32MP1_ETZPC_I2C3_ID>; 1062 status = "disabled"; 1063 }; 1064 1065 i2c5: i2c@40015000 { 1066 compatible = "st,stm32mp15-i2c"; 1067 reg = <0x40015000 0x400>; 1068 interrupt-names = "event", "error"; 1069 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1070 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1071 clocks = <&rcc I2C5_K>; 1072 resets = <&rcc I2C5_R>; 1073 #address-cells = <1>; 1074 #size-cells = <0>; 1075 st,syscfg-fmp = <&syscfg 0x4 0x10>; 1076 wakeup-source; 1077 i2c-analog-filter; 1078 access-controllers = <&etzpc STM32MP1_ETZPC_I2C5_ID>; 1079 status = "disabled"; 1080 }; 1081 1082 cec: cec@40016000 { 1083 compatible = "st,stm32-cec"; 1084 reg = <0x40016000 0x400>; 1085 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1086 clocks = <&rcc CEC_K>, <&rcc CEC>; 1087 clock-names = "cec", "hdmi-cec"; 1088 access-controllers = <&etzpc STM32MP1_ETZPC_CEC_ID>; 1089 status = "disabled"; 1090 }; 1091 1092 dac: dac@40017000 { 1093 compatible = "st,stm32h7-dac-core"; 1094 reg = <0x40017000 0x400>; 1095 clocks = <&rcc DAC12>; 1096 clock-names = "pclk"; 1097 #address-cells = <1>; 1098 #size-cells = <0>; 1099 access-controllers = <&etzpc STM32MP1_ETZPC_DAC_ID>; 1100 status = "disabled"; 1101 1102 dac1: dac@1 { 1103 compatible = "st,stm32-dac"; 1104 #io-channel-cells = <1>; 1105 reg = <1>; 1106 status = "disabled"; 1107 }; 1108 1109 dac2: dac@2 { 1110 compatible = "st,stm32-dac"; 1111 #io-channel-cells = <1>; 1112 reg = <2>; 1113 status = "disabled"; 1114 }; 1115 }; 1116 1117 uart7: serial@40018000 { 1118 compatible = "st,stm32h7-uart"; 1119 reg = <0x40018000 0x400>; 1120 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; 1121 clocks = <&rcc UART7_K>; 1122 wakeup-source; 1123 dmas = <&dmamux1 79 0x400 0x15>, 1124 <&dmamux1 80 0x400 0x11>; 1125 dma-names = "rx", "tx"; 1126 access-controllers = <&etzpc STM32MP1_ETZPC_UART7_ID>; 1127 status = "disabled"; 1128 }; 1129 1130 uart8: serial@40019000 { 1131 compatible = "st,stm32h7-uart"; 1132 reg = <0x40019000 0x400>; 1133 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; 1134 clocks = <&rcc UART8_K>; 1135 wakeup-source; 1136 dmas = <&dmamux1 81 0x400 0x15>, 1137 <&dmamux1 82 0x400 0x11>; 1138 dma-names = "rx", "tx"; 1139 access-controllers = <&etzpc STM32MP1_ETZPC_UART8_ID>; 1140 status = "disabled"; 1141 }; 1142 1143 timers1: timer@44000000 { 1144 #address-cells = <1>; 1145 #size-cells = <0>; 1146 compatible = "st,stm32-timers"; 1147 reg = <0x44000000 0x400>; 1148 clocks = <&rcc TIM1_K>; 1149 clock-names = "int"; 1150 dmas = <&dmamux1 11 0x400 0x1>, 1151 <&dmamux1 12 0x400 0x1>, 1152 <&dmamux1 13 0x400 0x1>, 1153 <&dmamux1 14 0x400 0x1>, 1154 <&dmamux1 15 0x400 0x1>, 1155 <&dmamux1 16 0x400 0x1>, 1156 <&dmamux1 17 0x400 0x1>; 1157 dma-names = "ch1", "ch2", "ch3", "ch4", 1158 "up", "trig", "com"; 1159 access-controllers = <&etzpc STM32MP1_ETZPC_TIM1_ID>; 1160 status = "disabled"; 1161 1162 pwm { 1163 compatible = "st,stm32-pwm"; 1164 #pwm-cells = <3>; 1165 status = "disabled"; 1166 }; 1167 1168 timer@0 { 1169 compatible = "st,stm32h7-timer-trigger"; 1170 reg = <0>; 1171 status = "disabled"; 1172 }; 1173 1174 counter { 1175 compatible = "st,stm32-timer-counter"; 1176 status = "disabled"; 1177 }; 1178 }; 1179 1180 timers8: timer@44001000 { 1181 #address-cells = <1>; 1182 #size-cells = <0>; 1183 compatible = "st,stm32-timers"; 1184 reg = <0x44001000 0x400>; 1185 clocks = <&rcc TIM8_K>; 1186 clock-names = "int"; 1187 dmas = <&dmamux1 47 0x400 0x1>, 1188 <&dmamux1 48 0x400 0x1>, 1189 <&dmamux1 49 0x400 0x1>, 1190 <&dmamux1 50 0x400 0x1>, 1191 <&dmamux1 51 0x400 0x1>, 1192 <&dmamux1 52 0x400 0x1>, 1193 <&dmamux1 53 0x400 0x1>; 1194 dma-names = "ch1", "ch2", "ch3", "ch4", 1195 "up", "trig", "com"; 1196 access-controllers = <&etzpc STM32MP1_ETZPC_TIM8_ID>; 1197 status = "disabled"; 1198 1199 pwm { 1200 compatible = "st,stm32-pwm"; 1201 #pwm-cells = <3>; 1202 status = "disabled"; 1203 }; 1204 1205 timer@7 { 1206 compatible = "st,stm32h7-timer-trigger"; 1207 reg = <7>; 1208 status = "disabled"; 1209 }; 1210 1211 counter { 1212 compatible = "st,stm32-timer-counter"; 1213 status = "disabled"; 1214 }; 1215 }; 1216 1217 usart6: serial@44003000 { 1218 compatible = "st,stm32h7-uart"; 1219 reg = <0x44003000 0x400>; 1220 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; 1221 clocks = <&rcc USART6_K>; 1222 wakeup-source; 1223 dmas = <&dmamux1 71 0x400 0x15>, 1224 <&dmamux1 72 0x400 0x11>; 1225 dma-names = "rx", "tx"; 1226 access-controllers = <&etzpc STM32MP1_ETZPC_USART6_ID>; 1227 status = "disabled"; 1228 }; 1229 1230 spi1: spi@44004000 { 1231 #address-cells = <1>; 1232 #size-cells = <0>; 1233 compatible = "st,stm32h7-spi"; 1234 reg = <0x44004000 0x400>; 1235 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1236 clocks = <&rcc SPI1_K>; 1237 resets = <&rcc SPI1_R>; 1238 dmas = <&dmamux1 37 0x400 0x05>, 1239 <&dmamux1 38 0x400 0x05>; 1240 dma-names = "rx", "tx"; 1241 access-controllers = <&etzpc STM32MP1_ETZPC_SPI1_ID>; 1242 status = "disabled"; 1243 }; 1244 1245 i2s1: audio-controller@44004000 { 1246 compatible = "st,stm32h7-i2s"; 1247 #sound-dai-cells = <0>; 1248 reg = <0x44004000 0x400>; 1249 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1250 dmas = <&dmamux1 37 0x400 0x01>, 1251 <&dmamux1 38 0x400 0x01>; 1252 dma-names = "rx", "tx"; 1253 access-controllers = <&etzpc STM32MP1_ETZPC_SPI1_ID>; 1254 status = "disabled"; 1255 }; 1256 1257 spi4: spi@44005000 { 1258 #address-cells = <1>; 1259 #size-cells = <0>; 1260 compatible = "st,stm32h7-spi"; 1261 reg = <0x44005000 0x400>; 1262 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1263 clocks = <&rcc SPI4_K>; 1264 resets = <&rcc SPI4_R>; 1265 dmas = <&dmamux1 83 0x400 0x05>, 1266 <&dmamux1 84 0x400 0x05>; 1267 dma-names = "rx", "tx"; 1268 access-controllers = <&etzpc STM32MP1_ETZPC_SPI4_ID>; 1269 status = "disabled"; 1270 }; 1271 1272 timers15: timer@44006000 { 1273 #address-cells = <1>; 1274 #size-cells = <0>; 1275 compatible = "st,stm32-timers"; 1276 reg = <0x44006000 0x400>; 1277 clocks = <&rcc TIM15_K>; 1278 clock-names = "int"; 1279 dmas = <&dmamux1 105 0x400 0x1>, 1280 <&dmamux1 106 0x400 0x1>, 1281 <&dmamux1 107 0x400 0x1>, 1282 <&dmamux1 108 0x400 0x1>; 1283 dma-names = "ch1", "up", "trig", "com"; 1284 access-controllers = <&etzpc STM32MP1_ETZPC_TIM15_ID>; 1285 status = "disabled"; 1286 1287 pwm { 1288 compatible = "st,stm32-pwm"; 1289 #pwm-cells = <3>; 1290 status = "disabled"; 1291 }; 1292 1293 timer@14 { 1294 compatible = "st,stm32h7-timer-trigger"; 1295 reg = <14>; 1296 status = "disabled"; 1297 }; 1298 }; 1299 1300 timers16: timer@44007000 { 1301 #address-cells = <1>; 1302 #size-cells = <0>; 1303 compatible = "st,stm32-timers"; 1304 reg = <0x44007000 0x400>; 1305 clocks = <&rcc TIM16_K>; 1306 clock-names = "int"; 1307 dmas = <&dmamux1 109 0x400 0x1>, 1308 <&dmamux1 110 0x400 0x1>; 1309 dma-names = "ch1", "up"; 1310 access-controllers = <&etzpc STM32MP1_ETZPC_TIM16_ID>; 1311 status = "disabled"; 1312 1313 pwm { 1314 compatible = "st,stm32-pwm"; 1315 #pwm-cells = <3>; 1316 status = "disabled"; 1317 }; 1318 timer@15 { 1319 compatible = "st,stm32h7-timer-trigger"; 1320 reg = <15>; 1321 status = "disabled"; 1322 }; 1323 }; 1324 1325 timers17: timer@44008000 { 1326 #address-cells = <1>; 1327 #size-cells = <0>; 1328 compatible = "st,stm32-timers"; 1329 reg = <0x44008000 0x400>; 1330 clocks = <&rcc TIM17_K>; 1331 clock-names = "int"; 1332 dmas = <&dmamux1 111 0x400 0x1>, 1333 <&dmamux1 112 0x400 0x1>; 1334 dma-names = "ch1", "up"; 1335 access-controllers = <&etzpc STM32MP1_ETZPC_TIM17_ID>; 1336 status = "disabled"; 1337 1338 pwm { 1339 compatible = "st,stm32-pwm"; 1340 #pwm-cells = <3>; 1341 status = "disabled"; 1342 }; 1343 1344 timer@16 { 1345 compatible = "st,stm32h7-timer-trigger"; 1346 reg = <16>; 1347 status = "disabled"; 1348 }; 1349 }; 1350 1351 spi5: spi@44009000 { 1352 #address-cells = <1>; 1353 #size-cells = <0>; 1354 compatible = "st,stm32h7-spi"; 1355 reg = <0x44009000 0x400>; 1356 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1357 clocks = <&rcc SPI5_K>; 1358 resets = <&rcc SPI5_R>; 1359 dmas = <&dmamux1 85 0x400 0x05>, 1360 <&dmamux1 86 0x400 0x05>; 1361 dma-names = "rx", "tx"; 1362 access-controllers = <&etzpc STM32MP1_ETZPC_SPI5_ID>; 1363 status = "disabled"; 1364 }; 1365 1366 sai1: sai@4400a000 { 1367 compatible = "st,stm32h7-sai"; 1368 #address-cells = <1>; 1369 #size-cells = <1>; 1370 ranges = <0 0x4400a000 0x400>; 1371 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; 1372 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1373 resets = <&rcc SAI1_R>; 1374 access-controllers = <&etzpc STM32MP1_ETZPC_SAI1_ID>; 1375 status = "disabled"; 1376 1377 sai1a: audio-controller@4400a004 { 1378 #sound-dai-cells = <0>; 1379 1380 compatible = "st,stm32-sai-sub-a"; 1381 reg = <0x4 0x20>; 1382 clocks = <&rcc SAI1_K>; 1383 clock-names = "sai_ck"; 1384 dmas = <&dmamux1 87 0x400 0x01>; 1385 status = "disabled"; 1386 }; 1387 1388 sai1b: audio-controller@4400a024 { 1389 #sound-dai-cells = <0>; 1390 compatible = "st,stm32-sai-sub-b"; 1391 reg = <0x24 0x20>; 1392 clocks = <&rcc SAI1_K>; 1393 clock-names = "sai_ck"; 1394 dmas = <&dmamux1 88 0x400 0x01>; 1395 status = "disabled"; 1396 }; 1397 }; 1398 1399 sai2: sai@4400b000 { 1400 compatible = "st,stm32h7-sai"; 1401 #address-cells = <1>; 1402 #size-cells = <1>; 1403 ranges = <0 0x4400b000 0x400>; 1404 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; 1405 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1406 resets = <&rcc SAI2_R>; 1407 access-controllers = <&etzpc STM32MP1_ETZPC_SAI2_ID>; 1408 status = "disabled"; 1409 1410 sai2a: audio-controller@4400b004 { 1411 #sound-dai-cells = <0>; 1412 compatible = "st,stm32-sai-sub-a"; 1413 reg = <0x4 0x20>; 1414 clocks = <&rcc SAI2_K>; 1415 clock-names = "sai_ck"; 1416 dmas = <&dmamux1 89 0x400 0x01>; 1417 status = "disabled"; 1418 }; 1419 1420 sai2b: audio-controller@4400b024 { 1421 #sound-dai-cells = <0>; 1422 compatible = "st,stm32-sai-sub-b"; 1423 reg = <0x24 0x20>; 1424 clocks = <&rcc SAI2_K>; 1425 clock-names = "sai_ck"; 1426 dmas = <&dmamux1 90 0x400 0x01>; 1427 status = "disabled"; 1428 }; 1429 }; 1430 1431 sai3: sai@4400c000 { 1432 compatible = "st,stm32h7-sai"; 1433 #address-cells = <1>; 1434 #size-cells = <1>; 1435 ranges = <0 0x4400c000 0x400>; 1436 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; 1437 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1438 resets = <&rcc SAI3_R>; 1439 access-controllers = <&etzpc STM32MP1_ETZPC_SAI3_ID>; 1440 status = "disabled"; 1441 1442 sai3a: audio-controller@4400c004 { 1443 #sound-dai-cells = <0>; 1444 compatible = "st,stm32-sai-sub-a"; 1445 reg = <0x04 0x20>; 1446 clocks = <&rcc SAI3_K>; 1447 clock-names = "sai_ck"; 1448 dmas = <&dmamux1 113 0x400 0x01>; 1449 status = "disabled"; 1450 }; 1451 1452 sai3b: audio-controller@4400c024 { 1453 #sound-dai-cells = <0>; 1454 compatible = "st,stm32-sai-sub-b"; 1455 reg = <0x24 0x20>; 1456 clocks = <&rcc SAI3_K>; 1457 clock-names = "sai_ck"; 1458 dmas = <&dmamux1 114 0x400 0x01>; 1459 status = "disabled"; 1460 }; 1461 }; 1462 1463 dfsdm: dfsdm@4400d000 { 1464 compatible = "st,stm32mp1-dfsdm"; 1465 reg = <0x4400d000 0x800>; 1466 clocks = <&rcc DFSDM_K>; 1467 clock-names = "dfsdm"; 1468 #address-cells = <1>; 1469 #size-cells = <0>; 1470 access-controllers = <&etzpc STM32MP1_ETZPC_DFSDM_ID>; 1471 status = "disabled"; 1472 1473 dfsdm0: filter@0 { 1474 compatible = "st,stm32-dfsdm-adc"; 1475 #io-channel-cells = <1>; 1476 reg = <0>; 1477 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 1478 dmas = <&dmamux1 101 0x400 0x01>; 1479 dma-names = "rx"; 1480 status = "disabled"; 1481 }; 1482 1483 dfsdm1: filter@1 { 1484 compatible = "st,stm32-dfsdm-adc"; 1485 #io-channel-cells = <1>; 1486 reg = <1>; 1487 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1488 dmas = <&dmamux1 102 0x400 0x01>; 1489 dma-names = "rx"; 1490 status = "disabled"; 1491 }; 1492 1493 dfsdm2: filter@2 { 1494 compatible = "st,stm32-dfsdm-adc"; 1495 #io-channel-cells = <1>; 1496 reg = <2>; 1497 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1498 dmas = <&dmamux1 103 0x400 0x01>; 1499 dma-names = "rx"; 1500 status = "disabled"; 1501 }; 1502 1503 dfsdm3: filter@3 { 1504 compatible = "st,stm32-dfsdm-adc"; 1505 #io-channel-cells = <1>; 1506 reg = <3>; 1507 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1508 dmas = <&dmamux1 104 0x400 0x01>; 1509 dma-names = "rx"; 1510 status = "disabled"; 1511 }; 1512 1513 dfsdm4: filter@4 { 1514 compatible = "st,stm32-dfsdm-adc"; 1515 #io-channel-cells = <1>; 1516 reg = <4>; 1517 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1518 dmas = <&dmamux1 91 0x400 0x01>; 1519 dma-names = "rx"; 1520 status = "disabled"; 1521 }; 1522 1523 dfsdm5: filter@5 { 1524 compatible = "st,stm32-dfsdm-adc"; 1525 #io-channel-cells = <1>; 1526 reg = <5>; 1527 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1528 dmas = <&dmamux1 92 0x400 0x01>; 1529 dma-names = "rx"; 1530 status = "disabled"; 1531 }; 1532 }; 1533 1534 dma1: dma-controller@48000000 { 1535 compatible = "st,stm32-dma"; 1536 reg = <0x48000000 0x400>; 1537 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1540 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1541 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1542 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1543 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1544 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1545 clocks = <&rcc DMA1>; 1546 resets = <&rcc DMA1_R>; 1547 #dma-cells = <4>; 1548 st,mem2mem; 1549 dma-requests = <8>; 1550 access-controllers = <&etzpc STM32MP1_ETZPC_DMA1_ID>; 1551 status = "disabled"; 1552 }; 1553 1554 dma2: dma-controller@48001000 { 1555 compatible = "st,stm32-dma"; 1556 reg = <0x48001000 0x400>; 1557 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1558 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1559 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1560 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1564 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1565 clocks = <&rcc DMA2>; 1566 resets = <&rcc DMA2_R>; 1567 #dma-cells = <4>; 1568 st,mem2mem; 1569 dma-requests = <8>; 1570 access-controllers = <&etzpc STM32MP1_ETZPC_DMA2_ID>; 1571 status = "disabled"; 1572 }; 1573 1574 dmamux1: dma-router@48002000 { 1575 compatible = "st,stm32h7-dmamux"; 1576 reg = <0x48002000 0x40>; 1577 #dma-cells = <3>; 1578 dma-requests = <128>; 1579 dma-masters = <&dma1 &dma2>; 1580 dma-channels = <16>; 1581 clocks = <&rcc DMAMUX>; 1582 resets = <&rcc DMAMUX_R>; 1583 access-controllers = <&etzpc STM32MP1_ETZPC_DMAMUX_ID>; 1584 status = "disabled"; 1585 }; 1586 1587 adc: adc@48003000 { 1588 compatible = "st,stm32mp1-adc-core"; 1589 reg = <0x48003000 0x400>; 1590 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1591 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1592 clocks = <&rcc ADC12>, <&rcc ADC12_K>; 1593 clock-names = "bus", "adc"; 1594 interrupt-controller; 1595 st,syscfg = <&syscfg>; 1596 #interrupt-cells = <1>; 1597 #address-cells = <1>; 1598 #size-cells = <0>; 1599 access-controllers = <&etzpc STM32MP1_ETZPC_ADC_ID>; 1600 status = "disabled"; 1601 1602 adc1: adc@0 { 1603 compatible = "st,stm32mp1-adc"; 1604 #io-channel-cells = <1>; 1605 reg = <0x0>; 1606 interrupt-parent = <&adc>; 1607 interrupts = <0>; 1608 dmas = <&dmamux1 9 0x400 0x01>; 1609 dma-names = "rx"; 1610 status = "disabled"; 1611 }; 1612 1613 adc2: adc@100 { 1614 compatible = "st,stm32mp1-adc"; 1615 #io-channel-cells = <1>; 1616 reg = <0x100>; 1617 interrupt-parent = <&adc>; 1618 interrupts = <1>; 1619 dmas = <&dmamux1 10 0x400 0x01>; 1620 dma-names = "rx"; 1621 status = "disabled"; 1622 }; 1623 }; 1624 1625 sdmmc3: mmc@48004000 { 1626 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 1627 arm,primecell-periphid = <0x00253180>; 1628 reg = <0x48004000 0x400>; 1629 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1630 interrupt-names = "cmd_irq"; 1631 clocks = <&rcc SDMMC3_K>; 1632 clock-names = "apb_pclk"; 1633 resets = <&rcc SDMMC3_R>; 1634 cap-sd-highspeed; 1635 cap-mmc-highspeed; 1636 max-frequency = <120000000>; 1637 access-controllers = <&etzpc STM32MP1_ETZPC_SDMMC3_ID>; 1638 status = "disabled"; 1639 }; 1640 1641 usbotg_hs: usb-otg@49000000 { 1642 compatible = "st,stm32mp15-hsotg", "snps,dwc2"; 1643 reg = <0x49000000 0x10000>; 1644 clocks = <&rcc USBO_K>; 1645 clock-names = "otg"; 1646 resets = <&rcc USBO_R>; 1647 reset-names = "dwc2"; 1648 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1649 g-rx-fifo-size = <512>; 1650 g-np-tx-fifo-size = <32>; 1651 g-tx-fifo-size = <256 16 16 16 16 16 16 16>; 1652 dr_mode = "otg"; 1653 otg-rev = <0x200>; 1654 usb33d-supply = <&usb33>; 1655 access-controllers = <&etzpc STM32MP1_ETZPC_OTG_ID>; 1656 status = "disabled"; 1657 }; 1658 1659 dcmi: dcmi@4c006000 { 1660 compatible = "st,stm32-dcmi"; 1661 reg = <0x4c006000 0x400>; 1662 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1663 resets = <&rcc CAMITF_R>; 1664 clocks = <&rcc DCMI>; 1665 clock-names = "mclk"; 1666 dmas = <&dmamux1 75 0x400 0x01>; 1667 dma-names = "tx"; 1668 access-controllers = <&etzpc STM32MP1_ETZPC_DCMI_ID>; 1669 status = "disabled"; 1670 }; 1671 1672 lptimer2: timer@50021000 { 1673 #address-cells = <1>; 1674 #size-cells = <0>; 1675 compatible = "st,stm32-lptimer"; 1676 reg = <0x50021000 0x400>; 1677 interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; 1678 clocks = <&rcc LPTIM2_K>; 1679 clock-names = "mux"; 1680 wakeup-source; 1681 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM2_ID>; 1682 status = "disabled"; 1683 1684 pwm { 1685 compatible = "st,stm32-pwm-lp"; 1686 #pwm-cells = <3>; 1687 status = "disabled"; 1688 }; 1689 1690 trigger@1 { 1691 compatible = "st,stm32-lptimer-trigger"; 1692 reg = <1>; 1693 status = "disabled"; 1694 }; 1695 1696 counter { 1697 compatible = "st,stm32-lptimer-counter"; 1698 status = "disabled"; 1699 }; 1700 }; 1701 1702 lptimer3: timer@50022000 { 1703 #address-cells = <1>; 1704 #size-cells = <0>; 1705 compatible = "st,stm32-lptimer"; 1706 reg = <0x50022000 0x400>; 1707 interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; 1708 clocks = <&rcc LPTIM3_K>; 1709 clock-names = "mux"; 1710 wakeup-source; 1711 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM3_ID>; 1712 status = "disabled"; 1713 1714 pwm { 1715 compatible = "st,stm32-pwm-lp"; 1716 #pwm-cells = <3>; 1717 status = "disabled"; 1718 }; 1719 1720 trigger@2 { 1721 compatible = "st,stm32-lptimer-trigger"; 1722 reg = <2>; 1723 status = "disabled"; 1724 }; 1725 }; 1726 1727 lptimer4: timer@50023000 { 1728 compatible = "st,stm32-lptimer"; 1729 reg = <0x50023000 0x400>; 1730 interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; 1731 clocks = <&rcc LPTIM4_K>; 1732 clock-names = "mux"; 1733 wakeup-source; 1734 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM4_ID>; 1735 status = "disabled"; 1736 1737 pwm { 1738 compatible = "st,stm32-pwm-lp"; 1739 #pwm-cells = <3>; 1740 status = "disabled"; 1741 }; 1742 }; 1743 1744 lptimer5: timer@50024000 { 1745 compatible = "st,stm32-lptimer"; 1746 reg = <0x50024000 0x400>; 1747 interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; 1748 clocks = <&rcc LPTIM5_K>; 1749 clock-names = "mux"; 1750 wakeup-source; 1751 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM5_ID>; 1752 status = "disabled"; 1753 1754 pwm { 1755 compatible = "st,stm32-pwm-lp"; 1756 #pwm-cells = <3>; 1757 status = "disabled"; 1758 }; 1759 }; 1760 1761 vrefbuf: vrefbuf@50025000 { 1762 compatible = "st,stm32-vrefbuf"; 1763 reg = <0x50025000 0x8>; 1764 regulator-min-microvolt = <1500000>; 1765 regulator-max-microvolt = <2500000>; 1766 clocks = <&rcc VREF>; 1767 access-controllers = <&etzpc STM32MP1_ETZPC_VREFBUF_ID>; 1768 status = "disabled"; 1769 }; 1770 1771 sai4: sai@50027000 { 1772 compatible = "st,stm32h7-sai"; 1773 #address-cells = <1>; 1774 #size-cells = <1>; 1775 ranges = <0 0x50027000 0x400>; 1776 reg = <0x50027000 0x4>, <0x500273f0 0x10>; 1777 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1778 resets = <&rcc SAI4_R>; 1779 access-controllers = <&etzpc STM32MP1_ETZPC_SAI4_ID>; 1780 status = "disabled"; 1781 1782 sai4a: audio-controller@50027004 { 1783 #sound-dai-cells = <0>; 1784 compatible = "st,stm32-sai-sub-a"; 1785 reg = <0x04 0x20>; 1786 clocks = <&rcc SAI4_K>; 1787 clock-names = "sai_ck"; 1788 dmas = <&dmamux1 99 0x400 0x01>; 1789 status = "disabled"; 1790 }; 1791 1792 sai4b: audio-controller@50027024 { 1793 #sound-dai-cells = <0>; 1794 compatible = "st,stm32-sai-sub-b"; 1795 reg = <0x24 0x20>; 1796 clocks = <&rcc SAI4_K>; 1797 clock-names = "sai_ck"; 1798 dmas = <&dmamux1 100 0x400 0x01>; 1799 status = "disabled"; 1800 }; 1801 }; 1802 1803 hash1: hash@54002000 { 1804 compatible = "st,stm32f756-hash"; 1805 reg = <0x54002000 0x400>; 1806 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1807 clocks = <&rcc HASH1>; 1808 resets = <&rcc HASH1_R>; 1809 dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; 1810 dma-names = "in"; 1811 dma-maxburst = <2>; 1812 access-controllers = <&etzpc STM32MP1_ETZPC_HASH1_ID>; 1813 status = "disabled"; 1814 }; 1815 1816 rng1: rng@54003000 { 1817 compatible = "st,stm32-rng"; 1818 reg = <0x54003000 0x400>; 1819 clocks = <&rcc RNG1_K>; 1820 resets = <&rcc RNG1_R>; 1821 access-controllers = <&etzpc STM32MP1_ETZPC_RNG1_ID>; 1822 status = "disabled"; 1823 }; 1824 1825 fmc: memory-controller@58002000 { 1826 #address-cells = <2>; 1827 #size-cells = <1>; 1828 compatible = "st,stm32mp1-fmc2-ebi"; 1829 reg = <0x58002000 0x1000>; 1830 clocks = <&rcc FMC_K>; 1831 resets = <&rcc FMC_R>; 1832 access-controllers = <&etzpc STM32MP1_ETZPC_FMC_ID>; 1833 status = "disabled"; 1834 1835 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 1836 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 1837 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 1838 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 1839 <4 0 0x80000000 0x10000000>; /* NAND */ 1840 1841 nand-controller@4,0 { 1842 #address-cells = <1>; 1843 #size-cells = <0>; 1844 compatible = "st,stm32mp1-fmc2-nfc"; 1845 reg = <4 0x00000000 0x1000>, 1846 <4 0x08010000 0x1000>, 1847 <4 0x08020000 0x1000>, 1848 <4 0x01000000 0x1000>, 1849 <4 0x09010000 0x1000>, 1850 <4 0x09020000 0x1000>; 1851 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1852 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, 1853 <&mdma1 20 0x2 0x12000a08 0x0 0x0>, 1854 <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; 1855 dma-names = "tx", "rx", "ecc"; 1856 status = "disabled"; 1857 }; 1858 }; 1859 1860 qspi: spi@58003000 { 1861 compatible = "st,stm32f469-qspi"; 1862 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; 1863 reg-names = "qspi", "qspi_mm"; 1864 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 1865 dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, 1866 <&mdma1 22 0x2 0x10100008 0x0 0x0>; 1867 dma-names = "tx", "rx"; 1868 clocks = <&rcc QSPI_K>; 1869 resets = <&rcc QSPI_R>; 1870 #address-cells = <1>; 1871 #size-cells = <0>; 1872 access-controllers = <&etzpc STM32MP1_ETZPC_QSPI_ID>; 1873 status = "disabled"; 1874 }; 1875 1876 ethernet0: ethernet@5800a000 { 1877 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; 1878 reg = <0x5800a000 0x2000>; 1879 reg-names = "stmmaceth"; 1880 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1881 interrupt-names = "macirq"; 1882 clock-names = "stmmaceth", 1883 "mac-clk-tx", 1884 "mac-clk-rx", 1885 "eth-ck", 1886 "ptp_ref", 1887 "ethstp"; 1888 clocks = <&rcc ETHMAC>, 1889 <&rcc ETHTX>, 1890 <&rcc ETHRX>, 1891 <&rcc ETHCK_K>, 1892 <&rcc ETHPTP_K>, 1893 <&rcc ETHSTP>; 1894 st,syscon = <&syscfg 0x4>; 1895 snps,mixed-burst; 1896 snps,pbl = <2>; 1897 snps,en-tx-lpi-clockgating; 1898 snps,axi-config = <&stmmac_axi_config_0>; 1899 snps,tso; 1900 access-controllers = <&etzpc STM32MP1_ETZPC_ETH_ID>; 1901 status = "disabled"; 1902 1903 stmmac_axi_config_0: stmmac-axi-config { 1904 snps,wr_osr_lmt = <0x7>; 1905 snps,rd_osr_lmt = <0x7>; 1906 snps,blen = <0 0 0 0 16 8 4>; 1907 }; 1908 }; 1909 1910 usart1: serial@5c000000 { 1911 compatible = "st,stm32h7-uart"; 1912 reg = <0x5c000000 0x400>; 1913 interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; 1914 clocks = <&rcc USART1_K>; 1915 wakeup-source; 1916 access-controllers = <&etzpc STM32MP1_ETZPC_USART1_ID>; 1917 status = "disabled"; 1918 }; 1919 1920 spi6: spi@5c001000 { 1921 #address-cells = <1>; 1922 #size-cells = <0>; 1923 compatible = "st,stm32h7-spi"; 1924 reg = <0x5c001000 0x400>; 1925 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1926 clocks = <&rcc SPI6_K>; 1927 resets = <&rcc SPI6_R>; 1928 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, 1929 <&mdma1 35 0x0 0x40002 0x0 0x0>; 1930 dma-names = "rx", "tx"; 1931 access-controllers = <&etzpc STM32MP1_ETZPC_SPI6_ID>; 1932 status = "disabled"; 1933 }; 1934 1935 i2c4: i2c@5c002000 { 1936 compatible = "st,stm32mp15-i2c"; 1937 reg = <0x5c002000 0x400>; 1938 interrupt-names = "event", "error"; 1939 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1940 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1941 clocks = <&rcc I2C4_K>; 1942 resets = <&rcc I2C4_R>; 1943 #address-cells = <1>; 1944 #size-cells = <0>; 1945 st,syscfg-fmp = <&syscfg 0x4 0x8>; 1946 wakeup-source; 1947 i2c-analog-filter; 1948 access-controllers = <&etzpc STM32MP1_ETZPC_I2C4_ID>; 1949 status = "disabled"; 1950 }; 1951 1952 iwdg1: watchdog@5c003000 { 1953 compatible = "st,stm32mp1-iwdg"; 1954 reg = <0x5C003000 0x400>; 1955 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1956 clocks = <&rcc IWDG1>, <&rcc CK_LSI>; 1957 clock-names = "pclk", "lsi"; 1958 access-controllers = <&etzpc STM32MP1_ETZPC_IWDG1_ID>; 1959 status = "disabled"; 1960 }; 1961 1962 i2c6: i2c@5c009000 { 1963 compatible = "st,stm32mp15-i2c"; 1964 reg = <0x5c009000 0x400>; 1965 interrupt-names = "event", "error"; 1966 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1967 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1968 clocks = <&rcc I2C6_K>; 1969 resets = <&rcc I2C6_R>; 1970 #address-cells = <1>; 1971 #size-cells = <0>; 1972 st,syscfg-fmp = <&syscfg 0x4 0x20>; 1973 wakeup-source; 1974 i2c-analog-filter; 1975 access-controllers = <&etzpc STM32MP1_ETZPC_I2C6_ID>; 1976 status = "disabled"; 1977 }; 1978 }; 1979 }; 1980 1981 mlahb: ahb { 1982 compatible = "st,mlahb", "simple-bus"; 1983 #address-cells = <1>; 1984 #size-cells = <1>; 1985 ranges; 1986 dma-ranges = <0x00000000 0x38000000 0x10000>, 1987 <0x10000000 0x10000000 0x60000>, 1988 <0x30000000 0x30000000 0x60000>; 1989 1990 m4_rproc: m4@10000000 { 1991 compatible = "st,stm32mp1-m4"; 1992 reg = <0x10000000 0x40000>, 1993 <0x30000000 0x40000>, 1994 <0x38000000 0x10000>; 1995 resets = <&rcc MCU_R>, <&rcc MCU_HOLD_BOOT_R>; 1996 reset-names = "mcu_rst", "hold_boot"; 1997 st,syscfg-tz = <&rcc 0x000 0x1>; 1998 st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; 1999 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; 2000 st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; 2001 status = "disabled"; 2002 }; 2003 }; 2004}; 2005