1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2017-2025 - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/stm32mp1-clks.h> 8#include <dt-bindings/reset/stm32mp1-resets.h> 9#include <dt-bindings/firewall/stm32mp15-etzpc.h> 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a7"; 21 clock-frequency = <650000000>; 22 device_type = "cpu"; 23 reg = <0>; 24 }; 25 }; 26 27 arm-pmu { 28 compatible = "arm,cortex-a7-pmu"; 29 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 30 interrupt-affinity = <&cpu0>; 31 interrupt-parent = <&intc>; 32 }; 33 34 psci { 35 compatible = "arm,psci-1.0"; 36 method = "smc"; 37 }; 38 39 intc: interrupt-controller@a0021000 { 40 compatible = "arm,cortex-a7-gic"; 41 #interrupt-cells = <3>; 42 interrupt-controller; 43 reg = <0xa0021000 0x1000>, 44 <0xa0022000 0x2000>; 45 }; 46 47 timer { 48 compatible = "arm,armv7-timer"; 49 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 50 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 51 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 52 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 53 interrupt-parent = <&intc>; 54 }; 55 56 clocks { 57 clk_hse: clk-hse { 58 #clock-cells = <0>; 59 compatible = "fixed-clock"; 60 clock-frequency = <24000000>; 61 }; 62 63 clk_hsi: clk-hsi { 64 #clock-cells = <0>; 65 compatible = "fixed-clock"; 66 clock-frequency = <64000000>; 67 }; 68 69 clk_lse: clk-lse { 70 #clock-cells = <0>; 71 compatible = "fixed-clock"; 72 clock-frequency = <32768>; 73 }; 74 75 clk_lsi: clk-lsi { 76 #clock-cells = <0>; 77 compatible = "fixed-clock"; 78 clock-frequency = <32000>; 79 }; 80 81 clk_csi: clk-csi { 82 #clock-cells = <0>; 83 compatible = "fixed-clock"; 84 clock-frequency = <4000000>; 85 }; 86 }; 87 88 thermal-zones { 89 cpu_thermal: cpu-thermal { 90 polling-delay-passive = <0>; 91 polling-delay = <0>; 92 thermal-sensors = <&dts>; 93 94 trips { 95 cpu_alert1: cpu-alert1 { 96 temperature = <85000>; 97 hysteresis = <0>; 98 type = "passive"; 99 }; 100 101 cpu-crit { 102 temperature = <120000>; 103 hysteresis = <0>; 104 type = "critical"; 105 }; 106 }; 107 108 cooling-maps { 109 }; 110 }; 111 }; 112 113 booster: regulator-booster { 114 compatible = "st,stm32mp1-booster"; 115 st,syscfg = <&syscfg>; 116 status = "disabled"; 117 }; 118 119 soc { 120 compatible = "simple-bus"; 121 #address-cells = <1>; 122 #size-cells = <1>; 123 interrupt-parent = <&intc>; 124 ranges; 125 126 ipcc: mailbox@4c001000 { 127 compatible = "st,stm32mp1-ipcc"; 128 #mbox-cells = <1>; 129 reg = <0x4c001000 0x400>; 130 st,proc-id = <0>; 131 interrupts-extended = 132 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 133 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 134 <&exti 61 1>; 135 interrupt-names = "rx", "tx", "wakeup"; 136 clocks = <&rcc IPCC>; 137 wakeup-source; 138 status = "disabled"; 139 }; 140 141 rcc: rcc@50000000 { 142 compatible = "st,stm32mp1-rcc", "syscon"; 143 reg = <0x50000000 0x1000>; 144 #clock-cells = <1>; 145 #reset-cells = <1>; 146 }; 147 148 pwr_regulators: pwr@50001000 { 149 compatible = "st,stm32mp1,pwr-reg"; 150 reg = <0x50001000 0x10>; 151 152 reg11: reg11 { 153 regulator-name = "reg11"; 154 regulator-min-microvolt = <1100000>; 155 regulator-max-microvolt = <1100000>; 156 }; 157 158 reg18: reg18 { 159 regulator-name = "reg18"; 160 regulator-min-microvolt = <1800000>; 161 regulator-max-microvolt = <1800000>; 162 }; 163 164 usb33: usb33 { 165 regulator-name = "usb33"; 166 regulator-min-microvolt = <3300000>; 167 regulator-max-microvolt = <3300000>; 168 }; 169 }; 170 171 pwr_mcu: pwr_mcu@50001014 { 172 compatible = "st,stm32mp151-pwr-mcu", "syscon"; 173 reg = <0x50001014 0x4>; 174 }; 175 176 exti: interrupt-controller@5000d000 { 177 compatible = "st,stm32mp1-exti"; 178 interrupt-controller; 179 #interrupt-cells = <2>; 180 reg = <0x5000d000 0x400>; 181 interrupts-extended = 182 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 183 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 184 <&intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 185 <&intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 186 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 187 <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 188 <&intc GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 189 <&intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 190 <&intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 191 <&intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 192 <&intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 193 <&intc GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 194 <&intc GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 195 <&intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 196 <&intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 197 <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 198 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 199 <0>, 200 <0>, 201 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 202 <0>, /* EXTI_20 */ 203 <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 204 <&intc GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 205 <&intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 206 <&intc GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 207 <&intc GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 208 <&intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 209 <&intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 210 <&intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 211 <&intc GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 212 <&intc GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 213 <&intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 214 <&intc GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 215 <&intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 216 <0>, 217 <0>, 218 <0>, 219 <0>, 220 <0>, 221 <0>, 222 <0>, /* EXTI_40 */ 223 <0>, 224 <0>, 225 <&intc GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 226 <&intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 227 <0>, 228 <0>, 229 <&intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 230 <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 231 <0>, 232 <&intc GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 233 <0>, 234 <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 235 <&intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 236 <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 237 <0>, 238 <0>, 239 <0>, 240 <0>, 241 <0>, 242 <0>, /* EXTI_60 */ 243 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 244 <0>, 245 <0>, 246 <0>, 247 <&intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 248 <0>, 249 <0>, 250 <&intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 251 <&intc GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 252 <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ 253 <0>, 254 <0>, 255 <&intc GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 256 }; 257 258 syscfg: syscon@50020000 { 259 compatible = "st,stm32mp157-syscfg", "syscon"; 260 reg = <0x50020000 0x400>; 261 clocks = <&rcc SYSCFG>; 262 }; 263 264 dts: thermal@50028000 { 265 compatible = "st,stm32-thermal"; 266 reg = <0x50028000 0x100>; 267 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&rcc TMPSENS>; 269 clock-names = "pclk"; 270 #thermal-sensor-cells = <0>; 271 status = "disabled"; 272 }; 273 274 mdma1: dma-controller@58000000 { 275 compatible = "st,stm32h7-mdma"; 276 reg = <0x58000000 0x1000>; 277 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 278 clocks = <&rcc MDMA>; 279 resets = <&rcc MDMA_R>; 280 #dma-cells = <5>; 281 dma-channels = <32>; 282 dma-requests = <48>; 283 }; 284 285 sdmmc1: mmc@58005000 { 286 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 287 arm,primecell-periphid = <0x00253180>; 288 reg = <0x58005000 0x1000>; 289 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 290 interrupt-names = "cmd_irq"; 291 clocks = <&rcc SDMMC1_K>; 292 clock-names = "apb_pclk"; 293 resets = <&rcc SDMMC1_R>; 294 cap-sd-highspeed; 295 cap-mmc-highspeed; 296 max-frequency = <120000000>; 297 status = "disabled"; 298 }; 299 300 sdmmc2: mmc@58007000 { 301 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 302 arm,primecell-periphid = <0x00253180>; 303 reg = <0x58007000 0x1000>; 304 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 305 interrupt-names = "cmd_irq"; 306 clocks = <&rcc SDMMC2_K>; 307 clock-names = "apb_pclk"; 308 resets = <&rcc SDMMC2_R>; 309 cap-sd-highspeed; 310 cap-mmc-highspeed; 311 max-frequency = <120000000>; 312 status = "disabled"; 313 }; 314 315 crc1: crc@58009000 { 316 compatible = "st,stm32f7-crc"; 317 reg = <0x58009000 0x400>; 318 clocks = <&rcc CRC1>; 319 status = "disabled"; 320 }; 321 322 usbh_ohci: usb@5800c000 { 323 compatible = "generic-ohci"; 324 reg = <0x5800c000 0x1000>; 325 clocks = <&usbphyc>, <&rcc USBH>; 326 resets = <&rcc USBH_R>; 327 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 328 status = "disabled"; 329 }; 330 331 usbh_ehci: usb@5800d000 { 332 compatible = "generic-ehci"; 333 reg = <0x5800d000 0x1000>; 334 clocks = <&usbphyc>, <&rcc USBH>; 335 resets = <&rcc USBH_R>; 336 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 337 companion = <&usbh_ohci>; 338 status = "disabled"; 339 }; 340 341 ltdc: display-controller@5a001000 { 342 compatible = "st,stm32-ltdc"; 343 reg = <0x5a001000 0x400>; 344 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&rcc LTDC_PX>; 347 clock-names = "lcd"; 348 resets = <&rcc LTDC_R>; 349 status = "disabled"; 350 351 port { 352 #address-cells = <1>; 353 #size-cells = <0>; 354 }; 355 }; 356 357 iwdg2: watchdog@5a002000 { 358 compatible = "st,stm32mp1-iwdg"; 359 reg = <0x5a002000 0x400>; 360 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 361 clocks = <&rcc IWDG2>, <&rcc CK_LSI>; 362 clock-names = "pclk", "lsi"; 363 status = "disabled"; 364 }; 365 366 usbphyc: usbphyc@5a006000 { 367 #address-cells = <1>; 368 #size-cells = <0>; 369 #clock-cells = <0>; 370 compatible = "st,stm32mp1-usbphyc"; 371 reg = <0x5a006000 0x1000>; 372 clocks = <&rcc USBPHY_K>; 373 resets = <&rcc USBPHY_R>; 374 vdda1v1-supply = <®11>; 375 vdda1v8-supply = <®18>; 376 status = "disabled"; 377 378 usbphyc_port0: usb-phy@0 { 379 #phy-cells = <0>; 380 reg = <0>; 381 }; 382 383 usbphyc_port1: usb-phy@1 { 384 #phy-cells = <1>; 385 reg = <1>; 386 }; 387 }; 388 389 rtc: rtc@5c004000 { 390 compatible = "st,stm32mp1-rtc"; 391 reg = <0x5c004000 0x400>; 392 clocks = <&rcc RTCAPB>, <&rcc RTC>; 393 clock-names = "pclk", "rtc_ck"; 394 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; 395 status = "disabled"; 396 }; 397 398 bsec: efuse@5c005000 { 399 compatible = "st,stm32mp15-bsec"; 400 reg = <0x5c005000 0x400>; 401 #address-cells = <1>; 402 #size-cells = <1>; 403 404 cfg0_otp: cfg0_otp@0 { 405 reg = <0x0 0x1>; 406 }; 407 part_number_otp: part_number_otp@4 { 408 reg = <0x4 0x1>; 409 }; 410 monotonic_otp: monotonic_otp@10 { 411 reg = <0x10 0x4>; 412 }; 413 nand_otp: nand_otp@24 { 414 reg = <0x24 0x4>; 415 }; 416 uid_otp: uid_otp@34 { 417 reg = <0x34 0xc>; 418 }; 419 package_otp: package_otp@40 { 420 reg = <0x40 0x4>; 421 }; 422 hw2_otp: hw2_otp@48 { 423 reg = <0x48 0x4>; 424 }; 425 ts_cal1: calib@5c { 426 reg = <0x5c 0x2>; 427 }; 428 ts_cal2: calib@5e { 429 reg = <0x5e 0x2>; 430 }; 431 pkh_otp: pkh_otp@60 { 432 reg = <0x60 0x20>; 433 }; 434 ethernet_mac_address: mac@e4 { 435 reg = <0xe4 0x8>; 436 st,non-secure-otp; 437 }; 438 }; 439 440 tamp: tamp@5c00a000 { 441 compatible = "st,stm32-tamp", "syscon", "simple-mfd"; 442 reg = <0x5c00a000 0x400>; 443 clocks = <&rcc RTCAPB>; 444 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 445 st,backup-zones = <10 5 17>; 446 }; 447 448 /* 449 * Break node order to solve dependency probe issue between 450 * pinctrl and exti. 451 */ 452 pinctrl: pinctrl@50002000 { 453 #address-cells = <1>; 454 #size-cells = <1>; 455 compatible = "st,stm32mp157-pinctrl"; 456 ranges = <0 0x50002000 0xa400>; 457 interrupt-parent = <&exti>; 458 st,syscfg = <&exti 0x60 0xff>; 459 pins-are-numbered; 460 461 gpioa: gpio@50002000 { 462 gpio-controller; 463 #gpio-cells = <2>; 464 interrupt-controller; 465 #interrupt-cells = <2>; 466 reg = <0x0 0x400>; 467 clocks = <&rcc GPIOA>; 468 st,bank-name = "GPIOA"; 469 status = "disabled"; 470 }; 471 472 gpiob: gpio@50003000 { 473 gpio-controller; 474 #gpio-cells = <2>; 475 interrupt-controller; 476 #interrupt-cells = <2>; 477 reg = <0x1000 0x400>; 478 clocks = <&rcc GPIOB>; 479 st,bank-name = "GPIOB"; 480 status = "disabled"; 481 }; 482 483 gpioc: gpio@50004000 { 484 gpio-controller; 485 #gpio-cells = <2>; 486 interrupt-controller; 487 #interrupt-cells = <2>; 488 reg = <0x2000 0x400>; 489 clocks = <&rcc GPIOC>; 490 st,bank-name = "GPIOC"; 491 status = "disabled"; 492 }; 493 494 gpiod: gpio@50005000 { 495 gpio-controller; 496 #gpio-cells = <2>; 497 interrupt-controller; 498 #interrupt-cells = <2>; 499 reg = <0x3000 0x400>; 500 clocks = <&rcc GPIOD>; 501 st,bank-name = "GPIOD"; 502 status = "disabled"; 503 }; 504 505 gpioe: gpio@50006000 { 506 gpio-controller; 507 #gpio-cells = <2>; 508 interrupt-controller; 509 #interrupt-cells = <2>; 510 reg = <0x4000 0x400>; 511 clocks = <&rcc GPIOE>; 512 st,bank-name = "GPIOE"; 513 status = "disabled"; 514 }; 515 516 gpiof: gpio@50007000 { 517 gpio-controller; 518 #gpio-cells = <2>; 519 interrupt-controller; 520 #interrupt-cells = <2>; 521 reg = <0x5000 0x400>; 522 clocks = <&rcc GPIOF>; 523 st,bank-name = "GPIOF"; 524 status = "disabled"; 525 }; 526 527 gpiog: gpio@50008000 { 528 gpio-controller; 529 #gpio-cells = <2>; 530 interrupt-controller; 531 #interrupt-cells = <2>; 532 reg = <0x6000 0x400>; 533 clocks = <&rcc GPIOG>; 534 st,bank-name = "GPIOG"; 535 status = "disabled"; 536 }; 537 538 gpioh: gpio@50009000 { 539 gpio-controller; 540 #gpio-cells = <2>; 541 interrupt-controller; 542 #interrupt-cells = <2>; 543 reg = <0x7000 0x400>; 544 clocks = <&rcc GPIOH>; 545 st,bank-name = "GPIOH"; 546 status = "disabled"; 547 }; 548 549 gpioi: gpio@5000a000 { 550 gpio-controller; 551 #gpio-cells = <2>; 552 interrupt-controller; 553 #interrupt-cells = <2>; 554 reg = <0x8000 0x400>; 555 clocks = <&rcc GPIOI>; 556 st,bank-name = "GPIOI"; 557 status = "disabled"; 558 }; 559 560 gpioj: gpio@5000b000 { 561 gpio-controller; 562 #gpio-cells = <2>; 563 interrupt-controller; 564 #interrupt-cells = <2>; 565 reg = <0x9000 0x400>; 566 clocks = <&rcc GPIOJ>; 567 st,bank-name = "GPIOJ"; 568 status = "disabled"; 569 }; 570 571 gpiok: gpio@5000c000 { 572 gpio-controller; 573 #gpio-cells = <2>; 574 interrupt-controller; 575 #interrupt-cells = <2>; 576 reg = <0xa000 0x400>; 577 clocks = <&rcc GPIOK>; 578 st,bank-name = "GPIOK"; 579 status = "disabled"; 580 }; 581 }; 582 583 pinctrl_z: pinctrl@54004000 { 584 #address-cells = <1>; 585 #size-cells = <1>; 586 compatible = "st,stm32mp157-z-pinctrl"; 587 ranges = <0 0x54004000 0x400>; 588 pins-are-numbered; 589 interrupt-parent = <&exti>; 590 st,syscfg = <&exti 0x60 0xff>; 591 592 gpioz: gpio@54004000 { 593 gpio-controller; 594 #gpio-cells = <2>; 595 interrupt-controller; 596 #interrupt-cells = <2>; 597 #access-controller-cells = <1>; 598 reg = <0 0x400>; 599 clocks = <&rcc GPIOZ>; 600 st,bank-name = "GPIOZ"; 601 st,bank-ioport = <11>; 602 status = "disabled"; 603 }; 604 }; 605 606 tzc400: tzc@5c006000 { 607 compatible = "st,stm32mp1-tzc"; 608 reg = <0x5c006000 0x1000>; 609 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 610 clocks = <&rcc TZC1>, <&rcc TZC2>; 611 st,mem-map = <0xc0000000 0x40000000>; 612 }; 613 614 etzpc: etzpc@5c007000 { 615 compatible = "st,stm32-etzpc", "simple-bus"; 616 reg = <0x5C007000 0x400>; 617 clocks = <&rcc TZPC>; 618 #address-cells = <1>; 619 #size-cells = <1>; 620 #access-controller-cells = <1>; 621 622 timers2: timer@40000000 { 623 #address-cells = <1>; 624 #size-cells = <0>; 625 compatible = "st,stm32-timers"; 626 reg = <0x40000000 0x400>; 627 clocks = <&rcc TIM2_K>; 628 clock-names = "int"; 629 dmas = <&dmamux1 18 0x400 0x1>, 630 <&dmamux1 19 0x400 0x1>, 631 <&dmamux1 20 0x400 0x1>, 632 <&dmamux1 21 0x400 0x1>, 633 <&dmamux1 22 0x400 0x1>; 634 dma-names = "ch1", "ch2", "ch3", "ch4", "up"; 635 access-controllers = <&etzpc STM32MP1_ETZPC_TIM2_ID>; 636 status = "disabled"; 637 638 pwm { 639 compatible = "st,stm32-pwm"; 640 #pwm-cells = <3>; 641 status = "disabled"; 642 }; 643 644 timer@1 { 645 compatible = "st,stm32h7-timer-trigger"; 646 reg = <1>; 647 status = "disabled"; 648 }; 649 650 counter { 651 compatible = "st,stm32-timer-counter"; 652 status = "disabled"; 653 }; 654 }; 655 656 timers3: timer@40001000 { 657 #address-cells = <1>; 658 #size-cells = <0>; 659 compatible = "st,stm32-timers"; 660 reg = <0x40001000 0x400>; 661 clocks = <&rcc TIM3_K>; 662 clock-names = "int"; 663 dmas = <&dmamux1 23 0x400 0x1>, 664 <&dmamux1 24 0x400 0x1>, 665 <&dmamux1 25 0x400 0x1>, 666 <&dmamux1 26 0x400 0x1>, 667 <&dmamux1 27 0x400 0x1>, 668 <&dmamux1 28 0x400 0x1>; 669 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 670 access-controllers = <&etzpc STM32MP1_ETZPC_TIM3_ID>; 671 status = "disabled"; 672 673 pwm { 674 compatible = "st,stm32-pwm"; 675 #pwm-cells = <3>; 676 status = "disabled"; 677 }; 678 679 timer@2 { 680 compatible = "st,stm32h7-timer-trigger"; 681 reg = <2>; 682 status = "disabled"; 683 }; 684 685 counter { 686 compatible = "st,stm32-timer-counter"; 687 status = "disabled"; 688 }; 689 }; 690 691 timers4: timer@40002000 { 692 #address-cells = <1>; 693 #size-cells = <0>; 694 compatible = "st,stm32-timers"; 695 reg = <0x40002000 0x400>; 696 clocks = <&rcc TIM4_K>; 697 clock-names = "int"; 698 dmas = <&dmamux1 29 0x400 0x1>, 699 <&dmamux1 30 0x400 0x1>, 700 <&dmamux1 31 0x400 0x1>, 701 <&dmamux1 32 0x400 0x1>; 702 dma-names = "ch1", "ch2", "ch3", "ch4"; 703 access-controllers = <&etzpc STM32MP1_ETZPC_TIM4_ID>; 704 status = "disabled"; 705 706 pwm { 707 compatible = "st,stm32-pwm"; 708 #pwm-cells = <3>; 709 status = "disabled"; 710 }; 711 712 timer@3 { 713 compatible = "st,stm32h7-timer-trigger"; 714 reg = <3>; 715 status = "disabled"; 716 }; 717 718 counter { 719 compatible = "st,stm32-timer-counter"; 720 status = "disabled"; 721 }; 722 }; 723 724 timers5: timer@40003000 { 725 #address-cells = <1>; 726 #size-cells = <0>; 727 compatible = "st,stm32-timers"; 728 reg = <0x40003000 0x400>; 729 clocks = <&rcc TIM5_K>; 730 clock-names = "int"; 731 dmas = <&dmamux1 55 0x400 0x1>, 732 <&dmamux1 56 0x400 0x1>, 733 <&dmamux1 57 0x400 0x1>, 734 <&dmamux1 58 0x400 0x1>, 735 <&dmamux1 59 0x400 0x1>, 736 <&dmamux1 60 0x400 0x1>; 737 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 738 access-controllers = <&etzpc STM32MP1_ETZPC_TIM5_ID>; 739 status = "disabled"; 740 741 pwm { 742 compatible = "st,stm32-pwm"; 743 #pwm-cells = <3>; 744 status = "disabled"; 745 }; 746 747 timer@4 { 748 compatible = "st,stm32h7-timer-trigger"; 749 reg = <4>; 750 status = "disabled"; 751 }; 752 753 counter { 754 compatible = "st,stm32-timer-counter"; 755 status = "disabled"; 756 }; 757 }; 758 759 timers6: timer@40004000 { 760 #address-cells = <1>; 761 #size-cells = <0>; 762 compatible = "st,stm32-timers"; 763 reg = <0x40004000 0x400>; 764 clocks = <&rcc TIM6_K>; 765 clock-names = "int"; 766 dmas = <&dmamux1 69 0x400 0x1>; 767 dma-names = "up"; 768 access-controllers = <&etzpc STM32MP1_ETZPC_TIM6_ID>; 769 status = "disabled"; 770 771 timer@5 { 772 compatible = "st,stm32h7-timer-trigger"; 773 reg = <5>; 774 status = "disabled"; 775 }; 776 }; 777 778 timers7: timer@40005000 { 779 #address-cells = <1>; 780 #size-cells = <0>; 781 compatible = "st,stm32-timers"; 782 reg = <0x40005000 0x400>; 783 clocks = <&rcc TIM7_K>; 784 clock-names = "int"; 785 dmas = <&dmamux1 70 0x400 0x1>; 786 dma-names = "up"; 787 access-controllers = <&etzpc STM32MP1_ETZPC_TIM7_ID>; 788 status = "disabled"; 789 790 timer@6 { 791 compatible = "st,stm32h7-timer-trigger"; 792 reg = <6>; 793 status = "disabled"; 794 }; 795 }; 796 797 timers12: timer@40006000 { 798 #address-cells = <1>; 799 #size-cells = <0>; 800 compatible = "st,stm32-timers"; 801 reg = <0x40006000 0x400>; 802 clocks = <&rcc TIM12_K>; 803 clock-names = "int"; 804 access-controllers = <&etzpc STM32MP1_ETZPC_TIM12_ID>; 805 status = "disabled"; 806 807 pwm { 808 compatible = "st,stm32-pwm"; 809 #pwm-cells = <3>; 810 status = "disabled"; 811 }; 812 813 timer@11 { 814 compatible = "st,stm32h7-timer-trigger"; 815 reg = <11>; 816 status = "disabled"; 817 }; 818 }; 819 820 timers13: timer@40007000 { 821 #address-cells = <1>; 822 #size-cells = <0>; 823 compatible = "st,stm32-timers"; 824 reg = <0x40007000 0x400>; 825 clocks = <&rcc TIM13_K>; 826 clock-names = "int"; 827 access-controllers = <&etzpc STM32MP1_ETZPC_TIM13_ID>; 828 status = "disabled"; 829 830 pwm { 831 compatible = "st,stm32-pwm"; 832 #pwm-cells = <3>; 833 status = "disabled"; 834 }; 835 836 timer@12 { 837 compatible = "st,stm32h7-timer-trigger"; 838 reg = <12>; 839 status = "disabled"; 840 }; 841 }; 842 843 timers14: timer@40008000 { 844 #address-cells = <1>; 845 #size-cells = <0>; 846 compatible = "st,stm32-timers"; 847 reg = <0x40008000 0x400>; 848 clocks = <&rcc TIM14_K>; 849 clock-names = "int"; 850 access-controllers = <&etzpc STM32MP1_ETZPC_TIM14_ID>; 851 status = "disabled"; 852 853 pwm { 854 compatible = "st,stm32-pwm"; 855 #pwm-cells = <3>; 856 status = "disabled"; 857 }; 858 859 timer@13 { 860 compatible = "st,stm32h7-timer-trigger"; 861 reg = <13>; 862 status = "disabled"; 863 }; 864 }; 865 866 lptimer1: timer@40009000 { 867 #address-cells = <1>; 868 #size-cells = <0>; 869 compatible = "st,stm32-lptimer"; 870 reg = <0x40009000 0x400>; 871 interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; 872 clocks = <&rcc LPTIM1_K>; 873 clock-names = "mux"; 874 wakeup-source; 875 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM1_ID>; 876 status = "disabled"; 877 878 pwm { 879 compatible = "st,stm32-pwm-lp"; 880 #pwm-cells = <3>; 881 status = "disabled"; 882 }; 883 884 trigger@0 { 885 compatible = "st,stm32-lptimer-trigger"; 886 reg = <0>; 887 status = "disabled"; 888 }; 889 890 counter { 891 compatible = "st,stm32-lptimer-counter"; 892 status = "disabled"; 893 }; 894 }; 895 896 spi2: spi@4000b000 { 897 #address-cells = <1>; 898 #size-cells = <0>; 899 compatible = "st,stm32h7-spi"; 900 reg = <0x4000b000 0x400>; 901 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 902 clocks = <&rcc SPI2_K>; 903 resets = <&rcc SPI2_R>; 904 dmas = <&dmamux1 39 0x400 0x05>, 905 <&dmamux1 40 0x400 0x05>; 906 dma-names = "rx", "tx"; 907 access-controllers = <&etzpc STM32MP1_ETZPC_SPI2_ID>; 908 status = "disabled"; 909 }; 910 911 i2s2: audio-controller@4000b000 { 912 compatible = "st,stm32h7-i2s"; 913 #sound-dai-cells = <0>; 914 reg = <0x4000b000 0x400>; 915 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 916 dmas = <&dmamux1 39 0x400 0x01>, 917 <&dmamux1 40 0x400 0x01>; 918 dma-names = "rx", "tx"; 919 access-controllers = <&etzpc STM32MP1_ETZPC_SPI2_ID>; 920 status = "disabled"; 921 }; 922 923 spi3: spi@4000c000 { 924 #address-cells = <1>; 925 #size-cells = <0>; 926 compatible = "st,stm32h7-spi"; 927 reg = <0x4000c000 0x400>; 928 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 929 clocks = <&rcc SPI3_K>; 930 resets = <&rcc SPI3_R>; 931 dmas = <&dmamux1 61 0x400 0x05>, 932 <&dmamux1 62 0x400 0x05>; 933 dma-names = "rx", "tx"; 934 access-controllers = <&etzpc STM32MP1_ETZPC_SPI3_ID>; 935 status = "disabled"; 936 }; 937 938 i2s3: audio-controller@4000c000 { 939 compatible = "st,stm32h7-i2s"; 940 #sound-dai-cells = <0>; 941 reg = <0x4000c000 0x400>; 942 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 943 dmas = <&dmamux1 61 0x400 0x01>, 944 <&dmamux1 62 0x400 0x01>; 945 dma-names = "rx", "tx"; 946 access-controllers = <&etzpc STM32MP1_ETZPC_SPI3_ID>; 947 status = "disabled"; 948 }; 949 950 spdifrx: audio-controller@4000d000 { 951 compatible = "st,stm32h7-spdifrx"; 952 #sound-dai-cells = <0>; 953 reg = <0x4000d000 0x400>; 954 clocks = <&rcc SPDIF_K>; 955 clock-names = "kclk"; 956 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 957 dmas = <&dmamux1 93 0x400 0x01>, 958 <&dmamux1 94 0x400 0x01>; 959 dma-names = "rx", "rx-ctrl"; 960 access-controllers = <&etzpc STM32MP1_ETZPC_SPDIFRX_ID>; 961 status = "disabled"; 962 }; 963 964 usart2: serial@4000e000 { 965 compatible = "st,stm32h7-uart"; 966 reg = <0x4000e000 0x400>; 967 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; 968 clocks = <&rcc USART2_K>; 969 wakeup-source; 970 dmas = <&dmamux1 43 0x400 0x15>, 971 <&dmamux1 44 0x400 0x11>; 972 dma-names = "rx", "tx"; 973 access-controllers = <&etzpc STM32MP1_ETZPC_USART2_ID>; 974 status = "disabled"; 975 }; 976 977 usart3: serial@4000f000 { 978 compatible = "st,stm32h7-uart"; 979 reg = <0x4000f000 0x400>; 980 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; 981 clocks = <&rcc USART3_K>; 982 wakeup-source; 983 dmas = <&dmamux1 45 0x400 0x15>, 984 <&dmamux1 46 0x400 0x11>; 985 dma-names = "rx", "tx"; 986 access-controllers = <&etzpc STM32MP1_ETZPC_USART3_ID>; 987 status = "disabled"; 988 }; 989 990 uart4: serial@40010000 { 991 compatible = "st,stm32h7-uart"; 992 reg = <0x40010000 0x400>; 993 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; 994 clocks = <&rcc UART4_K>; 995 wakeup-source; 996 dmas = <&dmamux1 63 0x400 0x15>, 997 <&dmamux1 64 0x400 0x11>; 998 dma-names = "rx", "tx"; 999 access-controllers = <&etzpc STM32MP1_ETZPC_UART4_ID>; 1000 status = "disabled"; 1001 }; 1002 1003 uart5: serial@40011000 { 1004 compatible = "st,stm32h7-uart"; 1005 reg = <0x40011000 0x400>; 1006 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; 1007 clocks = <&rcc UART5_K>; 1008 wakeup-source; 1009 dmas = <&dmamux1 65 0x400 0x15>, 1010 <&dmamux1 66 0x400 0x11>; 1011 dma-names = "rx", "tx"; 1012 access-controllers = <&etzpc STM32MP1_ETZPC_UART5_ID>; 1013 status = "disabled"; 1014 }; 1015 1016 i2c1: i2c@40012000 { 1017 compatible = "st,stm32mp15-i2c"; 1018 reg = <0x40012000 0x400>; 1019 interrupt-names = "event", "error"; 1020 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1021 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1022 clocks = <&rcc I2C1_K>; 1023 resets = <&rcc I2C1_R>; 1024 #address-cells = <1>; 1025 #size-cells = <0>; 1026 st,syscfg-fmp = <&syscfg 0x4 0x1>; 1027 wakeup-source; 1028 i2c-analog-filter; 1029 access-controllers = <&etzpc STM32MP1_ETZPC_I2C1_ID>; 1030 status = "disabled"; 1031 }; 1032 1033 i2c2: i2c@40013000 { 1034 compatible = "st,stm32mp15-i2c"; 1035 reg = <0x40013000 0x400>; 1036 interrupt-names = "event", "error"; 1037 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 1038 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1039 clocks = <&rcc I2C2_K>; 1040 resets = <&rcc I2C2_R>; 1041 #address-cells = <1>; 1042 #size-cells = <0>; 1043 st,syscfg-fmp = <&syscfg 0x4 0x2>; 1044 wakeup-source; 1045 i2c-analog-filter; 1046 access-controllers = <&etzpc STM32MP1_ETZPC_I2C2_ID>; 1047 status = "disabled"; 1048 }; 1049 1050 i2c3: i2c@40014000 { 1051 compatible = "st,stm32mp15-i2c"; 1052 reg = <0x40014000 0x400>; 1053 interrupt-names = "event", "error"; 1054 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 1055 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1056 clocks = <&rcc I2C3_K>; 1057 resets = <&rcc I2C3_R>; 1058 #address-cells = <1>; 1059 #size-cells = <0>; 1060 st,syscfg-fmp = <&syscfg 0x4 0x4>; 1061 wakeup-source; 1062 i2c-analog-filter; 1063 access-controllers = <&etzpc STM32MP1_ETZPC_I2C3_ID>; 1064 status = "disabled"; 1065 }; 1066 1067 i2c5: i2c@40015000 { 1068 compatible = "st,stm32mp15-i2c"; 1069 reg = <0x40015000 0x400>; 1070 interrupt-names = "event", "error"; 1071 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1072 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1073 clocks = <&rcc I2C5_K>; 1074 resets = <&rcc I2C5_R>; 1075 #address-cells = <1>; 1076 #size-cells = <0>; 1077 st,syscfg-fmp = <&syscfg 0x4 0x10>; 1078 wakeup-source; 1079 i2c-analog-filter; 1080 access-controllers = <&etzpc STM32MP1_ETZPC_I2C5_ID>; 1081 status = "disabled"; 1082 }; 1083 1084 cec: cec@40016000 { 1085 compatible = "st,stm32-cec"; 1086 reg = <0x40016000 0x400>; 1087 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1088 clocks = <&rcc CEC_K>, <&rcc CEC>; 1089 clock-names = "cec", "hdmi-cec"; 1090 access-controllers = <&etzpc STM32MP1_ETZPC_CEC_ID>; 1091 status = "disabled"; 1092 }; 1093 1094 dac: dac@40017000 { 1095 compatible = "st,stm32h7-dac-core"; 1096 reg = <0x40017000 0x400>; 1097 clocks = <&rcc DAC12>; 1098 clock-names = "pclk"; 1099 #address-cells = <1>; 1100 #size-cells = <0>; 1101 access-controllers = <&etzpc STM32MP1_ETZPC_DAC_ID>; 1102 status = "disabled"; 1103 1104 dac1: dac@1 { 1105 compatible = "st,stm32-dac"; 1106 #io-channel-cells = <1>; 1107 reg = <1>; 1108 status = "disabled"; 1109 }; 1110 1111 dac2: dac@2 { 1112 compatible = "st,stm32-dac"; 1113 #io-channel-cells = <1>; 1114 reg = <2>; 1115 status = "disabled"; 1116 }; 1117 }; 1118 1119 uart7: serial@40018000 { 1120 compatible = "st,stm32h7-uart"; 1121 reg = <0x40018000 0x400>; 1122 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; 1123 clocks = <&rcc UART7_K>; 1124 wakeup-source; 1125 dmas = <&dmamux1 79 0x400 0x15>, 1126 <&dmamux1 80 0x400 0x11>; 1127 dma-names = "rx", "tx"; 1128 access-controllers = <&etzpc STM32MP1_ETZPC_UART7_ID>; 1129 status = "disabled"; 1130 }; 1131 1132 uart8: serial@40019000 { 1133 compatible = "st,stm32h7-uart"; 1134 reg = <0x40019000 0x400>; 1135 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; 1136 clocks = <&rcc UART8_K>; 1137 wakeup-source; 1138 dmas = <&dmamux1 81 0x400 0x15>, 1139 <&dmamux1 82 0x400 0x11>; 1140 dma-names = "rx", "tx"; 1141 access-controllers = <&etzpc STM32MP1_ETZPC_UART8_ID>; 1142 status = "disabled"; 1143 }; 1144 1145 timers1: timer@44000000 { 1146 #address-cells = <1>; 1147 #size-cells = <0>; 1148 compatible = "st,stm32-timers"; 1149 reg = <0x44000000 0x400>; 1150 clocks = <&rcc TIM1_K>; 1151 clock-names = "int"; 1152 dmas = <&dmamux1 11 0x400 0x1>, 1153 <&dmamux1 12 0x400 0x1>, 1154 <&dmamux1 13 0x400 0x1>, 1155 <&dmamux1 14 0x400 0x1>, 1156 <&dmamux1 15 0x400 0x1>, 1157 <&dmamux1 16 0x400 0x1>, 1158 <&dmamux1 17 0x400 0x1>; 1159 dma-names = "ch1", "ch2", "ch3", "ch4", 1160 "up", "trig", "com"; 1161 access-controllers = <&etzpc STM32MP1_ETZPC_TIM1_ID>; 1162 status = "disabled"; 1163 1164 pwm { 1165 compatible = "st,stm32-pwm"; 1166 #pwm-cells = <3>; 1167 status = "disabled"; 1168 }; 1169 1170 timer@0 { 1171 compatible = "st,stm32h7-timer-trigger"; 1172 reg = <0>; 1173 status = "disabled"; 1174 }; 1175 1176 counter { 1177 compatible = "st,stm32-timer-counter"; 1178 status = "disabled"; 1179 }; 1180 }; 1181 1182 timers8: timer@44001000 { 1183 #address-cells = <1>; 1184 #size-cells = <0>; 1185 compatible = "st,stm32-timers"; 1186 reg = <0x44001000 0x400>; 1187 clocks = <&rcc TIM8_K>; 1188 clock-names = "int"; 1189 dmas = <&dmamux1 47 0x400 0x1>, 1190 <&dmamux1 48 0x400 0x1>, 1191 <&dmamux1 49 0x400 0x1>, 1192 <&dmamux1 50 0x400 0x1>, 1193 <&dmamux1 51 0x400 0x1>, 1194 <&dmamux1 52 0x400 0x1>, 1195 <&dmamux1 53 0x400 0x1>; 1196 dma-names = "ch1", "ch2", "ch3", "ch4", 1197 "up", "trig", "com"; 1198 access-controllers = <&etzpc STM32MP1_ETZPC_TIM8_ID>; 1199 status = "disabled"; 1200 1201 pwm { 1202 compatible = "st,stm32-pwm"; 1203 #pwm-cells = <3>; 1204 status = "disabled"; 1205 }; 1206 1207 timer@7 { 1208 compatible = "st,stm32h7-timer-trigger"; 1209 reg = <7>; 1210 status = "disabled"; 1211 }; 1212 1213 counter { 1214 compatible = "st,stm32-timer-counter"; 1215 status = "disabled"; 1216 }; 1217 }; 1218 1219 usart6: serial@44003000 { 1220 compatible = "st,stm32h7-uart"; 1221 reg = <0x44003000 0x400>; 1222 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; 1223 clocks = <&rcc USART6_K>; 1224 wakeup-source; 1225 dmas = <&dmamux1 71 0x400 0x15>, 1226 <&dmamux1 72 0x400 0x11>; 1227 dma-names = "rx", "tx"; 1228 access-controllers = <&etzpc STM32MP1_ETZPC_USART6_ID>; 1229 status = "disabled"; 1230 }; 1231 1232 spi1: spi@44004000 { 1233 #address-cells = <1>; 1234 #size-cells = <0>; 1235 compatible = "st,stm32h7-spi"; 1236 reg = <0x44004000 0x400>; 1237 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1238 clocks = <&rcc SPI1_K>; 1239 resets = <&rcc SPI1_R>; 1240 dmas = <&dmamux1 37 0x400 0x05>, 1241 <&dmamux1 38 0x400 0x05>; 1242 dma-names = "rx", "tx"; 1243 access-controllers = <&etzpc STM32MP1_ETZPC_SPI1_ID>; 1244 status = "disabled"; 1245 }; 1246 1247 i2s1: audio-controller@44004000 { 1248 compatible = "st,stm32h7-i2s"; 1249 #sound-dai-cells = <0>; 1250 reg = <0x44004000 0x400>; 1251 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1252 dmas = <&dmamux1 37 0x400 0x01>, 1253 <&dmamux1 38 0x400 0x01>; 1254 dma-names = "rx", "tx"; 1255 access-controllers = <&etzpc STM32MP1_ETZPC_SPI1_ID>; 1256 status = "disabled"; 1257 }; 1258 1259 spi4: spi@44005000 { 1260 #address-cells = <1>; 1261 #size-cells = <0>; 1262 compatible = "st,stm32h7-spi"; 1263 reg = <0x44005000 0x400>; 1264 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1265 clocks = <&rcc SPI4_K>; 1266 resets = <&rcc SPI4_R>; 1267 dmas = <&dmamux1 83 0x400 0x05>, 1268 <&dmamux1 84 0x400 0x05>; 1269 dma-names = "rx", "tx"; 1270 access-controllers = <&etzpc STM32MP1_ETZPC_SPI4_ID>; 1271 status = "disabled"; 1272 }; 1273 1274 timers15: timer@44006000 { 1275 #address-cells = <1>; 1276 #size-cells = <0>; 1277 compatible = "st,stm32-timers"; 1278 reg = <0x44006000 0x400>; 1279 clocks = <&rcc TIM15_K>; 1280 clock-names = "int"; 1281 dmas = <&dmamux1 105 0x400 0x1>, 1282 <&dmamux1 106 0x400 0x1>, 1283 <&dmamux1 107 0x400 0x1>, 1284 <&dmamux1 108 0x400 0x1>; 1285 dma-names = "ch1", "up", "trig", "com"; 1286 access-controllers = <&etzpc STM32MP1_ETZPC_TIM15_ID>; 1287 status = "disabled"; 1288 1289 pwm { 1290 compatible = "st,stm32-pwm"; 1291 #pwm-cells = <3>; 1292 status = "disabled"; 1293 }; 1294 1295 timer@14 { 1296 compatible = "st,stm32h7-timer-trigger"; 1297 reg = <14>; 1298 status = "disabled"; 1299 }; 1300 }; 1301 1302 timers16: timer@44007000 { 1303 #address-cells = <1>; 1304 #size-cells = <0>; 1305 compatible = "st,stm32-timers"; 1306 reg = <0x44007000 0x400>; 1307 clocks = <&rcc TIM16_K>; 1308 clock-names = "int"; 1309 dmas = <&dmamux1 109 0x400 0x1>, 1310 <&dmamux1 110 0x400 0x1>; 1311 dma-names = "ch1", "up"; 1312 access-controllers = <&etzpc STM32MP1_ETZPC_TIM16_ID>; 1313 status = "disabled"; 1314 1315 pwm { 1316 compatible = "st,stm32-pwm"; 1317 #pwm-cells = <3>; 1318 status = "disabled"; 1319 }; 1320 timer@15 { 1321 compatible = "st,stm32h7-timer-trigger"; 1322 reg = <15>; 1323 status = "disabled"; 1324 }; 1325 }; 1326 1327 timers17: timer@44008000 { 1328 #address-cells = <1>; 1329 #size-cells = <0>; 1330 compatible = "st,stm32-timers"; 1331 reg = <0x44008000 0x400>; 1332 clocks = <&rcc TIM17_K>; 1333 clock-names = "int"; 1334 dmas = <&dmamux1 111 0x400 0x1>, 1335 <&dmamux1 112 0x400 0x1>; 1336 dma-names = "ch1", "up"; 1337 access-controllers = <&etzpc STM32MP1_ETZPC_TIM17_ID>; 1338 status = "disabled"; 1339 1340 pwm { 1341 compatible = "st,stm32-pwm"; 1342 #pwm-cells = <3>; 1343 status = "disabled"; 1344 }; 1345 1346 timer@16 { 1347 compatible = "st,stm32h7-timer-trigger"; 1348 reg = <16>; 1349 status = "disabled"; 1350 }; 1351 }; 1352 1353 spi5: spi@44009000 { 1354 #address-cells = <1>; 1355 #size-cells = <0>; 1356 compatible = "st,stm32h7-spi"; 1357 reg = <0x44009000 0x400>; 1358 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1359 clocks = <&rcc SPI5_K>; 1360 resets = <&rcc SPI5_R>; 1361 dmas = <&dmamux1 85 0x400 0x05>, 1362 <&dmamux1 86 0x400 0x05>; 1363 dma-names = "rx", "tx"; 1364 access-controllers = <&etzpc STM32MP1_ETZPC_SPI5_ID>; 1365 status = "disabled"; 1366 }; 1367 1368 sai1: sai@4400a000 { 1369 compatible = "st,stm32h7-sai"; 1370 #address-cells = <1>; 1371 #size-cells = <1>; 1372 ranges = <0 0x4400a000 0x400>; 1373 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; 1374 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1375 resets = <&rcc SAI1_R>; 1376 access-controllers = <&etzpc STM32MP1_ETZPC_SAI1_ID>; 1377 status = "disabled"; 1378 1379 sai1a: audio-controller@4400a004 { 1380 #sound-dai-cells = <0>; 1381 1382 compatible = "st,stm32-sai-sub-a"; 1383 reg = <0x4 0x20>; 1384 clocks = <&rcc SAI1_K>; 1385 clock-names = "sai_ck"; 1386 dmas = <&dmamux1 87 0x400 0x01>; 1387 status = "disabled"; 1388 }; 1389 1390 sai1b: audio-controller@4400a024 { 1391 #sound-dai-cells = <0>; 1392 compatible = "st,stm32-sai-sub-b"; 1393 reg = <0x24 0x20>; 1394 clocks = <&rcc SAI1_K>; 1395 clock-names = "sai_ck"; 1396 dmas = <&dmamux1 88 0x400 0x01>; 1397 status = "disabled"; 1398 }; 1399 }; 1400 1401 sai2: sai@4400b000 { 1402 compatible = "st,stm32h7-sai"; 1403 #address-cells = <1>; 1404 #size-cells = <1>; 1405 ranges = <0 0x4400b000 0x400>; 1406 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; 1407 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1408 resets = <&rcc SAI2_R>; 1409 access-controllers = <&etzpc STM32MP1_ETZPC_SAI2_ID>; 1410 status = "disabled"; 1411 1412 sai2a: audio-controller@4400b004 { 1413 #sound-dai-cells = <0>; 1414 compatible = "st,stm32-sai-sub-a"; 1415 reg = <0x4 0x20>; 1416 clocks = <&rcc SAI2_K>; 1417 clock-names = "sai_ck"; 1418 dmas = <&dmamux1 89 0x400 0x01>; 1419 status = "disabled"; 1420 }; 1421 1422 sai2b: audio-controller@4400b024 { 1423 #sound-dai-cells = <0>; 1424 compatible = "st,stm32-sai-sub-b"; 1425 reg = <0x24 0x20>; 1426 clocks = <&rcc SAI2_K>; 1427 clock-names = "sai_ck"; 1428 dmas = <&dmamux1 90 0x400 0x01>; 1429 status = "disabled"; 1430 }; 1431 }; 1432 1433 sai3: sai@4400c000 { 1434 compatible = "st,stm32h7-sai"; 1435 #address-cells = <1>; 1436 #size-cells = <1>; 1437 ranges = <0 0x4400c000 0x400>; 1438 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; 1439 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1440 resets = <&rcc SAI3_R>; 1441 access-controllers = <&etzpc STM32MP1_ETZPC_SAI3_ID>; 1442 status = "disabled"; 1443 1444 sai3a: audio-controller@4400c004 { 1445 #sound-dai-cells = <0>; 1446 compatible = "st,stm32-sai-sub-a"; 1447 reg = <0x04 0x20>; 1448 clocks = <&rcc SAI3_K>; 1449 clock-names = "sai_ck"; 1450 dmas = <&dmamux1 113 0x400 0x01>; 1451 status = "disabled"; 1452 }; 1453 1454 sai3b: audio-controller@4400c024 { 1455 #sound-dai-cells = <0>; 1456 compatible = "st,stm32-sai-sub-b"; 1457 reg = <0x24 0x20>; 1458 clocks = <&rcc SAI3_K>; 1459 clock-names = "sai_ck"; 1460 dmas = <&dmamux1 114 0x400 0x01>; 1461 status = "disabled"; 1462 }; 1463 }; 1464 1465 dfsdm: dfsdm@4400d000 { 1466 compatible = "st,stm32mp1-dfsdm"; 1467 reg = <0x4400d000 0x800>; 1468 clocks = <&rcc DFSDM_K>; 1469 clock-names = "dfsdm"; 1470 #address-cells = <1>; 1471 #size-cells = <0>; 1472 access-controllers = <&etzpc STM32MP1_ETZPC_DFSDM_ID>; 1473 status = "disabled"; 1474 1475 dfsdm0: filter@0 { 1476 compatible = "st,stm32-dfsdm-adc"; 1477 #io-channel-cells = <1>; 1478 reg = <0>; 1479 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 1480 dmas = <&dmamux1 101 0x400 0x01>; 1481 dma-names = "rx"; 1482 status = "disabled"; 1483 }; 1484 1485 dfsdm1: filter@1 { 1486 compatible = "st,stm32-dfsdm-adc"; 1487 #io-channel-cells = <1>; 1488 reg = <1>; 1489 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1490 dmas = <&dmamux1 102 0x400 0x01>; 1491 dma-names = "rx"; 1492 status = "disabled"; 1493 }; 1494 1495 dfsdm2: filter@2 { 1496 compatible = "st,stm32-dfsdm-adc"; 1497 #io-channel-cells = <1>; 1498 reg = <2>; 1499 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1500 dmas = <&dmamux1 103 0x400 0x01>; 1501 dma-names = "rx"; 1502 status = "disabled"; 1503 }; 1504 1505 dfsdm3: filter@3 { 1506 compatible = "st,stm32-dfsdm-adc"; 1507 #io-channel-cells = <1>; 1508 reg = <3>; 1509 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1510 dmas = <&dmamux1 104 0x400 0x01>; 1511 dma-names = "rx"; 1512 status = "disabled"; 1513 }; 1514 1515 dfsdm4: filter@4 { 1516 compatible = "st,stm32-dfsdm-adc"; 1517 #io-channel-cells = <1>; 1518 reg = <4>; 1519 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1520 dmas = <&dmamux1 91 0x400 0x01>; 1521 dma-names = "rx"; 1522 status = "disabled"; 1523 }; 1524 1525 dfsdm5: filter@5 { 1526 compatible = "st,stm32-dfsdm-adc"; 1527 #io-channel-cells = <1>; 1528 reg = <5>; 1529 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1530 dmas = <&dmamux1 92 0x400 0x01>; 1531 dma-names = "rx"; 1532 status = "disabled"; 1533 }; 1534 }; 1535 1536 dma1: dma-controller@48000000 { 1537 compatible = "st,stm32-dma"; 1538 reg = <0x48000000 0x400>; 1539 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1540 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1541 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1542 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1543 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1544 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1545 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1546 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1547 clocks = <&rcc DMA1>; 1548 resets = <&rcc DMA1_R>; 1549 #dma-cells = <4>; 1550 st,mem2mem; 1551 dma-requests = <8>; 1552 access-controllers = <&etzpc STM32MP1_ETZPC_DMA1_ID>; 1553 status = "disabled"; 1554 }; 1555 1556 dma2: dma-controller@48001000 { 1557 compatible = "st,stm32-dma"; 1558 reg = <0x48001000 0x400>; 1559 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1560 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1564 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 1565 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1566 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1567 clocks = <&rcc DMA2>; 1568 resets = <&rcc DMA2_R>; 1569 #dma-cells = <4>; 1570 st,mem2mem; 1571 dma-requests = <8>; 1572 access-controllers = <&etzpc STM32MP1_ETZPC_DMA2_ID>; 1573 status = "disabled"; 1574 }; 1575 1576 dmamux1: dma-router@48002000 { 1577 compatible = "st,stm32h7-dmamux"; 1578 reg = <0x48002000 0x40>; 1579 #dma-cells = <3>; 1580 dma-requests = <128>; 1581 dma-masters = <&dma1 &dma2>; 1582 dma-channels = <16>; 1583 clocks = <&rcc DMAMUX>; 1584 resets = <&rcc DMAMUX_R>; 1585 access-controllers = <&etzpc STM32MP1_ETZPC_DMAMUX_ID>; 1586 status = "disabled"; 1587 }; 1588 1589 adc: adc@48003000 { 1590 compatible = "st,stm32mp1-adc-core"; 1591 reg = <0x48003000 0x400>; 1592 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1593 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1594 clocks = <&rcc ADC12>, <&rcc ADC12_K>; 1595 clock-names = "bus", "adc"; 1596 interrupt-controller; 1597 st,syscfg = <&syscfg>; 1598 #interrupt-cells = <1>; 1599 #address-cells = <1>; 1600 #size-cells = <0>; 1601 access-controllers = <&etzpc STM32MP1_ETZPC_ADC_ID>; 1602 status = "disabled"; 1603 1604 adc1: adc@0 { 1605 compatible = "st,stm32mp1-adc"; 1606 #io-channel-cells = <1>; 1607 reg = <0x0>; 1608 interrupt-parent = <&adc>; 1609 interrupts = <0>; 1610 dmas = <&dmamux1 9 0x400 0x01>; 1611 dma-names = "rx"; 1612 status = "disabled"; 1613 }; 1614 1615 adc2: adc@100 { 1616 compatible = "st,stm32mp1-adc"; 1617 #io-channel-cells = <1>; 1618 reg = <0x100>; 1619 interrupt-parent = <&adc>; 1620 interrupts = <1>; 1621 dmas = <&dmamux1 10 0x400 0x01>; 1622 dma-names = "rx"; 1623 status = "disabled"; 1624 }; 1625 }; 1626 1627 sdmmc3: mmc@48004000 { 1628 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 1629 arm,primecell-periphid = <0x00253180>; 1630 reg = <0x48004000 0x400>; 1631 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1632 interrupt-names = "cmd_irq"; 1633 clocks = <&rcc SDMMC3_K>; 1634 clock-names = "apb_pclk"; 1635 resets = <&rcc SDMMC3_R>; 1636 cap-sd-highspeed; 1637 cap-mmc-highspeed; 1638 max-frequency = <120000000>; 1639 access-controllers = <&etzpc STM32MP1_ETZPC_SDMMC3_ID>; 1640 status = "disabled"; 1641 }; 1642 1643 usbotg_hs: usb-otg@49000000 { 1644 compatible = "st,stm32mp15-hsotg", "snps,dwc2"; 1645 reg = <0x49000000 0x10000>; 1646 clocks = <&rcc USBO_K>; 1647 clock-names = "otg"; 1648 resets = <&rcc USBO_R>; 1649 reset-names = "dwc2"; 1650 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1651 g-rx-fifo-size = <512>; 1652 g-np-tx-fifo-size = <32>; 1653 g-tx-fifo-size = <256 16 16 16 16 16 16 16>; 1654 dr_mode = "otg"; 1655 otg-rev = <0x200>; 1656 usb33d-supply = <&usb33>; 1657 access-controllers = <&etzpc STM32MP1_ETZPC_OTG_ID>; 1658 status = "disabled"; 1659 }; 1660 1661 dcmi: dcmi@4c006000 { 1662 compatible = "st,stm32-dcmi"; 1663 reg = <0x4c006000 0x400>; 1664 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1665 resets = <&rcc CAMITF_R>; 1666 clocks = <&rcc DCMI>; 1667 clock-names = "mclk"; 1668 dmas = <&dmamux1 75 0x400 0x01>; 1669 dma-names = "tx"; 1670 access-controllers = <&etzpc STM32MP1_ETZPC_DCMI_ID>; 1671 status = "disabled"; 1672 }; 1673 1674 lptimer2: timer@50021000 { 1675 #address-cells = <1>; 1676 #size-cells = <0>; 1677 compatible = "st,stm32-lptimer"; 1678 reg = <0x50021000 0x400>; 1679 interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; 1680 clocks = <&rcc LPTIM2_K>; 1681 clock-names = "mux"; 1682 wakeup-source; 1683 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM2_ID>; 1684 status = "disabled"; 1685 1686 pwm { 1687 compatible = "st,stm32-pwm-lp"; 1688 #pwm-cells = <3>; 1689 status = "disabled"; 1690 }; 1691 1692 trigger@1 { 1693 compatible = "st,stm32-lptimer-trigger"; 1694 reg = <1>; 1695 status = "disabled"; 1696 }; 1697 1698 counter { 1699 compatible = "st,stm32-lptimer-counter"; 1700 status = "disabled"; 1701 }; 1702 }; 1703 1704 lptimer3: timer@50022000 { 1705 #address-cells = <1>; 1706 #size-cells = <0>; 1707 compatible = "st,stm32-lptimer"; 1708 reg = <0x50022000 0x400>; 1709 interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; 1710 clocks = <&rcc LPTIM3_K>; 1711 clock-names = "mux"; 1712 wakeup-source; 1713 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM3_ID>; 1714 status = "disabled"; 1715 1716 pwm { 1717 compatible = "st,stm32-pwm-lp"; 1718 #pwm-cells = <3>; 1719 status = "disabled"; 1720 }; 1721 1722 trigger@2 { 1723 compatible = "st,stm32-lptimer-trigger"; 1724 reg = <2>; 1725 status = "disabled"; 1726 }; 1727 }; 1728 1729 lptimer4: timer@50023000 { 1730 compatible = "st,stm32-lptimer"; 1731 reg = <0x50023000 0x400>; 1732 interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; 1733 clocks = <&rcc LPTIM4_K>; 1734 clock-names = "mux"; 1735 wakeup-source; 1736 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM4_ID>; 1737 status = "disabled"; 1738 1739 pwm { 1740 compatible = "st,stm32-pwm-lp"; 1741 #pwm-cells = <3>; 1742 status = "disabled"; 1743 }; 1744 }; 1745 1746 lptimer5: timer@50024000 { 1747 compatible = "st,stm32-lptimer"; 1748 reg = <0x50024000 0x400>; 1749 interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; 1750 clocks = <&rcc LPTIM5_K>; 1751 clock-names = "mux"; 1752 wakeup-source; 1753 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM5_ID>; 1754 status = "disabled"; 1755 1756 pwm { 1757 compatible = "st,stm32-pwm-lp"; 1758 #pwm-cells = <3>; 1759 status = "disabled"; 1760 }; 1761 }; 1762 1763 vrefbuf: vrefbuf@50025000 { 1764 compatible = "st,stm32-vrefbuf"; 1765 reg = <0x50025000 0x8>; 1766 regulator-min-microvolt = <1500000>; 1767 regulator-max-microvolt = <2500000>; 1768 clocks = <&rcc VREF>; 1769 access-controllers = <&etzpc STM32MP1_ETZPC_VREFBUF_ID>; 1770 status = "disabled"; 1771 }; 1772 1773 sai4: sai@50027000 { 1774 compatible = "st,stm32h7-sai"; 1775 #address-cells = <1>; 1776 #size-cells = <1>; 1777 ranges = <0 0x50027000 0x400>; 1778 reg = <0x50027000 0x4>, <0x500273f0 0x10>; 1779 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1780 resets = <&rcc SAI4_R>; 1781 access-controllers = <&etzpc STM32MP1_ETZPC_SAI4_ID>; 1782 status = "disabled"; 1783 1784 sai4a: audio-controller@50027004 { 1785 #sound-dai-cells = <0>; 1786 compatible = "st,stm32-sai-sub-a"; 1787 reg = <0x04 0x20>; 1788 clocks = <&rcc SAI4_K>; 1789 clock-names = "sai_ck"; 1790 dmas = <&dmamux1 99 0x400 0x01>; 1791 status = "disabled"; 1792 }; 1793 1794 sai4b: audio-controller@50027024 { 1795 #sound-dai-cells = <0>; 1796 compatible = "st,stm32-sai-sub-b"; 1797 reg = <0x24 0x20>; 1798 clocks = <&rcc SAI4_K>; 1799 clock-names = "sai_ck"; 1800 dmas = <&dmamux1 100 0x400 0x01>; 1801 status = "disabled"; 1802 }; 1803 }; 1804 1805 hash1: hash@54002000 { 1806 compatible = "st,stm32f756-hash"; 1807 reg = <0x54002000 0x400>; 1808 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1809 clocks = <&rcc HASH1>; 1810 resets = <&rcc HASH1_R>; 1811 dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; 1812 dma-names = "in"; 1813 dma-maxburst = <2>; 1814 access-controllers = <&etzpc STM32MP1_ETZPC_HASH1_ID>; 1815 status = "disabled"; 1816 }; 1817 1818 rng1: rng@54003000 { 1819 compatible = "st,stm32-rng"; 1820 reg = <0x54003000 0x400>; 1821 clocks = <&rcc RNG1_K>; 1822 resets = <&rcc RNG1_R>; 1823 access-controllers = <&etzpc STM32MP1_ETZPC_RNG1_ID>; 1824 status = "disabled"; 1825 }; 1826 1827 fmc: memory-controller@58002000 { 1828 #address-cells = <2>; 1829 #size-cells = <1>; 1830 compatible = "st,stm32mp1-fmc2-ebi"; 1831 reg = <0x58002000 0x1000>; 1832 clocks = <&rcc FMC_K>; 1833 resets = <&rcc FMC_R>; 1834 access-controllers = <&etzpc STM32MP1_ETZPC_FMC_ID>; 1835 status = "disabled"; 1836 1837 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 1838 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 1839 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 1840 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 1841 <4 0 0x80000000 0x10000000>; /* NAND */ 1842 1843 nand-controller@4,0 { 1844 #address-cells = <1>; 1845 #size-cells = <0>; 1846 compatible = "st,stm32mp1-fmc2-nfc"; 1847 reg = <4 0x00000000 0x1000>, 1848 <4 0x08010000 0x1000>, 1849 <4 0x08020000 0x1000>, 1850 <4 0x01000000 0x1000>, 1851 <4 0x09010000 0x1000>, 1852 <4 0x09020000 0x1000>; 1853 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1854 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, 1855 <&mdma1 20 0x2 0x12000a08 0x0 0x0>, 1856 <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; 1857 dma-names = "tx", "rx", "ecc"; 1858 status = "disabled"; 1859 }; 1860 }; 1861 1862 qspi: spi@58003000 { 1863 compatible = "st,stm32f469-qspi"; 1864 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; 1865 reg-names = "qspi", "qspi_mm"; 1866 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 1867 dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, 1868 <&mdma1 22 0x2 0x10100008 0x0 0x0>; 1869 dma-names = "tx", "rx"; 1870 clocks = <&rcc QSPI_K>; 1871 resets = <&rcc QSPI_R>; 1872 #address-cells = <1>; 1873 #size-cells = <0>; 1874 access-controllers = <&etzpc STM32MP1_ETZPC_QSPI_ID>; 1875 status = "disabled"; 1876 }; 1877 1878 ethernet0: ethernet@5800a000 { 1879 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; 1880 reg = <0x5800a000 0x2000>; 1881 reg-names = "stmmaceth"; 1882 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1883 interrupt-names = "macirq"; 1884 clock-names = "stmmaceth", 1885 "mac-clk-tx", 1886 "mac-clk-rx", 1887 "eth-ck", 1888 "ptp_ref", 1889 "ethstp"; 1890 clocks = <&rcc ETHMAC>, 1891 <&rcc ETHTX>, 1892 <&rcc ETHRX>, 1893 <&rcc ETHCK_K>, 1894 <&rcc ETHPTP_K>, 1895 <&rcc ETHSTP>; 1896 st,syscon = <&syscfg 0x4>; 1897 snps,mixed-burst; 1898 snps,pbl = <2>; 1899 snps,en-tx-lpi-clockgating; 1900 snps,axi-config = <&stmmac_axi_config_0>; 1901 snps,tso; 1902 access-controllers = <&etzpc STM32MP1_ETZPC_ETH_ID>; 1903 status = "disabled"; 1904 1905 stmmac_axi_config_0: stmmac-axi-config { 1906 snps,wr_osr_lmt = <0x7>; 1907 snps,rd_osr_lmt = <0x7>; 1908 snps,blen = <0 0 0 0 16 8 4>; 1909 }; 1910 }; 1911 1912 usart1: serial@5c000000 { 1913 compatible = "st,stm32h7-uart"; 1914 reg = <0x5c000000 0x400>; 1915 interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; 1916 clocks = <&rcc USART1_K>; 1917 wakeup-source; 1918 access-controllers = <&etzpc STM32MP1_ETZPC_USART1_ID>; 1919 status = "disabled"; 1920 }; 1921 1922 spi6: spi@5c001000 { 1923 #address-cells = <1>; 1924 #size-cells = <0>; 1925 compatible = "st,stm32h7-spi"; 1926 reg = <0x5c001000 0x400>; 1927 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1928 clocks = <&rcc SPI6_K>; 1929 resets = <&rcc SPI6_R>; 1930 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, 1931 <&mdma1 35 0x0 0x40002 0x0 0x0>; 1932 dma-names = "rx", "tx"; 1933 access-controllers = <&etzpc STM32MP1_ETZPC_SPI6_ID>; 1934 status = "disabled"; 1935 }; 1936 1937 i2c4: i2c@5c002000 { 1938 compatible = "st,stm32mp15-i2c"; 1939 reg = <0x5c002000 0x400>; 1940 interrupt-names = "event", "error"; 1941 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1942 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1943 clocks = <&rcc I2C4_K>; 1944 resets = <&rcc I2C4_R>; 1945 #address-cells = <1>; 1946 #size-cells = <0>; 1947 st,syscfg-fmp = <&syscfg 0x4 0x8>; 1948 wakeup-source; 1949 i2c-analog-filter; 1950 access-controllers = <&etzpc STM32MP1_ETZPC_I2C4_ID>; 1951 status = "disabled"; 1952 }; 1953 1954 iwdg1: watchdog@5c003000 { 1955 compatible = "st,stm32mp1-iwdg"; 1956 reg = <0x5C003000 0x400>; 1957 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1958 clocks = <&rcc IWDG1>, <&rcc CK_LSI>; 1959 clock-names = "pclk", "lsi"; 1960 access-controllers = <&etzpc STM32MP1_ETZPC_IWDG1_ID>; 1961 status = "disabled"; 1962 }; 1963 1964 i2c6: i2c@5c009000 { 1965 compatible = "st,stm32mp15-i2c"; 1966 reg = <0x5c009000 0x400>; 1967 interrupt-names = "event", "error"; 1968 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1969 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1970 clocks = <&rcc I2C6_K>; 1971 resets = <&rcc I2C6_R>; 1972 #address-cells = <1>; 1973 #size-cells = <0>; 1974 st,syscfg-fmp = <&syscfg 0x4 0x20>; 1975 wakeup-source; 1976 i2c-analog-filter; 1977 access-controllers = <&etzpc STM32MP1_ETZPC_I2C6_ID>; 1978 status = "disabled"; 1979 }; 1980 }; 1981 }; 1982 1983 mlahb: ahb { 1984 compatible = "st,mlahb", "simple-bus"; 1985 #address-cells = <1>; 1986 #size-cells = <1>; 1987 ranges; 1988 dma-ranges = <0x00000000 0x38000000 0x10000>, 1989 <0x10000000 0x10000000 0x60000>, 1990 <0x30000000 0x30000000 0x60000>; 1991 1992 m4_rproc: m4@10000000 { 1993 compatible = "st,stm32mp1-m4"; 1994 reg = <0x10000000 0x40000>, 1995 <0x30000000 0x40000>, 1996 <0x38000000 0x10000>; 1997 resets = <&rcc MCU_R>, <&rcc MCU_HOLD_BOOT_R>; 1998 reset-names = "mcu_rst", "hold_boot"; 1999 st,syscfg-tz = <&rcc 0x000 0x1>; 2000 st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; 2001 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; 2002 st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; 2003 status = "disabled"; 2004 }; 2005 }; 2006}; 2007