1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2021-2024 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/clock/stm32mp13-clksrc.h> 10#include <dt-bindings/firewall/stm32mp13-tzc400.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/gpio/stm32mp_gpio.h> 13#include <dt-bindings/regulator/st,stm32mp13-regulator.h> 14#include "stm32mp135.dtsi" 15#include "stm32mp13xf.dtsi" 16#include "stm32mp13-pinctrl.dtsi" 17 18/ { 19 model = "STMicroelectronics STM32MP135F-DK Discovery Board"; 20 compatible = "st,stm32mp135f-dk", "st,stm32mp135"; 21 22 aliases { 23 serial0 = &uart4; 24 serial1 = &usart1; 25 }; 26 27 chosen { 28 stdout-path = "serial0:115200n8"; 29 }; 30 31 memory@c0000000 { 32 device_type = "memory"; 33 reg = <0xc0000000 0x20000000>; 34 }; 35 36 reserved-memory { 37 #address-cells = <1>; 38 #size-cells = <1>; 39 ranges; 40 41 optee_framebuffer: optee-framebuffer@dd000000 { 42 /* Secure framebuffer memory */ 43 reg = <0xdd000000 0x1000000>; 44 st,protreg = <DT_TZC_REGION_S_RDWR 0>; 45 no-map; 46 }; 47 }; 48 49 vin: vin { 50 compatible = "regulator-fixed"; 51 regulator-name = "vin"; 52 regulator-min-microvolt = <5000000>; 53 regulator-max-microvolt = <5000000>; 54 regulator-always-on; 55 }; 56 57 v3v3_ao: v3v3_ao { 58 compatible = "regulator-fixed"; 59 regulator-name = "v3v3_ao"; 60 regulator-min-microvolt = <3300000>; 61 regulator-max-microvolt = <3300000>; 62 regulator-always-on; 63 }; 64}; 65 66&bsec { 67 board_id: board_id@f0 { 68 reg = <0xf0 0x4>; 69 st,non-secure-otp; 70 }; 71}; 72 73&etzpc { 74 st,decprot = 75 <DECPROT(STM32MP1_ETZPC_ADC1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 76 <DECPROT(STM32MP1_ETZPC_ADC2_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 77 <DECPROT(STM32MP1_ETZPC_BKPSRAM_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 78 <DECPROT(STM32MP1_ETZPC_CRYP_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 79 <DECPROT(STM32MP1_ETZPC_DCMIPP_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 80 <DECPROT(STM32MP1_ETZPC_DDRCTRLPHY_ID, DECPROT_NS_R_S_W, DECPROT_UNLOCK)>, 81 <DECPROT(STM32MP1_ETZPC_ETH1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 82 <DECPROT(STM32MP1_ETZPC_ETH2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 83 <DECPROT(STM32MP1_ETZPC_FMC_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 84 <DECPROT(STM32MP1_ETZPC_HASH_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 85 <DECPROT(STM32MP1_ETZPC_I2C3_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 86 <DECPROT(STM32MP1_ETZPC_I2C4_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 87 <DECPROT(STM32MP1_ETZPC_I2C5_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 88 <DECPROT(STM32MP1_ETZPC_IWDG1_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 89 <DECPROT(STM32MP1_ETZPC_LPTIM2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 90 <DECPROT(STM32MP1_ETZPC_LPTIM3_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 91 <DECPROT(STM32MP1_ETZPC_LTDC_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 92 <DECPROT(STM32MP1_ETZPC_MCE_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 93 <DECPROT(STM32MP1_ETZPC_OTG_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 94 <DECPROT(STM32MP1_ETZPC_PKA_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 95 <DECPROT(STM32MP1_ETZPC_QSPI_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 96 <DECPROT(STM32MP1_ETZPC_RNG_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 97 <DECPROT(STM32MP1_ETZPC_SAES_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 98 <DECPROT(STM32MP1_ETZPC_SDMMC1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 99 <DECPROT(STM32MP1_ETZPC_SDMMC2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 100 <DECPROT(STM32MP1_ETZPC_SPI4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 101 <DECPROT(STM32MP1_ETZPC_SPI5_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 102 <DECPROT(STM32MP1_ETZPC_SRAM1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 103 <DECPROT(STM32MP1_ETZPC_SRAM2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 104 <DECPROT(STM32MP1_ETZPC_SRAM3_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 105 <DECPROT(STM32MP1_ETZPC_STGENC_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 106 <DECPROT(STM32MP1_ETZPC_TIM12_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 107 <DECPROT(STM32MP1_ETZPC_TIM13_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 108 <DECPROT(STM32MP1_ETZPC_TIM14_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 109 <DECPROT(STM32MP1_ETZPC_TIM15_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 110 <DECPROT(STM32MP1_ETZPC_TIM16_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 111 <DECPROT(STM32MP1_ETZPC_TIM17_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 112 <DECPROT(STM32MP1_ETZPC_USART1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 113 <DECPROT(STM32MP1_ETZPC_USART2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 114 <DECPROT(STM32MP1_ETZPC_USBPHYCTRL_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 115 <DECPROT(STM32MP1_ETZPC_VREFBUF_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>; 116}; 117 118&gpiob { 119 st,protreg = <TZPROT(9)>; 120}; 121 122&gpiod { 123 st,protreg = <TZPROT(7)>; 124}; 125 126&gpioe { 127 st,protreg = <TZPROT(15)>; 128}; 129 130&i2c4 { 131 pinctrl-names = "default"; 132 pinctrl-0 = <&i2c4_pins_a>; 133 i2c-scl-rising-time-ns = <185>; 134 i2c-scl-falling-time-ns = <20>; 135 clock-frequency = <400000>; 136 status = "okay"; 137 138 pmic: stpmic@33 { 139 compatible = "st,stpmic1"; 140 reg = <0x33>; 141 status = "okay"; 142 st,wakeup-pin-number = <1>; 143 st,notif-it-id = <0>; 144 145 regulators { 146 compatible = "st,stpmic1-regulators"; 147 buck1-supply = <&vin>; 148 buck2-supply = <&vin>; 149 buck3-supply = <&vin>; 150 buck4-supply = <&vin>; 151 ldo1-supply = <&vin>; 152 ldo4-supply = <&vin>; 153 ldo5-supply = <&vin>; 154 ldo6-supply = <&vin>; 155 vref_ddr-supply = <&vin>; 156 pwr_sw1-supply = <&bst_out>; 157 pwr_sw2-supply = <&v3v3_ao>; 158 159 vddcpu: buck1 { 160 regulator-name = "vddcpu"; 161 regulator-min-microvolt = <1250000>; 162 regulator-max-microvolt = <1350000>; 163 regulator-always-on; 164 regulator-over-current-protection; 165 166 lp-stop { 167 regulator-suspend-microvolt = <1250000>; 168 }; 169 lplv-stop { 170 regulator-suspend-microvolt = <900000>; 171 }; 172 lplv-stop2 { 173 regulator-off-in-suspend; 174 }; 175 standby-ddr-sr { 176 regulator-off-in-suspend; 177 }; 178 standby-ddr-off { 179 regulator-off-in-suspend; 180 }; 181 }; 182 183 vdd_ddr: buck2 { 184 regulator-name = "vdd_ddr"; 185 regulator-min-microvolt = <1350000>; 186 regulator-max-microvolt = <1350000>; 187 regulator-always-on; 188 regulator-over-current-protection; 189 190 standby-ddr-off { 191 regulator-off-in-suspend; 192 }; 193 }; 194 195 vdd: buck3 { 196 regulator-name = "vdd"; 197 regulator-min-microvolt = <3300000>; 198 regulator-max-microvolt = <3300000>; 199 regulator-always-on; 200 st,mask-reset; 201 regulator-over-current-protection; 202 }; 203 204 vddcore: buck4 { 205 regulator-name = "vddcore"; 206 regulator-min-microvolt = <1250000>; 207 regulator-max-microvolt = <1250000>; 208 regulator-always-on; 209 regulator-over-current-protection; 210 211 lplv-stop { 212 regulator-suspend-microvolt = <900000>; 213 }; 214 lplv-stop2 { 215 regulator-suspend-microvolt = <900000>; 216 }; 217 standby-ddr-sr { 218 regulator-off-in-suspend; 219 }; 220 standby-ddr-off { 221 regulator-off-in-suspend; 222 }; 223 }; 224 225 vdd_adc: ldo1 { 226 regulator-name = "vdd_adc"; 227 regulator-min-microvolt = <3300000>; 228 regulator-max-microvolt = <3300000>; 229 230 standby-ddr-sr { 231 regulator-off-in-suspend; 232 }; 233 standby-ddr-off { 234 regulator-off-in-suspend; 235 }; 236 }; 237 238 unused1: ldo2 { 239 regulator-name = "ldo2"; 240 }; 241 242 unused2: ldo3 { 243 regulator-name = "ldo3"; 244 }; 245 246 vdd_usb: ldo4 { 247 regulator-name = "vdd_usb"; 248 regulator-min-microvolt = <3300000>; 249 regulator-max-microvolt = <3300000>; 250 251 standby-ddr-sr { 252 regulator-off-in-suspend; 253 }; 254 standby-ddr-off { 255 regulator-off-in-suspend; 256 }; 257 }; 258 259 vdd_sd: ldo5 { 260 regulator-name = "vdd_sd"; 261 regulator-min-microvolt = <3300000>; 262 regulator-max-microvolt = <3300000>; 263 regulator-boot-on; 264 265 standby-ddr-sr { 266 regulator-off-in-suspend; 267 }; 268 standby-ddr-off { 269 regulator-off-in-suspend; 270 }; 271 }; 272 273 v1v8_periph: ldo6 { 274 regulator-name = "v1v8_periph"; 275 regulator-min-microvolt = <1800000>; 276 regulator-max-microvolt = <1800000>; 277 278 standby-ddr-sr { 279 regulator-off-in-suspend; 280 }; 281 standby-ddr-off { 282 regulator-off-in-suspend; 283 }; 284 }; 285 286 vref_ddr: vref_ddr { 287 regulator-name = "vref_ddr"; 288 regulator-always-on; 289 290 standby-ddr-sr { 291 regulator-off-in-suspend; 292 }; 293 standby-ddr-off { 294 regulator-off-in-suspend; 295 }; 296 }; 297 298 bst_out: boost { 299 regulator-name = "bst_out"; 300 }; 301 302 v3v3_sw: pwr_sw2 { 303 regulator-name = "v3v3_sw"; 304 regulator-active-discharge = <1>; 305 regulator-min-microvolt = <3300000>; 306 regulator-max-microvolt = <3300000>; 307 }; 308 }; 309 }; 310}; 311 312&iwdg1 { 313 timeout-sec = <32>; 314 status = "okay"; 315}; 316 317&oem_enc_key { 318 st,non-secure-otp-provisioning; 319}; 320 321&pwr_regulators { 322 vdd-supply = <&vdd>; 323 vdd_3v3_usbfs-supply = <&vdd_usb>; 324}; 325 326&rcc { 327 compatible = "st,stm32mp13-rcc", "syscon"; 328 329 st,clksrc = < 330 CLK_MPU_PLL1P 331 CLK_AXI_PLL2P 332 CLK_MLAHBS_PLL3 333 CLK_RTC_LSE 334 CLK_MCO1_HSE 335 CLK_MCO2_DISABLED 336 CLK_CKPER_HSE 337 CLK_ETH1_PLL4P 338 CLK_ETH2_PLL4P 339 CLK_SDMMC1_PLL4P 340 CLK_SDMMC2_PLL4P 341 CLK_STGEN_HSE 342 CLK_USBPHY_HSE 343 CLK_I2C4_HSI 344 CLK_I2C5_HSI 345 CLK_USBO_USBPHY 346 CLK_ADC2_CKPER 347 CLK_I2C12_HSI 348 CLK_UART1_HSI 349 CLK_UART2_HSI 350 CLK_UART35_HSI 351 CLK_UART4_HSI 352 CLK_UART6_HSI 353 CLK_UART78_HSI 354 CLK_SAES_AXI 355 CLK_DCMIPP_PLL2Q 356 CLK_LPTIM3_PCLK3 357 CLK_RNG1_PLL4R 358 >; 359 360 st,clkdiv = < 361 DIV(DIV_MPU, 1) 362 DIV(DIV_AXI, 0) 363 DIV(DIV_MLAHB, 0) 364 DIV(DIV_APB1, 1) 365 DIV(DIV_APB2, 1) 366 DIV(DIV_APB3, 1) 367 DIV(DIV_APB4, 1) 368 DIV(DIV_APB5, 2) 369 DIV(DIV_APB6, 1) 370 DIV(DIV_RTC, 0) 371 DIV(DIV_MCO1, 0) 372 DIV(DIV_MCO2, 0) 373 >; 374 375 st,pll_vco { 376 pll1_vco_2000Mhz: pll1-vco-2000Mhz { 377 src = <CLK_PLL12_HSE>; 378 divmn = <1 82>; 379 frac = <0xAAA>; 380 }; 381 382 pll1_vco_1300Mhz: pll1-vco-1300Mhz { 383 src = <CLK_PLL12_HSE>; 384 divmn = <2 80>; 385 frac = <0x800>; 386 }; 387 388 pll2_vco_1066Mhz: pll2-vco-1066Mhz { 389 src = <CLK_PLL12_HSE>; 390 divmn = <2 65>; 391 frac = <0x1400>; 392 }; 393 394 pll3_vco_417Mhz: pll3-vco-417Mhz { 395 src = <CLK_PLL3_HSE>; 396 divmn = <1 33>; 397 frac = <0x1a04>; 398 }; 399 400 pll4_vco_600Mhz: pll4-vco-600Mhz { 401 src = <CLK_PLL4_HSE>; 402 divmn = <1 49>; 403 }; 404 }; 405 406 /* VCO = 1300.0 MHz => P = 650 (CPU) */ 407 pll1: st,pll@0 { 408 compatible = "st,stm32mp1-pll"; 409 reg = <0>; 410 411 st,pll = <&pll1_cfg1>; 412 413 pll1_cfg1: pll1_cfg1 { 414 st,pll_vco = <&pll1_vco_1300Mhz>; 415 st,pll_div_pqr = <0 1 1>; 416 }; 417 418 pll1_cfg2: pll1_cfg2 { 419 st,pll_vco = <&pll1_vco_2000Mhz>; 420 st,pll_div_pqr = <0 1 1>; 421 }; 422 }; 423 424 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 266, R = 533 (DDR) */ 425 pll2: st,pll@1 { 426 compatible = "st,stm32mp1-pll"; 427 reg = <1>; 428 429 st,pll = <&pll2_cfg1>; 430 431 pll2_cfg1: pll2_cfg1 { 432 st,pll_vco = <&pll2_vco_1066Mhz>; 433 st,pll_div_pqr = <1 1 0>; 434 }; 435 }; 436 437 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 438 pll3: st,pll@2 { 439 compatible = "st,stm32mp1-pll"; 440 reg = <2>; 441 442 st,pll = <&pll3_cfg1>; 443 444 pll3_cfg1: pll3_cfg1 { 445 st,pll_vco = <&pll3_vco_417Mhz>; 446 st,pll_div_pqr = <1 16 36>; 447 }; 448 }; 449 450 /* VCO = 600.0 MHz => P = 50, Q = 10, R = 50 */ 451 pll4: st,pll@3 { 452 compatible = "st,stm32mp1-pll"; 453 reg = <3>; 454 st,pll = <&pll4_cfg1>; 455 456 pll4_cfg1: pll4_cfg1 { 457 st,pll_vco = <&pll4_vco_600Mhz>; 458 st,pll_div_pqr = <11 59 11>; 459 }; 460 }; 461 462 st,clk_opp { 463 /* CK_MPU clock config for MP13 */ 464 st,ck_mpu { 465 466 cfg_1 { 467 hz = <650000000>; 468 st,clksrc = <CLK_MPU_PLL1P>; 469 st,pll = <&pll1_cfg1>; 470 }; 471 472 cfg_2 { 473 hz = <1000000000>; 474 st,clksrc = <CLK_MPU_PLL1P>; 475 st,pll = <&pll1_cfg2>; 476 }; 477 }; 478 }; 479}; 480 481&rng { 482 status = "okay"; 483 clock-error-detect; 484}; 485 486&rtc { 487 status = "okay"; 488}; 489 490&saes { 491 status = "okay"; 492}; 493 494&sdmmc1_io { 495 vddsd1-supply = <&vdd>; 496}; 497 498&sdmmc2_io { 499 vddsd2-supply = <&vdd>; 500}; 501 502&tzc400 { 503 memory-region = <&optee_framebuffer>; 504}; 505 506&uart4 { 507 pinctrl-names = "default"; 508 pinctrl-0 = <&uart4_pins_a>; 509 status = "okay"; 510}; 511 512&usart1 { 513 pinctrl-names = "default"; 514 pinctrl-0 = <&usart1_pins_a>; 515 uart-has-rtscts; 516 status = "disabled"; 517}; 518