1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2021-2023 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/clock/stm32mp13-clksrc.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/gpio/stm32mp_gpio.h> 12#include <dt-bindings/regulator/st,stm32mp13-regulator.h> 13#include "stm32mp135.dtsi" 14#include "stm32mp13xf.dtsi" 15#include "stm32mp13-pinctrl.dtsi" 16 17/ { 18 model = "STMicroelectronics STM32MP135F-DK Discovery Board"; 19 compatible = "st,stm32mp135f-dk", "st,stm32mp135"; 20 21 aliases { 22 serial0 = &uart4; 23 serial1 = &usart1; 24 }; 25 26 chosen { 27 stdout-path = "serial0:115200n8"; 28 }; 29 30 memory@c0000000 { 31 device_type = "memory"; 32 reg = <0xc0000000 0x20000000>; 33 }; 34 35 reserved-memory { 36 #address-cells = <1>; 37 #size-cells = <1>; 38 ranges; 39 40 optee_framebuffer: optee-framebuffer@dd000000 { 41 /* Secure framebuffer memory */ 42 reg = <0xdd000000 0x1000000>; 43 no-map; 44 }; 45 }; 46 47 vin: vin { 48 compatible = "regulator-fixed"; 49 regulator-name = "vin"; 50 regulator-min-microvolt = <5000000>; 51 regulator-max-microvolt = <5000000>; 52 regulator-always-on; 53 }; 54 55 v3v3_ao: v3v3_ao { 56 compatible = "regulator-fixed"; 57 regulator-name = "v3v3_ao"; 58 regulator-min-microvolt = <3300000>; 59 regulator-max-microvolt = <3300000>; 60 regulator-always-on; 61 }; 62}; 63 64&adc_2 { 65 vdda-supply = <&vdd_adc>; 66 vref-supply = <&vdd_adc>; 67 status = "okay"; 68 69 adc2: adc@0 { 70 status = "okay"; 71 72 channel@15 { 73 reg = <15>; 74 label = "vbat"; 75 }; 76 }; 77}; 78 79&bsec { 80 board_id: board_id@f0 { 81 reg = <0xf0 0x4>; 82 st,non-secure-otp; 83 }; 84}; 85 86&gpiob { 87 st,protreg = <TZPROT(9)>; 88}; 89 90&gpiod { 91 st,protreg = <TZPROT(7)>; 92}; 93 94&gpioe { 95 st,protreg = <TZPROT(15)>; 96}; 97 98&i2c4 { 99 pinctrl-names = "default"; 100 pinctrl-0 = <&i2c4_pins_a>; 101 i2c-scl-rising-time-ns = <185>; 102 i2c-scl-falling-time-ns = <20>; 103 clock-frequency = <400000>; 104 status = "okay"; 105 106 pmic: stpmic@33 { 107 compatible = "st,stpmic1"; 108 reg = <0x33>; 109 status = "okay"; 110 st,wakeup-pin-number = <1>; 111 st,notif-it-id = <0>; 112 113 regulators { 114 compatible = "st,stpmic1-regulators"; 115 buck1-supply = <&vin>; 116 buck2-supply = <&vin>; 117 buck3-supply = <&vin>; 118 buck4-supply = <&vin>; 119 ldo1-supply = <&vin>; 120 ldo4-supply = <&vin>; 121 ldo5-supply = <&vin>; 122 ldo6-supply = <&vin>; 123 vref_ddr-supply = <&vin>; 124 pwr_sw1-supply = <&bst_out>; 125 pwr_sw2-supply = <&v3v3_ao>; 126 127 vddcpu: buck1 { 128 regulator-name = "vddcpu"; 129 regulator-min-microvolt = <1250000>; 130 regulator-max-microvolt = <1350000>; 131 regulator-always-on; 132 regulator-over-current-protection; 133 134 lp-stop { 135 regulator-suspend-microvolt = <1250000>; 136 }; 137 lplv-stop { 138 regulator-suspend-microvolt = <900000>; 139 }; 140 lplv-stop2 { 141 regulator-off-in-suspend; 142 }; 143 standby-ddr-sr { 144 regulator-off-in-suspend; 145 }; 146 standby-ddr-off { 147 regulator-off-in-suspend; 148 }; 149 }; 150 151 vdd_ddr: buck2 { 152 regulator-name = "vdd_ddr"; 153 regulator-min-microvolt = <1350000>; 154 regulator-max-microvolt = <1350000>; 155 regulator-always-on; 156 regulator-over-current-protection; 157 158 standby-ddr-off { 159 regulator-off-in-suspend; 160 }; 161 }; 162 163 vdd: buck3 { 164 regulator-name = "vdd"; 165 regulator-min-microvolt = <3300000>; 166 regulator-max-microvolt = <3300000>; 167 regulator-always-on; 168 st,mask-reset; 169 regulator-over-current-protection; 170 }; 171 172 vddcore: buck4 { 173 regulator-name = "vddcore"; 174 regulator-min-microvolt = <1250000>; 175 regulator-max-microvolt = <1250000>; 176 regulator-always-on; 177 regulator-over-current-protection; 178 179 lplv-stop { 180 regulator-suspend-microvolt = <900000>; 181 }; 182 lplv-stop2 { 183 regulator-suspend-microvolt = <900000>; 184 }; 185 standby-ddr-sr { 186 regulator-off-in-suspend; 187 }; 188 standby-ddr-off { 189 regulator-off-in-suspend; 190 }; 191 }; 192 193 vdd_adc: ldo1 { 194 regulator-name = "vdd_adc"; 195 regulator-min-microvolt = <3300000>; 196 regulator-max-microvolt = <3300000>; 197 198 standby-ddr-sr { 199 regulator-off-in-suspend; 200 }; 201 standby-ddr-off { 202 regulator-off-in-suspend; 203 }; 204 }; 205 206 unused1: ldo2 { 207 regulator-name = "ldo2"; 208 }; 209 210 unused2: ldo3 { 211 regulator-name = "ldo3"; 212 }; 213 214 vdd_usb: ldo4 { 215 regulator-name = "vdd_usb"; 216 regulator-min-microvolt = <3300000>; 217 regulator-max-microvolt = <3300000>; 218 219 standby-ddr-sr { 220 regulator-off-in-suspend; 221 }; 222 standby-ddr-off { 223 regulator-off-in-suspend; 224 }; 225 }; 226 227 vdd_sd: ldo5 { 228 regulator-name = "vdd_sd"; 229 regulator-min-microvolt = <3300000>; 230 regulator-max-microvolt = <3300000>; 231 regulator-boot-on; 232 233 standby-ddr-sr { 234 regulator-off-in-suspend; 235 }; 236 standby-ddr-off { 237 regulator-off-in-suspend; 238 }; 239 }; 240 241 v1v8_periph: ldo6 { 242 regulator-name = "v1v8_periph"; 243 regulator-min-microvolt = <1800000>; 244 regulator-max-microvolt = <1800000>; 245 246 standby-ddr-sr { 247 regulator-off-in-suspend; 248 }; 249 standby-ddr-off { 250 regulator-off-in-suspend; 251 }; 252 }; 253 254 vref_ddr: vref_ddr { 255 regulator-name = "vref_ddr"; 256 regulator-always-on; 257 258 standby-ddr-sr { 259 regulator-off-in-suspend; 260 }; 261 standby-ddr-off { 262 regulator-off-in-suspend; 263 }; 264 }; 265 266 bst_out: boost { 267 regulator-name = "bst_out"; 268 }; 269 270 v3v3_sw: pwr_sw2 { 271 regulator-name = "v3v3_sw"; 272 regulator-active-discharge = <1>; 273 regulator-min-microvolt = <3300000>; 274 regulator-max-microvolt = <3300000>; 275 }; 276 }; 277 }; 278}; 279 280&iwdg1 { 281 timeout-sec = <32>; 282 status = "okay"; 283}; 284 285&oem_enc_key { 286 st,non-secure-otp-provisioning; 287}; 288 289&pwr_regulators { 290 vdd-supply = <&vdd>; 291 vdd_3v3_usbfs-supply = <&vdd_usb>; 292}; 293 294&rcc { 295 compatible = "st,stm32mp13-rcc", "syscon"; 296 297 st,clksrc = < 298 CLK_MPU_PLL1P 299 CLK_AXI_PLL2P 300 CLK_MLAHBS_PLL3 301 CLK_RTC_LSE 302 CLK_MCO1_HSE 303 CLK_MCO2_DISABLED 304 CLK_CKPER_HSE 305 CLK_ETH1_PLL4P 306 CLK_ETH2_PLL4P 307 CLK_SDMMC1_PLL4P 308 CLK_SDMMC2_PLL4P 309 CLK_STGEN_HSE 310 CLK_USBPHY_HSE 311 CLK_I2C4_HSI 312 CLK_I2C5_HSI 313 CLK_USBO_USBPHY 314 CLK_ADC2_CKPER 315 CLK_I2C12_HSI 316 CLK_UART1_HSI 317 CLK_UART2_HSI 318 CLK_UART35_HSI 319 CLK_UART4_HSI 320 CLK_UART6_HSI 321 CLK_UART78_HSI 322 CLK_SAES_AXI 323 CLK_DCMIPP_PLL2Q 324 CLK_LPTIM3_PCLK3 325 CLK_RNG1_PLL4R 326 >; 327 328 st,clkdiv = < 329 DIV(DIV_MPU, 1) 330 DIV(DIV_AXI, 0) 331 DIV(DIV_MLAHB, 0) 332 DIV(DIV_APB1, 1) 333 DIV(DIV_APB2, 1) 334 DIV(DIV_APB3, 1) 335 DIV(DIV_APB4, 1) 336 DIV(DIV_APB5, 2) 337 DIV(DIV_APB6, 1) 338 DIV(DIV_RTC, 0) 339 DIV(DIV_MCO1, 0) 340 DIV(DIV_MCO2, 0) 341 >; 342 343 st,pll_vco { 344 pll1_vco_2000Mhz: pll1-vco-2000Mhz { 345 src = <CLK_PLL12_HSE>; 346 divmn = <1 82>; 347 frac = <0xAAA>; 348 }; 349 350 pll1_vco_1300Mhz: pll1-vco-1300Mhz { 351 src = <CLK_PLL12_HSE>; 352 divmn = <2 80>; 353 frac = <0x800>; 354 }; 355 356 pll2_vco_1066Mhz: pll2-vco-1066Mhz { 357 src = <CLK_PLL12_HSE>; 358 divmn = <2 65>; 359 frac = <0x1400>; 360 }; 361 362 pll3_vco_417Mhz: pll3-vco-417Mhz { 363 src = <CLK_PLL3_HSE>; 364 divmn = <1 33>; 365 frac = <0x1a04>; 366 }; 367 368 pll4_vco_600Mhz: pll4-vco-600Mhz { 369 src = <CLK_PLL4_HSE>; 370 divmn = <1 49>; 371 }; 372 }; 373 374 /* VCO = 1300.0 MHz => P = 650 (CPU) */ 375 pll1: st,pll@0 { 376 compatible = "st,stm32mp1-pll"; 377 reg = <0>; 378 379 st,pll = <&pll1_cfg1>; 380 381 pll1_cfg1: pll1_cfg1 { 382 st,pll_vco = <&pll1_vco_1300Mhz>; 383 st,pll_div_pqr = <0 1 1>; 384 }; 385 386 pll1_cfg2: pll1_cfg2 { 387 st,pll_vco = <&pll1_vco_2000Mhz>; 388 st,pll_div_pqr = <0 1 1>; 389 }; 390 }; 391 392 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 266, R = 533 (DDR) */ 393 pll2: st,pll@1 { 394 compatible = "st,stm32mp1-pll"; 395 reg = <1>; 396 397 st,pll = <&pll2_cfg1>; 398 399 pll2_cfg1: pll2_cfg1 { 400 st,pll_vco = <&pll2_vco_1066Mhz>; 401 st,pll_div_pqr = <1 1 0>; 402 }; 403 }; 404 405 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 406 pll3: st,pll@2 { 407 compatible = "st,stm32mp1-pll"; 408 reg = <2>; 409 410 st,pll = <&pll3_cfg1>; 411 412 pll3_cfg1: pll3_cfg1 { 413 st,pll_vco = <&pll3_vco_417Mhz>; 414 st,pll_div_pqr = <1 16 36>; 415 }; 416 }; 417 418 /* VCO = 600.0 MHz => P = 50, Q = 10, R = 50 */ 419 pll4: st,pll@3 { 420 compatible = "st,stm32mp1-pll"; 421 reg = <3>; 422 st,pll = <&pll4_cfg1>; 423 424 pll4_cfg1: pll4_cfg1 { 425 st,pll_vco = <&pll4_vco_600Mhz>; 426 st,pll_div_pqr = <11 59 11>; 427 }; 428 }; 429 430 st,clk_opp { 431 /* CK_MPU clock config for MP13 */ 432 st,ck_mpu { 433 434 cfg_1 { 435 hz = <650000000>; 436 st,clksrc = <CLK_MPU_PLL1P>; 437 st,pll = <&pll1_cfg1>; 438 }; 439 440 cfg_2 { 441 hz = <1000000000>; 442 st,clksrc = <CLK_MPU_PLL1P>; 443 st,pll = <&pll1_cfg2>; 444 }; 445 }; 446 }; 447}; 448 449&rng { 450 status = "okay"; 451 clock-error-detect; 452}; 453 454&rtc { 455 status = "okay"; 456}; 457 458&saes { 459 status = "okay"; 460}; 461 462&sdmmc1_io { 463 vddsd1-supply = <&vdd>; 464}; 465 466&sdmmc2_io { 467 vddsd2-supply = <&vdd>; 468}; 469 470&uart4 { 471 pinctrl-names = "default"; 472 pinctrl-0 = <&uart4_pins_a>; 473 status = "okay"; 474}; 475 476&usart1 { 477 pinctrl-names = "default"; 478 pinctrl-0 = <&usart1_pins_a>; 479 uart-has-rtscts; 480 status = "disabled"; 481}; 482