1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2021-2023 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/clock/stm32mp13-clksrc.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/regulator/st,stm32mp13-regulator.h> 12#include "stm32mp135.dtsi" 13#include "stm32mp13xf.dtsi" 14#include "stm32mp13-pinctrl.dtsi" 15 16/ { 17 model = "STMicroelectronics STM32MP135F-DK Discovery Board"; 18 compatible = "st,stm32mp135f-dk", "st,stm32mp135"; 19 20 aliases { 21 serial0 = &uart4; 22 serial1 = &usart1; 23 }; 24 25 chosen { 26 stdout-path = "serial0:115200n8"; 27 }; 28 29 memory@c0000000 { 30 device_type = "memory"; 31 reg = <0xc0000000 0x20000000>; 32 }; 33 34 reserved-memory { 35 #address-cells = <1>; 36 #size-cells = <1>; 37 ranges; 38 39 optee_framebuffer: optee-framebuffer@dd000000 { 40 /* Secure framebuffer memory */ 41 reg = <0xdd000000 0x1000000>; 42 no-map; 43 }; 44 }; 45 46 vin: vin { 47 compatible = "regulator-fixed"; 48 regulator-name = "vin"; 49 regulator-min-microvolt = <5000000>; 50 regulator-max-microvolt = <5000000>; 51 regulator-always-on; 52 }; 53 54 v3v3_ao: v3v3_ao { 55 compatible = "regulator-fixed"; 56 regulator-name = "v3v3_ao"; 57 regulator-min-microvolt = <3300000>; 58 regulator-max-microvolt = <3300000>; 59 regulator-always-on; 60 }; 61}; 62 63&adc_2 { 64 vdda-supply = <&vdd_adc>; 65 vref-supply = <&vdd_adc>; 66 status = "okay"; 67 68 adc2: adc@0 { 69 status = "okay"; 70 71 channel@15 { 72 reg = <15>; 73 label = "vbat"; 74 }; 75 }; 76}; 77 78&bsec { 79 board_id: board_id@f0 { 80 reg = <0xf0 0x4>; 81 st,non-secure-otp; 82 }; 83}; 84 85&i2c4 { 86 pinctrl-names = "default"; 87 pinctrl-0 = <&i2c4_pins_a>; 88 i2c-scl-rising-time-ns = <185>; 89 i2c-scl-falling-time-ns = <20>; 90 clock-frequency = <400000>; 91 status = "okay"; 92 93 pmic: stpmic@33 { 94 compatible = "st,stpmic1"; 95 reg = <0x33>; 96 status = "okay"; 97 st,wakeup-pin-number = <1>; 98 st,notif-it-id = <0>; 99 100 regulators { 101 compatible = "st,stpmic1-regulators"; 102 buck1-supply = <&vin>; 103 buck2-supply = <&vin>; 104 buck3-supply = <&vin>; 105 buck4-supply = <&vin>; 106 ldo1-supply = <&vin>; 107 ldo4-supply = <&vin>; 108 ldo5-supply = <&vin>; 109 ldo6-supply = <&vin>; 110 vref_ddr-supply = <&vin>; 111 pwr_sw1-supply = <&bst_out>; 112 pwr_sw2-supply = <&v3v3_ao>; 113 114 vddcpu: buck1 { 115 regulator-name = "vddcpu"; 116 regulator-min-microvolt = <1250000>; 117 regulator-max-microvolt = <1350000>; 118 regulator-always-on; 119 regulator-over-current-protection; 120 121 lp-stop { 122 regulator-suspend-microvolt = <1250000>; 123 }; 124 lplv-stop { 125 regulator-suspend-microvolt = <900000>; 126 }; 127 lplv-stop2 { 128 regulator-off-in-suspend; 129 }; 130 standby-ddr-sr { 131 regulator-off-in-suspend; 132 }; 133 standby-ddr-off { 134 regulator-off-in-suspend; 135 }; 136 }; 137 138 vdd_ddr: buck2 { 139 regulator-name = "vdd_ddr"; 140 regulator-min-microvolt = <1350000>; 141 regulator-max-microvolt = <1350000>; 142 regulator-always-on; 143 regulator-over-current-protection; 144 145 standby-ddr-off { 146 regulator-off-in-suspend; 147 }; 148 }; 149 150 vdd: buck3 { 151 regulator-name = "vdd"; 152 regulator-min-microvolt = <3300000>; 153 regulator-max-microvolt = <3300000>; 154 regulator-always-on; 155 st,mask-reset; 156 regulator-over-current-protection; 157 }; 158 159 vddcore: buck4 { 160 regulator-name = "vddcore"; 161 regulator-min-microvolt = <1250000>; 162 regulator-max-microvolt = <1250000>; 163 regulator-always-on; 164 regulator-over-current-protection; 165 166 lplv-stop { 167 regulator-suspend-microvolt = <900000>; 168 }; 169 lplv-stop2 { 170 regulator-suspend-microvolt = <900000>; 171 }; 172 standby-ddr-sr { 173 regulator-off-in-suspend; 174 }; 175 standby-ddr-off { 176 regulator-off-in-suspend; 177 }; 178 }; 179 180 vdd_adc: ldo1 { 181 regulator-name = "vdd_adc"; 182 regulator-min-microvolt = <3300000>; 183 regulator-max-microvolt = <3300000>; 184 185 standby-ddr-sr { 186 regulator-off-in-suspend; 187 }; 188 standby-ddr-off { 189 regulator-off-in-suspend; 190 }; 191 }; 192 193 unused1: ldo2 { 194 regulator-name = "ldo2"; 195 }; 196 197 unused2: ldo3 { 198 regulator-name = "ldo3"; 199 }; 200 201 vdd_usb: ldo4 { 202 regulator-name = "vdd_usb"; 203 regulator-min-microvolt = <3300000>; 204 regulator-max-microvolt = <3300000>; 205 206 standby-ddr-sr { 207 regulator-off-in-suspend; 208 }; 209 standby-ddr-off { 210 regulator-off-in-suspend; 211 }; 212 }; 213 214 vdd_sd: ldo5 { 215 regulator-name = "vdd_sd"; 216 regulator-min-microvolt = <3300000>; 217 regulator-max-microvolt = <3300000>; 218 regulator-boot-on; 219 220 standby-ddr-sr { 221 regulator-off-in-suspend; 222 }; 223 standby-ddr-off { 224 regulator-off-in-suspend; 225 }; 226 }; 227 228 v1v8_periph: ldo6 { 229 regulator-name = "v1v8_periph"; 230 regulator-min-microvolt = <1800000>; 231 regulator-max-microvolt = <1800000>; 232 233 standby-ddr-sr { 234 regulator-off-in-suspend; 235 }; 236 standby-ddr-off { 237 regulator-off-in-suspend; 238 }; 239 }; 240 241 vref_ddr: vref_ddr { 242 regulator-name = "vref_ddr"; 243 regulator-always-on; 244 245 standby-ddr-sr { 246 regulator-off-in-suspend; 247 }; 248 standby-ddr-off { 249 regulator-off-in-suspend; 250 }; 251 }; 252 253 bst_out: boost { 254 regulator-name = "bst_out"; 255 }; 256 257 v3v3_sw: pwr_sw2 { 258 regulator-name = "v3v3_sw"; 259 regulator-active-discharge = <1>; 260 regulator-min-microvolt = <3300000>; 261 regulator-max-microvolt = <3300000>; 262 }; 263 }; 264 }; 265}; 266 267&iwdg1 { 268 timeout-sec = <32>; 269 status = "okay"; 270}; 271 272&oem_enc_key { 273 st,non-secure-otp-provisioning; 274}; 275 276&pwr_regulators { 277 vdd-supply = <&vdd>; 278 vdd_3v3_usbfs-supply = <&vdd_usb>; 279}; 280 281&rcc { 282 compatible = "st,stm32mp13-rcc", "syscon"; 283 284 st,clksrc = < 285 CLK_MPU_PLL1P 286 CLK_AXI_PLL2P 287 CLK_MLAHBS_PLL3 288 CLK_RTC_LSE 289 CLK_MCO1_HSE 290 CLK_MCO2_DISABLED 291 CLK_CKPER_HSE 292 CLK_ETH1_PLL4P 293 CLK_ETH2_PLL4P 294 CLK_SDMMC1_PLL4P 295 CLK_SDMMC2_PLL4P 296 CLK_STGEN_HSE 297 CLK_USBPHY_HSE 298 CLK_I2C4_HSI 299 CLK_I2C5_HSI 300 CLK_USBO_USBPHY 301 CLK_ADC2_CKPER 302 CLK_I2C12_HSI 303 CLK_UART1_HSI 304 CLK_UART2_HSI 305 CLK_UART35_HSI 306 CLK_UART4_HSI 307 CLK_UART6_HSI 308 CLK_UART78_HSI 309 CLK_SAES_AXI 310 CLK_DCMIPP_PLL2Q 311 CLK_LPTIM3_PCLK3 312 CLK_RNG1_PLL4R 313 >; 314 315 st,clkdiv = < 316 DIV(DIV_MPU, 1) 317 DIV(DIV_AXI, 0) 318 DIV(DIV_MLAHB, 0) 319 DIV(DIV_APB1, 1) 320 DIV(DIV_APB2, 1) 321 DIV(DIV_APB3, 1) 322 DIV(DIV_APB4, 1) 323 DIV(DIV_APB5, 2) 324 DIV(DIV_APB6, 1) 325 DIV(DIV_RTC, 0) 326 DIV(DIV_MCO1, 0) 327 DIV(DIV_MCO2, 0) 328 >; 329 330 st,pll_vco { 331 pll1_vco_2000Mhz: pll1-vco-2000Mhz { 332 src = <CLK_PLL12_HSE>; 333 divmn = <1 82>; 334 frac = <0xAAA>; 335 }; 336 337 pll1_vco_1300Mhz: pll1-vco-1300Mhz { 338 src = <CLK_PLL12_HSE>; 339 divmn = <2 80>; 340 frac = <0x800>; 341 }; 342 343 pll2_vco_1066Mhz: pll2-vco-1066Mhz { 344 src = <CLK_PLL12_HSE>; 345 divmn = <2 65>; 346 frac = <0x1400>; 347 }; 348 349 pll3_vco_417Mhz: pll3-vco-417Mhz { 350 src = <CLK_PLL3_HSE>; 351 divmn = <1 33>; 352 frac = <0x1a04>; 353 }; 354 355 pll4_vco_600Mhz: pll4-vco-600Mhz { 356 src = <CLK_PLL4_HSE>; 357 divmn = <1 49>; 358 }; 359 }; 360 361 /* VCO = 1300.0 MHz => P = 650 (CPU) */ 362 pll1: st,pll@0 { 363 compatible = "st,stm32mp1-pll"; 364 reg = <0>; 365 366 st,pll = <&pll1_cfg1>; 367 368 pll1_cfg1: pll1_cfg1 { 369 st,pll_vco = <&pll1_vco_1300Mhz>; 370 st,pll_div_pqr = <0 1 1>; 371 }; 372 373 pll1_cfg2: pll1_cfg2 { 374 st,pll_vco = <&pll1_vco_2000Mhz>; 375 st,pll_div_pqr = <0 1 1>; 376 }; 377 }; 378 379 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 266, R = 533 (DDR) */ 380 pll2: st,pll@1 { 381 compatible = "st,stm32mp1-pll"; 382 reg = <1>; 383 384 st,pll = <&pll2_cfg1>; 385 386 pll2_cfg1: pll2_cfg1 { 387 st,pll_vco = <&pll2_vco_1066Mhz>; 388 st,pll_div_pqr = <1 1 0>; 389 }; 390 }; 391 392 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 393 pll3: st,pll@2 { 394 compatible = "st,stm32mp1-pll"; 395 reg = <2>; 396 397 st,pll = <&pll3_cfg1>; 398 399 pll3_cfg1: pll3_cfg1 { 400 st,pll_vco = <&pll3_vco_417Mhz>; 401 st,pll_div_pqr = <1 16 36>; 402 }; 403 }; 404 405 /* VCO = 600.0 MHz => P = 50, Q = 10, R = 50 */ 406 pll4: st,pll@3 { 407 compatible = "st,stm32mp1-pll"; 408 reg = <3>; 409 st,pll = <&pll4_cfg1>; 410 411 pll4_cfg1: pll4_cfg1 { 412 st,pll_vco = <&pll4_vco_600Mhz>; 413 st,pll_div_pqr = <11 59 11>; 414 }; 415 }; 416 417 st,clk_opp { 418 /* CK_MPU clock config for MP13 */ 419 st,ck_mpu { 420 421 cfg_1 { 422 hz = <650000000>; 423 st,clksrc = <CLK_MPU_PLL1P>; 424 st,pll = <&pll1_cfg1>; 425 }; 426 427 cfg_2 { 428 hz = <1000000000>; 429 st,clksrc = <CLK_MPU_PLL1P>; 430 st,pll = <&pll1_cfg2>; 431 }; 432 }; 433 }; 434}; 435 436&rng { 437 status = "okay"; 438 clock-error-detect; 439}; 440 441&rtc { 442 status = "okay"; 443}; 444 445&saes { 446 status = "okay"; 447}; 448 449&sdmmc1_io { 450 vddsd1-supply = <&vdd>; 451}; 452 453&sdmmc2_io { 454 vddsd2-supply = <&vdd>; 455}; 456 457&uart4 { 458 pinctrl-names = "default"; 459 pinctrl-0 = <&uart4_pins_a>; 460 status = "okay"; 461}; 462 463&usart1 { 464 pinctrl-names = "default"; 465 pinctrl-0 = <&usart1_pins_a>; 466 uart-has-rtscts; 467 status = "disabled"; 468}; 469