1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2021-2024 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/clock/stm32mp13-clksrc.h> 10#include <dt-bindings/firewall/stm32mp13-tzc400.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/gpio/stm32mp_gpio.h> 13#include <dt-bindings/regulator/st,stm32mp13-regulator.h> 14#include "stm32mp135.dtsi" 15#include "stm32mp13xf.dtsi" 16#include "stm32mp13-pinctrl.dtsi" 17 18/ { 19 model = "STMicroelectronics STM32MP135F-DK Discovery Board"; 20 compatible = "st,stm32mp135f-dk", "st,stm32mp135"; 21 22 aliases { 23 serial0 = &uart4; 24 serial1 = &usart1; 25 }; 26 27 chosen { 28 stdout-path = "serial0:115200n8"; 29 }; 30 31 memory@c0000000 { 32 device_type = "memory"; 33 reg = <0xc0000000 0x20000000>; 34 }; 35 36 reserved-memory { 37 #address-cells = <1>; 38 #size-cells = <1>; 39 ranges; 40 41 optee_framebuffer: optee-framebuffer@dd000000 { 42 /* Secure framebuffer memory */ 43 reg = <0xdd000000 0x1000000>; 44 st,protreg = <DT_TZC_REGION_S_RDWR 0>; 45 no-map; 46 }; 47 }; 48 49 vin: vin { 50 compatible = "regulator-fixed"; 51 regulator-name = "vin"; 52 regulator-min-microvolt = <5000000>; 53 regulator-max-microvolt = <5000000>; 54 regulator-always-on; 55 }; 56 57 v3v3_ao: v3v3_ao { 58 compatible = "regulator-fixed"; 59 regulator-name = "v3v3_ao"; 60 regulator-min-microvolt = <3300000>; 61 regulator-max-microvolt = <3300000>; 62 regulator-always-on; 63 }; 64}; 65 66&bsec { 67 board_id: board_id@f0 { 68 reg = <0xf0 0x4>; 69 st,non-secure-otp; 70 }; 71}; 72 73&cpu0 { 74 cpu-supply = <&vddcpu>; 75}; 76 77&etzpc { 78 st,decprot = 79 <DECPROT(STM32MP1_ETZPC_ADC1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 80 <DECPROT(STM32MP1_ETZPC_ADC2_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 81 <DECPROT(STM32MP1_ETZPC_BKPSRAM_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 82 <DECPROT(STM32MP1_ETZPC_CRYP_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 83 <DECPROT(STM32MP1_ETZPC_DCMIPP_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 84 <DECPROT(STM32MP1_ETZPC_DDRCTRLPHY_ID, DECPROT_NS_R_S_W, DECPROT_UNLOCK)>, 85 <DECPROT(STM32MP1_ETZPC_ETH1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 86 <DECPROT(STM32MP1_ETZPC_ETH2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 87 <DECPROT(STM32MP1_ETZPC_FMC_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 88 <DECPROT(STM32MP1_ETZPC_HASH_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 89 <DECPROT(STM32MP1_ETZPC_I2C3_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 90 <DECPROT(STM32MP1_ETZPC_I2C4_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 91 <DECPROT(STM32MP1_ETZPC_I2C5_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 92 <DECPROT(STM32MP1_ETZPC_IWDG1_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 93 <DECPROT(STM32MP1_ETZPC_LPTIM2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 94 <DECPROT(STM32MP1_ETZPC_LPTIM3_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 95 <DECPROT(STM32MP1_ETZPC_LTDC_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 96 <DECPROT(STM32MP1_ETZPC_MCE_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 97 <DECPROT(STM32MP1_ETZPC_OTG_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 98 <DECPROT(STM32MP1_ETZPC_PKA_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 99 <DECPROT(STM32MP1_ETZPC_QSPI_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 100 <DECPROT(STM32MP1_ETZPC_RNG_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 101 <DECPROT(STM32MP1_ETZPC_SAES_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 102 <DECPROT(STM32MP1_ETZPC_SDMMC1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 103 <DECPROT(STM32MP1_ETZPC_SDMMC2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 104 <DECPROT(STM32MP1_ETZPC_SPI4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 105 <DECPROT(STM32MP1_ETZPC_SPI5_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 106 <DECPROT(STM32MP1_ETZPC_SRAM1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 107 <DECPROT(STM32MP1_ETZPC_SRAM2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 108 <DECPROT(STM32MP1_ETZPC_SRAM3_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 109 <DECPROT(STM32MP1_ETZPC_STGENC_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 110 <DECPROT(STM32MP1_ETZPC_TIM12_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 111 <DECPROT(STM32MP1_ETZPC_TIM13_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 112 <DECPROT(STM32MP1_ETZPC_TIM14_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 113 <DECPROT(STM32MP1_ETZPC_TIM15_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 114 <DECPROT(STM32MP1_ETZPC_TIM16_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 115 <DECPROT(STM32MP1_ETZPC_TIM17_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 116 <DECPROT(STM32MP1_ETZPC_USART1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 117 <DECPROT(STM32MP1_ETZPC_USART2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 118 <DECPROT(STM32MP1_ETZPC_USBPHYCTRL_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 119 <DECPROT(STM32MP1_ETZPC_VREFBUF_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>; 120}; 121 122&gpiob { 123 st,protreg = <TZPROT(9)>; 124}; 125 126&gpiod { 127 st,protreg = <TZPROT(7)>; 128}; 129 130&gpioe { 131 st,protreg = <TZPROT(15)>; 132}; 133 134&hash { 135 status = "okay"; 136}; 137 138&i2c4 { 139 pinctrl-names = "default"; 140 pinctrl-0 = <&i2c4_pins_a>; 141 i2c-scl-rising-time-ns = <185>; 142 i2c-scl-falling-time-ns = <20>; 143 clock-frequency = <400000>; 144 status = "okay"; 145 146 pmic: stpmic@33 { 147 compatible = "st,stpmic1"; 148 reg = <0x33>; 149 status = "okay"; 150 st,wakeup-pin-number = <1>; 151 st,notif-it-id = <0>; 152 153 regulators { 154 compatible = "st,stpmic1-regulators"; 155 buck1-supply = <&vin>; 156 buck2-supply = <&vin>; 157 buck3-supply = <&vin>; 158 buck4-supply = <&vin>; 159 ldo1-supply = <&vin>; 160 ldo4-supply = <&vin>; 161 ldo5-supply = <&vin>; 162 ldo6-supply = <&vin>; 163 vref_ddr-supply = <&vin>; 164 pwr_sw1-supply = <&bst_out>; 165 pwr_sw2-supply = <&v3v3_ao>; 166 167 vddcpu: buck1 { 168 regulator-name = "vddcpu"; 169 regulator-min-microvolt = <1250000>; 170 regulator-max-microvolt = <1350000>; 171 regulator-always-on; 172 regulator-over-current-protection; 173 174 lp-stop { 175 regulator-suspend-microvolt = <1250000>; 176 }; 177 lplv-stop { 178 regulator-suspend-microvolt = <900000>; 179 }; 180 lplv-stop2 { 181 regulator-off-in-suspend; 182 }; 183 standby-ddr-sr { 184 regulator-off-in-suspend; 185 }; 186 standby-ddr-off { 187 regulator-off-in-suspend; 188 }; 189 }; 190 191 vdd_ddr: buck2 { 192 regulator-name = "vdd_ddr"; 193 regulator-min-microvolt = <1350000>; 194 regulator-max-microvolt = <1350000>; 195 regulator-always-on; 196 regulator-over-current-protection; 197 198 standby-ddr-off { 199 regulator-off-in-suspend; 200 }; 201 }; 202 203 vdd: buck3 { 204 regulator-name = "vdd"; 205 regulator-min-microvolt = <3300000>; 206 regulator-max-microvolt = <3300000>; 207 regulator-always-on; 208 st,mask-reset; 209 regulator-over-current-protection; 210 }; 211 212 vddcore: buck4 { 213 regulator-name = "vddcore"; 214 regulator-min-microvolt = <1250000>; 215 regulator-max-microvolt = <1250000>; 216 regulator-always-on; 217 regulator-over-current-protection; 218 219 lplv-stop { 220 regulator-suspend-microvolt = <900000>; 221 }; 222 lplv-stop2 { 223 regulator-suspend-microvolt = <900000>; 224 }; 225 standby-ddr-sr { 226 regulator-off-in-suspend; 227 }; 228 standby-ddr-off { 229 regulator-off-in-suspend; 230 }; 231 }; 232 233 vdd_adc: ldo1 { 234 regulator-name = "vdd_adc"; 235 regulator-min-microvolt = <3300000>; 236 regulator-max-microvolt = <3300000>; 237 238 standby-ddr-sr { 239 regulator-off-in-suspend; 240 }; 241 standby-ddr-off { 242 regulator-off-in-suspend; 243 }; 244 }; 245 246 unused1: ldo2 { 247 regulator-name = "ldo2"; 248 }; 249 250 unused2: ldo3 { 251 regulator-name = "ldo3"; 252 }; 253 254 vdd_usb: ldo4 { 255 regulator-name = "vdd_usb"; 256 regulator-min-microvolt = <3300000>; 257 regulator-max-microvolt = <3300000>; 258 259 standby-ddr-sr { 260 regulator-off-in-suspend; 261 }; 262 standby-ddr-off { 263 regulator-off-in-suspend; 264 }; 265 }; 266 267 vdd_sd: ldo5 { 268 regulator-name = "vdd_sd"; 269 regulator-min-microvolt = <3300000>; 270 regulator-max-microvolt = <3300000>; 271 regulator-boot-on; 272 273 standby-ddr-sr { 274 regulator-off-in-suspend; 275 }; 276 standby-ddr-off { 277 regulator-off-in-suspend; 278 }; 279 }; 280 281 v1v8_periph: ldo6 { 282 regulator-name = "v1v8_periph"; 283 regulator-min-microvolt = <1800000>; 284 regulator-max-microvolt = <1800000>; 285 286 standby-ddr-sr { 287 regulator-off-in-suspend; 288 }; 289 standby-ddr-off { 290 regulator-off-in-suspend; 291 }; 292 }; 293 294 vref_ddr: vref_ddr { 295 regulator-name = "vref_ddr"; 296 regulator-always-on; 297 298 standby-ddr-sr { 299 regulator-off-in-suspend; 300 }; 301 standby-ddr-off { 302 regulator-off-in-suspend; 303 }; 304 }; 305 306 bst_out: boost { 307 regulator-name = "bst_out"; 308 }; 309 310 v3v3_sw: pwr_sw2 { 311 regulator-name = "v3v3_sw"; 312 regulator-active-discharge = <1>; 313 regulator-min-microvolt = <3300000>; 314 regulator-max-microvolt = <3300000>; 315 }; 316 }; 317 }; 318}; 319 320&iwdg1 { 321 timeout-sec = <32>; 322 status = "okay"; 323}; 324 325&oem_enc_key { 326 st,non-secure-otp-provisioning; 327}; 328 329&pka { 330 status = "okay"; 331}; 332 333&pwr_regulators { 334 vdd-supply = <&vdd>; 335 vdd_3v3_usbfs-supply = <&vdd_usb>; 336}; 337 338&rcc { 339 compatible = "st,stm32mp13-rcc", "syscon"; 340 341 st,clksrc = < 342 CLK_MPU_PLL1P 343 CLK_AXI_PLL2P 344 CLK_MLAHBS_PLL3 345 CLK_RTC_LSE 346 CLK_MCO1_HSE 347 CLK_MCO2_DISABLED 348 CLK_CKPER_HSE 349 CLK_ETH1_PLL4P 350 CLK_ETH2_PLL4P 351 CLK_SDMMC1_PLL4P 352 CLK_SDMMC2_PLL4P 353 CLK_STGEN_HSE 354 CLK_USBPHY_HSE 355 CLK_I2C4_HSI 356 CLK_I2C5_HSI 357 CLK_USBO_USBPHY 358 CLK_ADC2_CKPER 359 CLK_I2C12_HSI 360 CLK_UART1_HSI 361 CLK_UART2_HSI 362 CLK_UART35_HSI 363 CLK_UART4_HSI 364 CLK_UART6_HSI 365 CLK_UART78_HSI 366 CLK_SAES_AXI 367 CLK_DCMIPP_PLL2Q 368 CLK_LPTIM3_PCLK3 369 CLK_RNG1_PLL4R 370 >; 371 372 st,clkdiv = < 373 DIV(DIV_MPU, 1) 374 DIV(DIV_AXI, 0) 375 DIV(DIV_MLAHB, 0) 376 DIV(DIV_APB1, 1) 377 DIV(DIV_APB2, 1) 378 DIV(DIV_APB3, 1) 379 DIV(DIV_APB4, 1) 380 DIV(DIV_APB5, 2) 381 DIV(DIV_APB6, 1) 382 DIV(DIV_RTC, 0) 383 DIV(DIV_MCO1, 0) 384 DIV(DIV_MCO2, 0) 385 >; 386 387 st,pll_vco { 388 pll1_vco_2000Mhz: pll1-vco-2000Mhz { 389 src = <CLK_PLL12_HSE>; 390 divmn = <1 82>; 391 frac = <0xAAA>; 392 }; 393 394 pll1_vco_1800Mhz: pll1-vco-1800Mhz { 395 src = <CLK_PLL12_HSE>; 396 divmn = <1 74>; 397 frac = <0>; 398 }; 399 400 pll1_vco_1300Mhz: pll1-vco-1300Mhz { 401 src = <CLK_PLL12_HSE>; 402 divmn = <2 80>; 403 frac = <0x800>; 404 }; 405 406 pll2_vco_1066Mhz: pll2-vco-1066Mhz { 407 src = <CLK_PLL12_HSE>; 408 divmn = <2 65>; 409 frac = <0x1400>; 410 }; 411 412 pll3_vco_417Mhz: pll3-vco-417Mhz { 413 src = <CLK_PLL3_HSE>; 414 divmn = <1 33>; 415 frac = <0x1a04>; 416 }; 417 418 pll4_vco_600Mhz: pll4-vco-600Mhz { 419 src = <CLK_PLL4_HSE>; 420 divmn = <1 49>; 421 }; 422 }; 423 424 /* VCO = 1300.0 MHz => P = 650 (CPU) */ 425 pll1: st,pll@0 { 426 compatible = "st,stm32mp1-pll"; 427 reg = <0>; 428 429 st,pll = <&pll1_cfg1>; 430 431 pll1_cfg1: pll1_cfg1 { 432 st,pll_vco = <&pll1_vco_1300Mhz>; 433 st,pll_div_pqr = <0 1 1>; 434 }; 435 436 pll1_cfg2: pll1_cfg2 { 437 st,pll_vco = <&pll1_vco_2000Mhz>; 438 st,pll_div_pqr = <0 1 1>; 439 }; 440 441 pll1_cfg3: pll1_cfg3 { 442 st,pll_vco = <&pll1_vco_1800Mhz>; 443 st,pll_div_pqr = <0 1 1>; 444 }; 445 }; 446 447 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 266, R = 533 (DDR) */ 448 pll2: st,pll@1 { 449 compatible = "st,stm32mp1-pll"; 450 reg = <1>; 451 452 st,pll = <&pll2_cfg1>; 453 454 pll2_cfg1: pll2_cfg1 { 455 st,pll_vco = <&pll2_vco_1066Mhz>; 456 st,pll_div_pqr = <1 1 0>; 457 }; 458 }; 459 460 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 461 pll3: st,pll@2 { 462 compatible = "st,stm32mp1-pll"; 463 reg = <2>; 464 465 st,pll = <&pll3_cfg1>; 466 467 pll3_cfg1: pll3_cfg1 { 468 st,pll_vco = <&pll3_vco_417Mhz>; 469 st,pll_div_pqr = <1 16 36>; 470 }; 471 }; 472 473 /* VCO = 600.0 MHz => P = 50, Q = 10, R = 50 */ 474 pll4: st,pll@3 { 475 compatible = "st,stm32mp1-pll"; 476 reg = <3>; 477 st,pll = <&pll4_cfg1>; 478 479 pll4_cfg1: pll4_cfg1 { 480 st,pll_vco = <&pll4_vco_600Mhz>; 481 st,pll_div_pqr = <11 59 11>; 482 }; 483 }; 484 485 st,clk_opp { 486 /* CK_MPU clock config for MP13 */ 487 st,ck_mpu { 488 cfg_1 { 489 hz = <650000000>; 490 st,clksrc = <CLK_MPU_PLL1P>; 491 st,pll = <&pll1_cfg1>; 492 }; 493 494 cfg_2 { 495 hz = <1000000000>; 496 st,clksrc = <CLK_MPU_PLL1P>; 497 st,pll = <&pll1_cfg2>; 498 }; 499 500 cfg_3 { 501 hz = <900000000>; 502 st,clksrc = <CLK_MPU_PLL1P>; 503 st,pll = <&pll1_cfg3>; 504 }; 505 }; 506 }; 507}; 508 509&rng { 510 status = "okay"; 511 clock-error-detect; 512}; 513 514&rtc { 515 status = "okay"; 516}; 517 518&saes { 519 status = "okay"; 520}; 521 522&sdmmc1_io { 523 vddsd1-supply = <&vdd>; 524}; 525 526&sdmmc2_io { 527 vddsd2-supply = <&vdd>; 528}; 529 530&tzc400 { 531 memory-region = <&optee_framebuffer>; 532}; 533 534&uart4 { 535 pinctrl-names = "default"; 536 pinctrl-0 = <&uart4_pins_a>; 537 status = "okay"; 538}; 539 540&usart1 { 541 pinctrl-names = "default"; 542 pinctrl-0 = <&usart1_pins_a>; 543 uart-has-rtscts; 544 status = "disabled"; 545}; 546