1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2021-2022 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/clock/stm32mp13-clksrc.h> 10#include "stm32mp135.dtsi" 11#include "stm32mp13xf.dtsi" 12#include "stm32mp13-pinctrl.dtsi" 13 14/ { 15 model = "STMicroelectronics STM32MP135F-DK Discovery Board"; 16 compatible = "st,stm32mp135f-dk", "st,stm32mp135"; 17 18 aliases { 19 serial0 = &uart4; 20 serial1 = &usart1; 21 }; 22 23 chosen { 24 stdout-path = "serial0:115200n8"; 25 }; 26 27 memory@c0000000 { 28 device_type = "memory"; 29 reg = <0xc0000000 0x20000000>; 30 }; 31 32 reserved-memory { 33 #address-cells = <1>; 34 #size-cells = <1>; 35 ranges; 36 37 optee_framebuffer: optee-framebuffer@dd000000 { 38 /* Secure framebuffer memory */ 39 reg = <0xdd000000 0x1000000>; 40 no-map; 41 }; 42 }; 43 44 vin: vin { 45 compatible = "regulator-fixed"; 46 regulator-name = "vin"; 47 regulator-min-microvolt = <5000000>; 48 regulator-max-microvolt = <5000000>; 49 regulator-always-on; 50 }; 51 52 v3v3_ao: v3v3_ao { 53 compatible = "regulator-fixed"; 54 regulator-name = "v3v3_ao"; 55 regulator-min-microvolt = <3300000>; 56 regulator-max-microvolt = <3300000>; 57 regulator-always-on; 58 }; 59}; 60 61&rcc { 62 compatible = "st,stm32mp13-rcc", "syscon"; 63 64 st,clksrc = < 65 CLK_MPU_PLL1P 66 CLK_AXI_PLL2P 67 CLK_MLAHBS_PLL3 68 CLK_RTC_LSE 69 CLK_MCO1_HSE 70 CLK_MCO2_DISABLED 71 CLK_CKPER_HSE 72 CLK_ETH1_PLL4P 73 CLK_ETH2_PLL4P 74 CLK_SDMMC1_PLL4P 75 CLK_SDMMC2_PLL4P 76 CLK_STGEN_HSE 77 CLK_USBPHY_HSE 78 CLK_I2C4_HSI 79 CLK_USBO_USBPHY 80 CLK_ADC2_CKPER 81 CLK_I2C12_HSI 82 CLK_UART1_HSI 83 CLK_UART2_HSI 84 CLK_UART35_HSI 85 CLK_UART4_HSI 86 CLK_UART6_HSI 87 CLK_UART78_HSI 88 CLK_SAES_AXI 89 CLK_DCMIPP_PLL2Q 90 CLK_LPTIM3_PCLK3 91 CLK_RNG1_PLL4R 92 >; 93 94 st,clkdiv = < 95 DIV(DIV_MPU, 1) 96 DIV(DIV_AXI, 0) 97 DIV(DIV_MLAHB, 0) 98 DIV(DIV_APB1, 1) 99 DIV(DIV_APB2, 1) 100 DIV(DIV_APB3, 1) 101 DIV(DIV_APB4, 1) 102 DIV(DIV_APB5, 2) 103 DIV(DIV_APB6, 1) 104 DIV(DIV_RTC, 0) 105 DIV(DIV_MCO1, 0) 106 DIV(DIV_MCO2, 0) 107 >; 108 109 st,pll_vco { 110 pll1_vco_2000Mhz: pll1-vco-2000Mhz { 111 src = < CLK_PLL12_HSE >; 112 divmn = < 1 82 >; 113 frac = < 0xAAA >; 114 }; 115 116 pll1_vco_1300Mhz: pll1-vco-1300Mhz { 117 src = < CLK_PLL12_HSE >; 118 divmn = < 2 80 >; 119 frac = < 0x800 >; 120 }; 121 122 pll2_vco_1066Mhz: pll2-vco-1066Mhz { 123 src = < CLK_PLL12_HSE >; 124 divmn = < 2 65 >; 125 frac = < 0x1400 >; 126 }; 127 128 pll3_vco_417_8Mhz: pll3-vco-417_8Mhz { 129 src = < CLK_PLL3_HSE >; 130 divmn = < 1 33 >; 131 frac = < 0x1a04 >; 132 }; 133 134 pll4_vco_600Mhz: pll4-vco-600Mhz { 135 src = < CLK_PLL4_HSE >; 136 divmn = < 1 49 >; 137 }; 138 }; 139 140 /* VCO = 1300.0 MHz => P = 650 (CPU) */ 141 pll1: st,pll@0 { 142 compatible = "st,stm32mp1-pll"; 143 reg = <0>; 144 145 st,pll = < &pll1_cfg1 >; 146 147 pll1_cfg1: pll1_cfg1 { 148 st,pll_vco = < &pll1_vco_1300Mhz >; 149 st,pll_div_pqr = < 0 1 1 >; 150 }; 151 152 pll1_cfg2: pll1_cfg2 { 153 st,pll_vco = < &pll1_vco_2000Mhz >; 154 st,pll_div_pqr = < 0 1 1 >; 155 }; 156 }; 157 158 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 266, R = 533 (DDR) */ 159 pll2: st,pll@1 { 160 compatible = "st,stm32mp1-pll"; 161 reg = <1>; 162 163 st,pll = < &pll2_cfg1 >; 164 165 pll2_cfg1: pll2_cfg1 { 166 st,pll_vco = < &pll2_vco_1066Mhz >; 167 st,pll_div_pqr = < 1 1 0 >; 168 }; 169 }; 170 171 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 172 pll3: st,pll@2 { 173 compatible = "st,stm32mp1-pll"; 174 reg = <2>; 175 176 st,pll = < &pll3_cfg1 >; 177 178 pll3_cfg1: pll3_cfg1 { 179 st,pll_vco = < &pll3_vco_417_8Mhz >; 180 st,pll_div_pqr = < 1 16 36 >; 181 }; 182 }; 183 184 /* VCO = 600.0 MHz => P = 50, Q = 10, R = 50 */ 185 pll4: st,pll@3 { 186 compatible = "st,stm32mp1-pll"; 187 reg = <3>; 188 st,pll = < &pll4_cfg1 >; 189 190 pll4_cfg1: pll4_cfg1 { 191 st,pll_vco = < &pll4_vco_600Mhz >; 192 st,pll_div_pqr = < 11 59 11 >; 193 }; 194 }; 195 196 st,clk_opp { 197 /* CK_MPU clock config for MP13 */ 198 st,ck_mpu { 199 200 cfg_1 { 201 hz = < 1000000000 >; 202 st,clksrc = < CLK_MPU_PLL1P >; 203 st,pll = < &pll1_cfg2 >; 204 }; 205 206 cfg_2 { 207 hz = < 650000000 >; 208 st,clksrc = < CLK_MPU_PLL1P >; 209 st,pll = < &pll1_cfg1 >; 210 }; 211 }; 212 }; 213}; 214 215&uart4 { 216 pinctrl-names = "default"; 217 pinctrl-0 = <&uart4_pins_a>; 218 status = "okay"; 219}; 220 221&usart1 { 222 pinctrl-names = "default"; 223 pinctrl-0 = <&usart1_pins_a>; 224 uart-has-rtscts; 225 status = "disabled"; 226}; 227 228&uart8 { 229 pinctrl-names = "default"; 230 pinctrl-0 = <&uart8_pins_a>; 231 status = "disabled"; 232}; 233