18fc45e1eSGatien Chevallier// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 28fc45e1eSGatien Chevallier/* 3*536461adSGatien Chevallier * Copyright (C) STMicroelectronics 2021-2024 - All Rights Reserved 48fc45e1eSGatien Chevallier * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 58fc45e1eSGatien Chevallier */ 68fc45e1eSGatien Chevallier 78fc45e1eSGatien Chevallier#include "stm32mp133.dtsi" 8f55e624aSEtienne Carriere 9f55e624aSEtienne Carriere/ { 10f55e624aSEtienne Carriere soc { 11f55e624aSEtienne Carriere etzpc: etzpc@5c007000 { 12f55e624aSEtienne Carriere ltdc: display-controller@5a001000 { 13f55e624aSEtienne Carriere compatible = "st,stm32-ltdc"; 14f55e624aSEtienne Carriere reg = <0x5a001000 0x400>; 15f55e624aSEtienne Carriere interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 16f55e624aSEtienne Carriere <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 17f55e624aSEtienne Carriere clocks = <&rcc LTDC_PX>; 18f55e624aSEtienne Carriere clock-names = "lcd"; 19f55e624aSEtienne Carriere resets = <&rcc LTDC_R>; 20*536461adSGatien Chevallier access-controllers = <&etzpc STM32MP1_ETZPC_LTDC_ID>; 21f55e624aSEtienne Carriere status = "disabled"; 22f55e624aSEtienne Carriere }; 23f55e624aSEtienne Carriere }; 24f55e624aSEtienne Carriere }; 25f55e624aSEtienne Carriere}; 26