1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2021-2024 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/clock/stm32mp13-clks.h> 8#include <dt-bindings/clock/stm32mp13-clksrc.h> 9#include <dt-bindings/firewall/stm32mp13-etzpc.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/regulator/st,stm32mp13-regulator.h> 12#include <dt-bindings/reset/stm32mp13-resets.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 cpu0: cpu@0 { 23 compatible = "arm,cortex-a7"; 24 device_type = "cpu"; 25 reg = <0>; 26 }; 27 }; 28 29 hse_monitor: hse-monitor { 30 compatible = "st,freq-monitor"; 31 counter = <&lptimer3 1 1 0 0>; 32 status = "disabled"; 33 }; 34 35 intc: interrupt-controller@a0021000 { 36 compatible = "arm,cortex-a7-gic"; 37 #interrupt-cells = <3>; 38 interrupt-controller; 39 reg = <0xa0021000 0x1000>, 40 <0xa0022000 0x2000>; 41 }; 42 43 psci { 44 compatible = "arm,psci-1.0"; 45 method = "smc"; 46 }; 47 48 clocks { 49 clk_hse: clk-hse { 50 #clock-cells = <0>; 51 compatible = "fixed-clock"; 52 clock-frequency = <24000000>; 53 }; 54 55 clk_hsi: clk-hsi { 56 #clock-cells = <0>; 57 compatible = "fixed-clock"; 58 clock-frequency = <64000000>; 59 }; 60 61 clk_lse: clk-lse { 62 #clock-cells = <0>; 63 compatible = "fixed-clock"; 64 clock-frequency = <32768>; 65 }; 66 67 clk_lsi: clk-lsi { 68 #clock-cells = <0>; 69 compatible = "fixed-clock"; 70 clock-frequency = <32000>; 71 }; 72 73 clk_csi: clk-csi { 74 #clock-cells = <0>; 75 compatible = "fixed-clock"; 76 clock-frequency = <4000000>; 77 }; 78 79 clk_i2sin: clk-i2sin { 80 #clock-cells = <0>; 81 compatible = "fixed-clock"; 82 clock-frequency = <19000000>; 83 }; 84 85 }; 86 87 sdmmc1_io: sdmmc1_io { 88 compatible = "st,stm32mp13-iod"; 89 regulator-name = "sdmmc1_io"; 90 regulator-always-on; 91 }; 92 93 sdmmc2_io: sdmmc2_io { 94 compatible = "st,stm32mp13-iod"; 95 regulator-name = "sdmmc2_io"; 96 regulator-always-on; 97 }; 98 99 soc { 100 compatible = "simple-bus"; 101 #address-cells = <1>; 102 #size-cells = <1>; 103 interrupt-parent = <&intc>; 104 ranges; 105 106 usart3: serial@4000f000 { 107 compatible = "st,stm32h7-uart"; 108 reg = <0x4000f000 0x400>; 109 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 110 clocks = <&rcc USART3_K>; 111 resets = <&rcc USART3_R>; 112 status = "disabled"; 113 }; 114 115 uart4: serial@40010000 { 116 compatible = "st,stm32h7-uart"; 117 reg = <0x40010000 0x400>; 118 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 119 clocks = <&rcc UART4_K>; 120 resets = <&rcc UART4_R>; 121 status = "disabled"; 122 }; 123 124 uart5: serial@40011000 { 125 compatible = "st,stm32h7-uart"; 126 reg = <0x40011000 0x400>; 127 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 128 clocks = <&rcc UART5_K>; 129 resets = <&rcc UART5_R>; 130 status = "disabled"; 131 }; 132 133 uart7: serial@40018000 { 134 compatible = "st,stm32h7-uart"; 135 reg = <0x40018000 0x400>; 136 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 137 clocks = <&rcc UART7_K>; 138 resets = <&rcc UART7_R>; 139 status = "disabled"; 140 }; 141 142 uart8: serial@40019000 { 143 compatible = "st,stm32h7-uart"; 144 reg = <0x40019000 0x400>; 145 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 146 clocks = <&rcc UART8_K>; 147 resets = <&rcc UART8_R>; 148 status = "disabled"; 149 }; 150 151 usart6: serial@44003000 { 152 compatible = "st,stm32h7-uart"; 153 reg = <0x44003000 0x400>; 154 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 155 clocks = <&rcc USART6_K>; 156 resets = <&rcc USART6_R>; 157 status = "disabled"; 158 }; 159 160 rcc: rcc@50000000 { 161 compatible = "st,stm32mp13-rcc", "syscon"; 162 reg = <0x50000000 0x1000>; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 #clock-cells = <1>; 166 #reset-cells = <1>; 167 clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>, <&clk_lsi>, <&clk_csi>, <&clk_i2sin>; 168 clock-names = "clk-hse", "clk-hsi", "clk-lse", "clk-lsi", "clk-csi", "clk-i2sin"; 169 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 170 secure-interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 171 secure-interrupt-names = "wakeup"; 172 }; 173 174 pwr_regulators: pwr@50001000 { 175 compatible = "st,stm32mp1,pwr-reg"; 176 reg = <0x50001000 0x10>; 177 178 reg11: reg11 { 179 regulator-name = "reg11"; 180 regulator-min-microvolt = <1100000>; 181 regulator-max-microvolt = <1100000>; 182 }; 183 184 reg18: reg18 { 185 regulator-name = "reg18"; 186 regulator-min-microvolt = <1800000>; 187 regulator-max-microvolt = <1800000>; 188 }; 189 190 usb33: usb33 { 191 regulator-name = "usb33"; 192 regulator-min-microvolt = <3300000>; 193 regulator-max-microvolt = <3300000>; 194 }; 195 }; 196 197 pwr_irq: pwr@50001010 { 198 compatible = "st,stm32mp1,pwr-irq"; 199 status = "disabled"; 200 }; 201 202 syscfg: syscon@50020000 { 203 compatible = "st,stm32mp157-syscfg", "syscon"; 204 reg = <0x50020000 0x400>; 205 }; 206 207 iwdg2: watchdog@5a002000 { 208 compatible = "st,stm32mp1-iwdg"; 209 reg = <0x5a002000 0x400>; 210 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&rcc IWDG2>, <&rcc CK_LSI>; 212 clock-names = "pclk", "lsi"; 213 status = "disabled"; 214 }; 215 216 rtc: rtc@5c004000 { 217 compatible = "st,stm32mp13-rtc"; 218 reg = <0x5c004000 0x400>; 219 clocks = <&rcc RTCAPB>, <&rcc RTC>; 220 clock-names = "pclk", "rtc_ck"; 221 status = "disabled"; 222 }; 223 224 bsec: efuse@5c005000 { 225 compatible = "st,stm32mp13-bsec"; 226 reg = <0x5c005000 0x400>; 227 #address-cells = <1>; 228 #size-cells = <1>; 229 230 cfg0_otp: cfg0_otp@0 { 231 reg = <0x0 0x2>; 232 }; 233 part_number_otp: part_number_otp@4 { 234 reg = <0x4 0x2>; 235 bits = <0 12>; 236 }; 237 monotonic_otp: monotonic_otp@10 { 238 reg = <0x10 0x4>; 239 }; 240 nand_otp: cfg9_otp@24 { 241 reg = <0x24 0x4>; 242 }; 243 uid_otp: uid_otp@34 { 244 reg = <0x34 0xc>; 245 }; 246 hw2_otp: hw2_otp@48 { 247 reg = <0x48 0x4>; 248 }; 249 ts_cal1: calib@5c { 250 reg = <0x5c 0x2>; 251 }; 252 ts_cal2: calib@5e { 253 reg = <0x5e 0x2>; 254 }; 255 pkh_otp: pkh_otp@60 { 256 reg = <0x60 0x20>; 257 }; 258 ethernet_mac1_address: mac1@e4 { 259 reg = <0xe4 0xc>; 260 st,non-secure-otp; 261 }; 262 oem_enc_key: oem_enc_key@170 { 263 reg = <0x170 0x10>; 264 }; 265 }; 266 267 tzc400: tzc@5c006000 { 268 compatible = "st,stm32mp1-tzc"; 269 reg = <0x5c006000 0x1000>; 270 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 271 st,mem-map = <0xc0000000 0x40000000>; 272 clocks = <&rcc TZC>; 273 }; 274 275 tamp: tamp@5c00a000 { 276 compatible = "st,stm32mp13-tamp"; 277 reg = <0x5c00a000 0x400>; 278 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&rcc RTCAPB>; 280 }; 281 282 pinctrl: pin-controller@50002000 { 283 #address-cells = <1>; 284 #size-cells = <1>; 285 compatible = "st,stm32mp135-pinctrl"; 286 ranges = <0 0x50002000 0x8400>; 287 pins-are-numbered; 288 289 gpioa: gpio@50002000 { 290 gpio-controller; 291 #gpio-cells = <2>; 292 interrupt-controller; 293 #interrupt-cells = <2>; 294 clocks = <&rcc GPIOA>; 295 reg = <0x0 0x400>; 296 st,bank-name = "GPIOA"; 297 ngpios = <16>; 298 gpio-ranges = <&pinctrl 0 0 16>; 299 }; 300 301 gpiob: gpio@50003000 { 302 gpio-controller; 303 #gpio-cells = <2>; 304 interrupt-controller; 305 #interrupt-cells = <2>; 306 clocks = <&rcc GPIOB>; 307 reg = <0x1000 0x400>; 308 st,bank-name = "GPIOB"; 309 ngpios = <16>; 310 gpio-ranges = <&pinctrl 0 16 16>; 311 }; 312 313 gpioc: gpio@50004000 { 314 gpio-controller; 315 #gpio-cells = <2>; 316 interrupt-controller; 317 #interrupt-cells = <2>; 318 clocks = <&rcc GPIOC>; 319 reg = <0x2000 0x400>; 320 st,bank-name = "GPIOC"; 321 ngpios = <16>; 322 gpio-ranges = <&pinctrl 0 32 16>; 323 }; 324 325 gpiod: gpio@50005000 { 326 gpio-controller; 327 #gpio-cells = <2>; 328 interrupt-controller; 329 #interrupt-cells = <2>; 330 clocks = <&rcc GPIOD>; 331 reg = <0x3000 0x400>; 332 st,bank-name = "GPIOD"; 333 ngpios = <16>; 334 gpio-ranges = <&pinctrl 0 48 16>; 335 }; 336 337 gpioe: gpio@50006000 { 338 gpio-controller; 339 #gpio-cells = <2>; 340 interrupt-controller; 341 #interrupt-cells = <2>; 342 clocks = <&rcc GPIOE>; 343 reg = <0x4000 0x400>; 344 st,bank-name = "GPIOE"; 345 ngpios = <16>; 346 gpio-ranges = <&pinctrl 0 64 16>; 347 }; 348 349 gpiof: gpio@50007000 { 350 gpio-controller; 351 #gpio-cells = <2>; 352 interrupt-controller; 353 #interrupt-cells = <2>; 354 clocks = <&rcc GPIOF>; 355 reg = <0x5000 0x400>; 356 st,bank-name = "GPIOF"; 357 ngpios = <16>; 358 gpio-ranges = <&pinctrl 0 80 16>; 359 }; 360 361 gpiog: gpio@50008000 { 362 gpio-controller; 363 #gpio-cells = <2>; 364 interrupt-controller; 365 #interrupt-cells = <2>; 366 clocks = <&rcc GPIOG>; 367 reg = <0x6000 0x400>; 368 st,bank-name = "GPIOG"; 369 ngpios = <16>; 370 gpio-ranges = <&pinctrl 0 96 16>; 371 }; 372 373 gpioh: gpio@50009000 { 374 gpio-controller; 375 #gpio-cells = <2>; 376 interrupt-controller; 377 #interrupt-cells = <2>; 378 clocks = <&rcc GPIOH>; 379 reg = <0x7000 0x400>; 380 st,bank-name = "GPIOH"; 381 ngpios = <15>; 382 gpio-ranges = <&pinctrl 0 112 15>; 383 }; 384 385 gpioi: gpio@5000a000 { 386 gpio-controller; 387 #gpio-cells = <2>; 388 interrupt-controller; 389 #interrupt-cells = <2>; 390 clocks = <&rcc GPIOI>; 391 reg = <0x8000 0x400>; 392 st,bank-name = "GPIOI"; 393 ngpios = <8>; 394 gpio-ranges = <&pinctrl 0 128 8>; 395 }; 396 }; 397 398 etzpc: etzpc@5c007000 { 399 compatible = "st,stm32-etzpc", "simple-bus"; 400 reg = <0x5C007000 0x400>; 401 clocks = <&rcc TZPC>; 402 #address-cells = <1>; 403 #size-cells = <1>; 404 #access-controller-cells = <1>; 405 406 adc_2: adc@48004000 { 407 reg = <0x48004000 0x400>; 408 compatible = "st,stm32mp13-adc-core"; 409 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&rcc ADC2>, <&rcc ADC2_K>; 411 clock-names = "bus", "adc"; 412 interrupt-controller; 413 #interrupt-cells = <1>; 414 #address-cells = <1>; 415 #size-cells = <0>; 416 access-controllers = <&etzpc STM32MP1_ETZPC_ADC2_ID>; 417 status = "disabled"; 418 419 adc2: adc@0 { 420 compatible = "st,stm32mp13-adc"; 421 reg = <0x0>; 422 #io-channel-cells = <1>; 423 #address-cells = <1>; 424 #size-cells = <0>; 425 interrupt-parent = <&adc_2>; 426 interrupts = <0>; 427 status = "disabled"; 428 429 channel@13 { 430 reg = <13>; 431 label = "vrefint"; 432 }; 433 434 channel@14 { 435 reg = <14>; 436 label = "vddcore"; 437 }; 438 439 channel@16 { 440 reg = <16>; 441 label = "vddcpu"; 442 }; 443 444 channel@17 { 445 reg = <17>; 446 label = "vddq_ddr"; 447 }; 448 }; 449 }; 450 451 usart1: serial@4c000000 { 452 compatible = "st,stm32h7-uart"; 453 reg = <0x4c000000 0x400>; 454 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 455 clocks = <&rcc USART1_K>; 456 resets = <&rcc USART1_R>; 457 access-controllers = <&etzpc STM32MP1_ETZPC_USART1_ID>; 458 status = "disabled"; 459 }; 460 461 usart2: serial@4c001000 { 462 compatible = "st,stm32h7-uart"; 463 reg = <0x4c001000 0x400>; 464 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&rcc USART2_K>; 466 resets = <&rcc USART2_R>; 467 access-controllers = <&etzpc STM32MP1_ETZPC_USART2_ID>; 468 status = "disabled"; 469 }; 470 471 i2c3: i2c@4c004000 { 472 compatible = "st,stm32mp13-i2c"; 473 reg = <0x4c004000 0x400>; 474 clocks = <&rcc I2C3_K>; 475 resets = <&rcc I2C3_R>; 476 #address-cells = <1>; 477 #size-cells = <0>; 478 st,syscfg-fmp = <&syscfg 0x4 0x4>; 479 i2c-analog-filter; 480 access-controllers = <&etzpc STM32MP1_ETZPC_I2C3_ID>; 481 status = "disabled"; 482 }; 483 484 i2c4: i2c@4c005000 { 485 compatible = "st,stm32mp13-i2c"; 486 reg = <0x4c005000 0x400>; 487 clocks = <&rcc I2C4_K>; 488 resets = <&rcc I2C4_R>; 489 #address-cells = <1>; 490 #size-cells = <0>; 491 st,syscfg-fmp = <&syscfg 0x4 0x8>; 492 i2c-analog-filter; 493 access-controllers = <&etzpc STM32MP1_ETZPC_I2C4_ID>; 494 status = "disabled"; 495 }; 496 497 i2c5: i2c@4c006000 { 498 compatible = "st,stm32mp13-i2c"; 499 reg = <0x4c006000 0x400>; 500 clocks = <&rcc I2C5_K>; 501 resets = <&rcc I2C5_R>; 502 #address-cells = <1>; 503 #size-cells = <0>; 504 st,syscfg-fmp = <&syscfg 0x4 0x10>; 505 i2c-analog-filter; 506 access-controllers = <&etzpc STM32MP1_ETZPC_I2C5_ID>; 507 status = "disabled"; 508 }; 509 510 timers12: timer@4c007000 { 511 #address-cells = <1>; 512 #size-cells = <0>; 513 compatible = "st,stm32-timers"; 514 reg = <0x4c007000 0x400>; 515 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 516 clocks = <&rcc TIM12_K>; 517 clock-names = "int"; 518 access-controllers = <&etzpc STM32MP1_ETZPC_TIM12_ID>; 519 status = "disabled"; 520 521 counter { 522 compatible = "st,stm32-timer-counter"; 523 status = "disabled"; 524 }; 525 }; 526 527 timers13: timer@4c008000 { 528 #address-cells = <1>; 529 #size-cells = <0>; 530 compatible = "st,stm32-timers"; 531 reg = <0x4c008000 0x400>; 532 clocks = <&rcc TIM13_K>; 533 clock-names = "int"; 534 access-controllers = <&etzpc STM32MP1_ETZPC_TIM13_ID>; 535 status = "disabled"; 536 }; 537 538 timers14: timer@4c009000 { 539 #address-cells = <1>; 540 #size-cells = <0>; 541 compatible = "st,stm32-timers"; 542 reg = <0x4c009000 0x400>; 543 clocks = <&rcc TIM14_K>; 544 clock-names = "int"; 545 access-controllers = <&etzpc STM32MP1_ETZPC_TIM14_ID>; 546 status = "disabled"; 547 }; 548 549 timers15: timer@4c00a000 { 550 #address-cells = <1>; 551 #size-cells = <0>; 552 compatible = "st,stm32-timers"; 553 reg = <0x4c00a000 0x400>; 554 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&rcc TIM15_K>; 556 clock-names = "int"; 557 access-controllers = <&etzpc STM32MP1_ETZPC_TIM15_ID>; 558 status = "disabled"; 559 560 counter { 561 compatible = "st,stm32-timer-counter"; 562 status = "disabled"; 563 }; 564 }; 565 566 timers16: timer@4c00b000 { 567 #address-cells = <1>; 568 #size-cells = <0>; 569 compatible = "st,stm32-timers"; 570 reg = <0x4c00b000 0x400>; 571 clocks = <&rcc TIM16_K>; 572 clock-names = "int"; 573 access-controllers = <&etzpc STM32MP1_ETZPC_TIM16_ID>; 574 status = "disabled"; 575 }; 576 577 timers17: timer@4c00c000 { 578 #address-cells = <1>; 579 #size-cells = <0>; 580 compatible = "st,stm32-timers"; 581 reg = <0x4c00c000 0x400>; 582 clocks = <&rcc TIM17_K>; 583 clock-names = "int"; 584 access-controllers = <&etzpc STM32MP1_ETZPC_TIM17_ID>; 585 status = "disabled"; 586 }; 587 588 lptimer2: timer@50021000 { 589 #address-cells = <1>; 590 #size-cells = <0>; 591 compatible = "st,stm32-lptimer"; 592 reg = <0x50021000 0x400>; 593 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 594 clocks = <&rcc LPTIM2_K>; 595 clock-names = "mux"; 596 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM2_ID>; 597 status = "disabled"; 598 }; 599 600 lptimer3: timer@50022000 { 601 #address-cells = <1>; 602 #size-cells = <0>; 603 compatible = "st,stm32-lptimer"; 604 reg = <0x50022000 0x400>; 605 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 606 clocks = <&rcc LPTIM3_K>; 607 clock-names = "mux"; 608 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM3_ID>; 609 status = "disabled"; 610 611 counter { 612 compatible = "st,stm32-lptimer-counter"; 613 status = "disabled"; 614 }; 615 }; 616 617 vrefbuf: vrefbuf@50025000 { 618 compatible = "st,stm32mp13-vrefbuf"; 619 reg = <0x50025000 0x8>; 620 regulator-name = "vrefbuf"; 621 regulator-min-microvolt = <1650000>; 622 regulator-max-microvolt = <2500000>; 623 clocks = <&rcc VREF>; 624 access-controllers = <&etzpc STM32MP1_ETZPC_VREFBUF_ID>; 625 status = "disabled"; 626 }; 627 628 hash: hash@54003000 { 629 compatible = "st,stm32mp13-hash"; 630 reg = <0x54003000 0x400>; 631 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&rcc HASH1>; 633 resets = <&rcc HASH1_R>; 634 access-controllers = <&etzpc STM32MP1_ETZPC_HASH_ID>; 635 status = "disabled"; 636 }; 637 638 rng: rng@54004000 { 639 compatible = "st,stm32mp13-rng"; 640 reg = <0x54004000 0x400>; 641 clocks = <&rcc RNG1_K>; 642 resets = <&rcc RNG1_R>; 643 access-controllers = <&etzpc STM32MP1_ETZPC_RNG_ID>; 644 status = "disabled"; 645 }; 646 647 iwdg1: watchdog@5c003000 { 648 compatible = "st,stm32mp1-iwdg"; 649 reg = <0x5C003000 0x400>; 650 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 651 clocks = <&rcc IWDG1>, <&rcc CK_LSI>; 652 clock-names = "pclk", "lsi"; 653 access-controllers = <&etzpc STM32MP1_ETZPC_IWDG1_ID>; 654 status = "disabled"; 655 }; 656 657 stgen: stgen@5c008000 { 658 compatible = "st,stm32-stgen"; 659 reg = <0x5C008000 0x1000>; 660 access-controllers = <&etzpc STM32MP1_ETZPC_STGENC_ID>; 661 }; 662 }; 663 }; 664}; 665